On the Design of Injection-Locked Frequency Dividers for Mm

ON THE DESIGN OF INJECTION-LOCKED FREQUENCY DIVIDERS FOR MM-

WAVE APPLICATIONS

Lakshmi Lavanya Bodepu

B.Tech., Indian Institute of Technology, Kharagpur, 2016

A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF

THE REQUIREMENTS FOR THE DEGREE OF

MASTER OF APPLIED SCIENCE

THE FACULTY OF GRADUATE AND POSTDOCTORAL STUDIES

(Electrical and Computer Engineering)

THE UNIVERSITY OF BRITISH COLUMBIA

(Vancouver)

Novemeber 2019

The following individuals certify that they have read, and recommend to the Faculty of Graduate and Postdoctoral Studies for acceptance, a thesis entitled:

ON THE DESIGN OF INJECTION-LOCKED FREQUENCY DIVIDERS FOR MM-

WAVE APPLICATIONS

submitted by Lakshmi Lavanya Bodepu in partial fulfillment of the requirements for the degree of Master of Applied Science in Electrical and Computer Engineering

Examining Committee:

Prof. Shahriar Mirabbasi, Electrical and Computer Engineering Supervisor

Prof. Sudip Shekhar, Electrical and Computer Engineering Supervisory Committee Member

Prof. Alireza Nojeh, Electrical and Computer Engineering Supervisory Committee Member

Abstract

This work presents the design and measurement results of two injection-locked frequency dividers (ILFDs) that are intended for mm-wave applications. The two prototypes are fabricated in a 65-nm CMOS process. The first direct-injection ILFD achieves a measured locking range of

24.5 GHz to 43 GHz while consuming 1.3 mW from a 0.48-V supply with a 0 dBm input injection power. The second ILFD design is based on the dual-injection multi-band architecture and as compared to the first design enhances the locking range by a factor of 2. The dual-injection ILFD achieves a locking range of 18 GHz to 61 GHz while consuming 1.8 mW from a 0.5-V supply with a 0 dBm input injection power. The design is optimized to improve the locking range and avoid in-band loss of lock which is a drawback of transformer-based higher order ILFDs.

Furthermore, techniques such as shunt inductor peaking to reduce power consumption and dual- injection of the input signal through a distributed multi-order resonator to improve the locking range are explored and discussed. The best achieved locking range is 108.8 % at 39.5 GHz. The locking range obtained makes the divider suitable for integration in a multi-band mm-wave frequency synthesizer that can support international roaming.

iii

Lay Summary

The increasing demand for mobile phones that can support international roaming is the main driving force behind implementation and deployment of multi-band millimeter-wave (mm- wave) wireless systems. In multi-standard systems, programmable frequency dividers are used to adjust the frequency of the main oscillator to the available bands of interest. Due to portable nature of such applications, power consumption of these dividers should be minimal, and they should not degrade the operation of the main oscillator. In this thesis, the design of two frequency dividers that work on the principle of injection locking are discussed. The two dividers are fabricated, and the integrated circuit prototypes are successfully measured, and their performance is compared with that of the state-of-the-art.

Preface

I am the main contributor to the work presented in this thesis and am responsible for the schematic, layout and the measurements of the two fabricated chips. My supervisor, Professor

Shahriar Mirabbasi, guided me throughout the crucial phases of the research. Professor Sudip

Shekhar has taken part in various fruitful discussions. Mengye Cai helped in the testing of my chips. I am preparing a publication based on the material presented in Chapters 3 and 4 of the thesis.

Table of Contents

Abstract ...... iii

Lay Summary ...... iv

Preface ...... v

Table of Contents ...... vi

List of Tables ...... x

List of Figures ...... xi

List of Abbreviations ...... xiv

Acknowledgements ...... xvi

Dedication ...... xvii

Chapter 1: Introduction ...... 1

1.1 Motivation ...... 1

1.2 Prior-art ...... 4

1.3 Overview ...... 5

Chapter 2: Design of an injection-locked frequency divider ...... 6

2.1 Principle of injection locking in a direct ILFD ...... 6

2.1.1 Effect of quality factor in a direct injection locked divider ...... 8

2.2 Design of a mm-wave ILFD ...... 9

2.2.1 Design of the oscillator LC tank...... 9

2.2.2 Design of the transformer ...... 12

2.2.3 Design of the active devices ...... 15

2.2.3.1 Dimensions and biasing of the injection device...... 15 vi

2.2.3.2 Dimensions of the cross-coupled pair ...... 17

2.3 Design verification ...... 19

2.3.1 Input sensitivity curve ...... 19

2.3.2 Phase slipping in an ILFD...... 20

2.3.3 Increase in the output power with the injection signal...... 21

2.3.4 Locking range for different 푉퐺푆,3 ...... 21

2.3.5 Process voltage temperature (PVT) effects on the locking range (LR) ...... 22

2.3.5.1 Locking range variations with VDD ...... 22

2.3.5.2 Locking range variations with temperature of the devices...... 23

2.3.5.3 Locking range variations with process ...... 23

2.4 Phase noise analysis in an ILFD ...... 24

Chapter 3: Design of multi-band injection-locked frequency divider ...... 27

3.1 Multi-order resonators using transformers...... 27

3.1.1 In-band loss of lock in a transformer based ILFD ...... 29

3.2 Design of a multi-band resonator...... 30

3.2.1 Inductive – peaking to enhance the magnitude response of an RLC tank...... 30

3.2.2 Switchable multi-band resonator ...... 31

3.3 Distributed dual-injection ...... 34

3.3.1 Series peaking of the input mixer...... 37

3.4 Design verification of the multi-band ILFD ...... 37

3.4.1 Overdrive voltage of the injection devices vs locking range ...... 37

3.4.2 Overdrive voltage of the injection devices vs output power...... 39

3.4.3 Advantages of multi - band resonator ...... 39 vii

3.4.2 PVT effects on the locking range ...... 39

3.4.3.1 Locking range variations with VDD ...... 40

3.4.3.2 Locking range variations with process ...... 40

3.4.3.3 Locking range variations with temperature ...... 41

3.4.3 Phase noise simulations: ...... 41

Chapter 4: Measurement results of the two fabricated ILFDs...... 43

4.1 Direct injection locked divider ...... 43

4.1.1 Measurement setup: ...... 43

4.1.2 Measurement results: ...... 47

4.1.2.1 Output spectrum for different frequencies for an input injection power of

0dBm:…………………………………………………………………………………….47

4.1.2.2 Locking range input sensitivity vs VDD: ...... 48

4.1.2.3 Phase noise measurements: ...... 49

4.2 Dual-injection, multi-band ILFD: ...... 50

4.2.1 Measurement setup: ...... 50

4.2.2 Measurement results: ...... 52

4.2.2.1 Output spectrum for different frequencies for an input injection power of

0dBm:…………………………………………………………………………………….52

4.2.2.2 Output power vs overdrive voltage of the injection devices ...... 54

4.2.2.3 Locking range vs overdrive voltage of the injection devices ...... 54

4.2.2.4 Input sensitivity vs VDD: ...... 55

4.2.2.5 Phase noise measurements: ...... 55

4.3 Performance comparison of dual-injection multi-band ILFD with the state-of-the-art 57 viii

Chapter 5: Conclusion ...... 59

5.1 Future work - injection locked multiplier...... 59

Bibliography ...... 61

List of Tables

Table 1.1 Comparison of high frequency dividers...... 3

Table 2.1 Comparison of different inductors ...... 11

Table 2.2 Dimensions of the cross-coupled pair ...... 18

Table 4.1 Performance summary and comparison table ...... 57

List of Figures

Figure 1.1 High frequency dividers (a) CML divider. (b) Miller divider. (c) ILFD...... 2

Figure 2.1 (a) Direct ILFD. (b) Phasor addition of currents. (c) Maximum phase when 퐼푡 and

퐼푚푖푥 are perpendicular. (d) Phase response of an RLC tank with frequency. (e) Magnitude response of an RLC tank with frequency...... 6

Figure 2.2 (a) SP analysis of the spiral inductor and a fixed parallel capacitance. (b) Equivalent model of the spiral inductor. (c) Equivalent RLC parallel tank...... 9

Figure 2.3 A direct injection locked frequency divider with a transformer for output buffer...... 14

Figure 2.4 Magnitude response of 푍푖푛 with frequency for different 푉퐺푆,3...... 15

Figure 2.5 Phase response of 푍푖푛 with frequency for different 푉퐺푆,3...... 16

Figure 2.6 Magnitude response of 푍푖푛 with frequency for different 푊3...... 16

Figure 2.7 Phase response of 푍푖푛 with frequency for different 푊3...... 16

Figure 2.8 Simulated input sensitivity curve ...... 19

Figure 2.9 Increase of Pin at Fin = 30 GHz ...... 20

Figure 2.10 Increase of Pin at 43 GHz ...... 21

Figure 2.11 LR vs VGS of M3...... 22

Figure 2.12 LR vs VDD ...... 22

Figure 2.13 LR vs temperature ...... 23

Figure 2.14 LR vs process ...... 23

Figure 2.15 Simulated phase noise for Fin=25GHz ...... 26

Figure 2.16 Simulated phase noise for Fin=34GHz...... 26

Figure 3.1 (a) RLC Tank (b) Transformer (c) Phase improvement (d) Magnitude response ...... 27

Figure 3.2 Magnitude response with varying k in a simple transformer...... 28 xi

Figure 3.3 Phase response with varying k in a simple transformer...... 29

Figure 3.4 In-band loss of lock in a transformer based ILFD...... 30

Figure 3.5 (a) Peaking differential inductors (b) Peaking center-tapped inductors ...... 31

Figure 3.6 Inductive peaking in an LC tank ...... 31

Figure 3.7 Magnitude response with (a) L1 (b) C1 (c) L (d) C (e) L1 (SW on) (f) L (SW on) ... 33

Figure 3.8 (a) Schematic of the dual-injection multi-band ILFD. (b) Improvement in ϕ from dual injection...... 34

Figure 3.9 Layout model of the dual-injection based multi-band ILFD...... 35

Figure 3.10 Magnitude response of Zin ...... 36

Figure 3.11 Phase response of Zin...... 36

Figure 3.12 Simulated locking range for dual-injection ...... 37

Figure 3.13 Magnitude response of Zin for different 푉퐺푆,3,4 ...... 38

Figure 3.14 Locking range vs overdrive voltage of the injection devices ...... 38

Figure 3.15 Output power vs overdrive voltage of the injection devices ...... 39

Figure 3.16 Locking range vs VDD; process = TT, temperature = 70 C ...... 40

Figure 3.17 Locking range vs process; VDD = 0.55 V, temperature = 70 C ...... 40

Figure 3.18 Locking range vs temperature; VDD = 0.55 V, process = TT ...... 41

Figure 3.19 Simulated phase noise for Fin=26 GHz with SW off...... 42

Figure 3.20 Simulated phase noise for Fin=34 GHz with SW on...... 42

Figure 4.1 Die micrograph of the direct ILFD ...... 43

Figure 4.2 Measurement setup...... 45

Figure 4.3 Block diagram of the measurement setup for the direct ILFD...... 46

Figure 4.4 Measured spectrum for Fin=37GHz, Fout=18.5GHz, VDD=0.48V, VGS=0.5V...... 47 xii

Figure 4.5 Span=1MHz, resolution bandwidth (RBW) = 10 KHz at 18.5 GHz...... 47

Figure 4.6 Measured spectrum for Fin=43 GHz, Fout=21.5 GHz, VDD=0.48 V, VGS=0.5 V. .. 48

Figure 4.7 Measured input sensitivity curve ...... 48

Figure 4.8 Measured phase noise for Fin=25GHz ...... 49

Figure 4.9 Measured phase noise for Fin=30GHz...... 49

Figure 4.10 Die micrograph of the dual-injection based multi-band ILFD...... 50

Figure 4.11 Block diagram of the measurement setup for the multi-band ILFD...... 51

Figure 4.12 Measured spectrum for Fout = 8.5 GHz for VDD = 0.52 V, VGS = 0.51 V ...... 52

Figure 4.13 Measured spectrum for Fout = 18 GHz for VDD = 0.5V VGS = 0.51V...... 52

Figure 4.14 Spectrum at Fout =18 GHz and VDD = 0.5 V, VGS = 0.45 V ...... 53

Figure 4.15 Measured spectrum for Fout = 28 GHz (2 GHz from the mixer)...... 53

Figure 4.16 Output power vs 푉퐺푆 for VDD=0.5V...... 54

Figure 4.17 Locking range vs overdrive voltage of the injection devices for VDD=0.5 V...... 54

Figure 4.18 Input sensitivity curve ...... 55

Figure 4.19 Measured phase noise at Fout=13GHz ...... 55

Figure 4.20 Measured phase noise at Fout=17GHz ...... 56

Figure 5.1 Injection locked multiplier ...... 60

xiii

List of Abbreviations

AC Alternating current

CAD Computer aided design

CMOS Complementary metal oxide semi-conductor

DC Direct current (0 Hertz)

Fin Input frequency

FOM Figure of merit

Fout Output frequency

Freq Frequency

GHz Giga-Hertz gm Transconductance of a transistor

Hz Hertz (unit of frequency)

IF Intermediate frequency

ILFD Injection locked frequency divider

LR Locking range

LO Local oscillator

MHz Mega-hertz

Mm milli-meter nH nano-Henry

PN Phase noise

Q Quality factor

RF Radio frequency sp scattering-parameters xiv

µm micro-meter

Vth Threshold voltage

VGS Gate to source voltage

Vov Overdrive voltage

Acknowledgements

I offer my enduring gratitude to Professor Shahriar Mirabbasi for his support in the research, guidance, and financial support.

I would like to take this opportunity to acknowledge Professor Sudip Shekhar, Mengye

Cai, Chen Yuan, Spoorthi.G.Nayak, Ajith.S.Ramani for their valuable suggestions.

I would also like to thank Dr, Roberto Rosales and Roozbeh Mehrabadi for providing measurement and CAD support.

Finally, I am greatly indebted to my family members and my friends for their constant moral support.

xvi

Dedication

I dedicate this thesis to my family and my friends.

xvii

Chapter 1: Introduction

1.1 Motivation

Increasing demand for higher speeds of data transfer and wireless communications with wider bandwidth are driving the exploration of millimeter wave (mm-wave) transceivers. One of the main advantages of operating at mm-wave frequencies is the availability of more bandwidth in such frequency bands, which, in turn facilitates delivering faster, higher quality data (e.g., video, and multimedia content). Many chip design companies in field of wireless communications are developing mm-wave systems designed for the currently licensed 24 GHz and 28 GHz bands that are allotted to 5th generation (5G) of wireless systems. These bands are allocated by the Federal

Communications Commission in the United States and other licensed bands of 37 GHz, 39 GHz and 47 GHz are expected to become available soon [1]. The 60 GHz band or commonly known as the V-Band is getting a lot of attention for short-range wireless applications such as Wireless

Gigabit (WiGig) technology which can communicate up-to data rates of 8 Gb/s. A transceiver that can support multiple bands of 5G technology can be greatly advantageous for International roaming and is of high-interest. Therefore, designing multi-band mm-wave transceivers is an active area of research. In such transceivers, the frequency synthesizer is one of the critical building block as it must generate clocks and local oscillators that provide all the required frequencies of operation.

In a multi-band phase-locked loop (PLL), not only the voltage-controlled oscillator (VCO) but also the first stage frequency divider must also be able to operate at all the above-mentioned bands of interest while consuming minimum power. The divider should also present a minimal load capacitance to the VCO. Therefore, proper divider design, especially at mm-wave frequencies, is critical. 1

Figure 1.1 High frequency dividers (a) CML divider. (b) Miller divider. (c) ILFD.

At frequencies beyond 10 GHz, the digital dividers in a typical 65-nm CMOS process run into timing violations because of the parasitic capacitance and process limitations. Thus, usually digital dividers are replaced by different high frequency dividers as shown in the Figure 1.1 especially at mm-wave frequencies. The inductor-less current-mode-logic (CML) dividers (Figure

1.1(a)) are very similar to digital dividers where the CML latches are the delay cells that replace the conventional complementary metal oxide semi-conductor (CMOS) latches. As compared to digital dividers, CML dividers occupy less area and have a wider locking range i.e., the range of frequencies of operation, but provide a very limited process dependent highest frequency of operation. Techniques such as inductor peaking with current reuse and gm boosting are employed to increase the frequency of operation and reduce the power consumption of such dividers [2].

Recent CML dividers with dynamic latches employ techniques such as load modulation [3] and self-calibration [4] to increase the operating frequency but power consumption is still high for the obtained locking range. Regenerative or Miller dividers [5], [6] (Figure 1.1(b)) work on the principle of filtering the higher harmonics after the mixer stage, allowing only the fundamental frequency in the loop. The filter can be either a passive or an active filter. They consume less power in comparison to CML dividers and can operate at higher frequencies but with a limited locking range. Injection locked frequency dividers (ILFDs) [7], [8], [9] (Figure 1.1(c)) which make use of injection locking in an oscillator support wider locking ranges for lower power consumption.

Table 1.1 summarizes the advantages and disadvantages of different high-frequency dividers. Due to their lower power consumption, wider locking range and lower supply voltage requirements,

ILFDs are mostly employed at mm-wave frequencies.

Table 1.1 Comparison of high frequency dividers.

CML dividers Miller dividers ILFD

Pros • Wide locking range • High operating frequency • High operating

• Low Area • Low Power frequencies

• Low Power

• Wide Locking Range

• Can be Tuning-less

Cons • Limited Frequency • Limited Locking Range • Higher Area

Operation • Higher Area

• High Power

Consumption

1.2 Prior-art

Among the previously proposed ILFDs, direct-injection ILFDs proved to acquire improved locking range than the indirect ILFD [7], [9], [10]. In a direct ILFD, the injection current is directly driven into the tank as opposed to the injection through the current source device in a conventional indirect-ILFD. In addition to direct injection, techniques like dual-injection through direct injection and indirect injection through coupling capacitor to the LC-tank at the common source of the oscillator [11], adaptive coupling to enhance the phase [12], frequency tracking to adopt the admittance locus with the input frequency[13] have increased the locking range. Distributed injection locking makes use of more than one injection device proved to acquire multiple bands of locking range [14]. Series peaking with a transformer feedback is used to enhance the voltage swings at the drain and source of the injection device and thereby increasing the mixer current

[15].

Finally, the transformer based multi-order resonators use the phase ripple to increase the locking range to 62 % at a center frequency of 40 GHz [16]. However, inaccurate calculations of coupling-coefficient, post-silicon variations in the passive elements can lead to an in-band loss-of- lock.

The in-band loss-of-lock can be problematic if continuous range of frequencies is desired.

The output power will be minimum for frequencies in between the two peaks in a transformer- based higher-order resonator. Hence, the goal of the thesis was to improve the locking range and avoid the in-band loss of lock while minimizing the power consumption from the voltage supply and at the same time maximizing the output power at all the frequencies of operation.

1.3 Overview

The proposed transformer less multi-band injection locked divider in this thesis offers a switchable multi-band operation. The first band itself provides a continuous locking range from

18 GHz to 61GHz. The second band can be helpful if higher output signal strength is desired within the intermediate band of interest thereby solving the problem of low output power at the frequencies in between the peaks. Further, techniques like shunt inductor peaking to reduce power consumption and dual-injection of the input signal to improve the locking range are discussed in this thesis. Chapter 2 explains the effects of Quality factor, design of the injection device in a direct

ILFD with a simple prototype. Chapter 3 discusses the injection locking in higher-order resonators and the design of the proposed multi-band, dual-injection ILFD to improve the locking range at mm-wave frequencies. Chapter 4 provides the measurement results of the two prototypes fabricated in 65 nm CMOS process. Chapter 5 concludes the paper and briefly describes the future work.

Chapter 2: Design of an injection-locked frequency divider

To improve the locking range of an ILFD, it would be useful to revisit the principle of injection locking and its operation in a divider. This is the purpose of the following section.

2.1 Principle of injection locking in a direct ILFD

Figure 2.1 (a) Direct ILFD. (b) Phasor addition of currents. (c) Maximum phase when 푰풕

and 푰풎풊풙 are perpendicular. (d) Phase response of an RLC tank with frequency. (e)

Magnitude response of an RLC tank with frequency.

In a simple direct-injection locked divider as shown in the Figure 2.1, the injection is at the gate of a transistor placed between the output nodes of the oscillator as opposed to the injection 6

through the current source device in a conventional indirect-ILFD. The injection device acts like a single transistor mixer (푀) where the input signal (푉,) is the radio-frequency port and the drains of the cross-coupled pair form the interchangeable local-oscillator and intermediate- frequency ports (푉,). The higher harmonic component at 3ω is rejected by the tank which is tuned for ω. Therefore, at steady state the oscillator locks to only ω frequency.

The phasor diagram of the currents( Figure 2.1(b)) in the system helps analyzing ILFD at steady- state and the operating frequency ω. The cross-coupled pair current from the transconductance gain (푔,) of the cross-coupled pair (푀 and 푀) is represented by 퐼, and the current from the mixer 푀 is denoted by 퐼, (푔, × 푉,). 퐼, is at a phase shift of θ with 퐼,.

The phasor addition of the two currents result in the tank current 퐼, at a phase difference of ϕ

with the 퐼,. Ideally in a free running oscillator resonating at 휔, 퐼, is the same as 퐼, allowing the tank to oscillate at its peak magnitude where the phase difference is 0° and the output voltage is given by

푉, = 푍 × 퐼, ( 1 )

But in the case of injection locking, since there is a phase difference ϕ in the current entering the tank, the tank should be able to compensate for the phase difference and bring back the system to a 360 closed loop phase response. In other words, the tank is now forced to oscillate at a frequency ω where the phase response is −ϕ as shown in the Figure 2.1(d) and the resultant output voltage is given by

푉, = 푍 × 퐼, ( 2 )

Reference [17] has proved that for a given 퐼, and a 퐼, the maximum value of ϕ is

achieved when the currents 퐼, and 퐼,, are at 90° apart (Figure 2.1(c)) and is given by

, 휙 = 푠푖푛 ( 3 ) ,

The locking range referred to the input is given by

, ω, ∝ ( 4 ) , where 푄 is the quality factor of the tank.

2.1.1 Effect of quality factor in a direct injection locked divider

At first glance, Equation (4) might lead us to believe that to improve the locking range one should decrease the quality factor of the tank; however, this equation does not depict the whole picture. To further explain, a low 푄 tank can be employed to flatten the phase response of the tank. However, this will result in the decrease of the magnitude response or the parallel resistance

(푅) of the tank. To compensate for the lower 푅, the gm of the cross-coupled pair can be improved by

1. Increasing the overdrive voltage of 푀, which results in lower gate to source

voltage (푉) of 푀 and 퐼, degrading the locking range.

2. Increasing the width of the cross-coupled pair which worsens the parasitic

capacitance in the tank. At mm-wave frequencies, it's always desired to keep the

capacitance low to keep the quality factor from the capacitance (푄) high.

To summarize, while designing an ILFD, the quality factor of the tank is kept not too low.

The quality factor (푄) from an inductor is given by

∗ 푄 = ( 5 ) and the equivalent parallel resistance can be approximated to

푅, =ω× 퐿 × 푄 ( 6 )

Increasing the L while maintaining a small series resistance improves the 푄 and results in high 푅, and thereby low power needed to start the oscillation. The increase in the series resistance with the number of turns is not exactly linear and the quality factor improves with higher number of turns in the inductor up to a certain number of turns. However, this may also increase the parallel capacitance. However, by opting for higher spacing between the turns and not very large width of the inductor, the parasitic capacitance is lowered and thereby, improving 푄.

2.2 Design of a mm-wave ILFD

2.2.1 Design of the oscillator LC tank.

Figure 2.2 (a) SP analysis of the spiral inductor and a fixed parallel capacitance. (b)

Equivalent model of the spiral inductor. (c) Equivalent RLC parallel tank.

In a mm-wave ILFD, the design of a moderate quality factor tank is the crucial step. To compare the inductors and their quality factors, a fixed estimated parasitic capacitance 퐶 from

the active devices and the metal interconnects is placed parallel to the spiral inductor as shown in the Figure 2.2 (a). Figure 2.2 (b) shows the equivalent model of the spiral inductor. The 푅, captures the series resistance at DC and the skin effect resistance at higher frequencies (the current only flows through a thinner shell of the outer surface as the frequency of operation increases).

The 푅, captures the substrate resistance in series with the substrate capacitance (퐶). 퐶 represents the fringe capacitance of the spiral inductor. Finally, the spiral inductor along with 퐶 can be represented as an 푅퐿퐶 parallel Tank. In order to estimate the values of 푄, 푅, 퐿, impedance Z-Parameters across the port A are simulated using Scattering Parameter (SP) Analysis in Cadence Spectre. The 푍 of the 푅퐿퐶 tank is given by

푍, = ( 7 )

푅푒(푍) = ( 8 )

( ) 퐼푚(푍) = ( 9 )

At ω=ω, 퐶 = and

푅 = 푅푒푍, ( 10 )

∗ 퐿 = , ( 11 ) , ∗

푄 = ( 12 ) ×

where ω is the resonating frequency at which 퐼푚(푍) = 0.

To choose the appropriate value of the inductor, the resonant frequencies of the tanks with

퐶 should be similar. The first chip is designed for a free running frequency of 18 GHz which

requires the product of (퐿 × 퐶) to be equal to 7.8 × 10 퐻푧 . For a tuning less ILFD without a varactor or switchable capacitor banks, the parasitic capacitance is kept as low as possible. With estimated 퐶 value approximately 30 fF, the inductance is chosen closer to 1 nH - 1.5 nH. The value of 퐿 and 푄 are estimated near the ω from the equations (7), (8), (9) and the SP Analysis.

Table 2.1 compares the characteristics of different monolithic inductors in our target technology which we will use for choosing the initial values of the tank.

Table 2.1 Comparison of different inductors

Inner Width Resonating 퐿 푅 Area(µ푚 ) Turn 푄 radius(µm) (µm) freq. (GHz) (nH) ()

2 70 20 19.3 1.1 16.8 1970 312272

2 80 15 18.2 1.3 20 2287 305272

3 30 15 18 1.17 20.3 2298 243210

3 40 6 18 1.4 30 3880 196176

3 45 4 17.1 1.6 32 3951 191174

From Table 2.1, the following inferences can be drawn for the tanks with similar resonant frequencies of the spiral inductor and the C ,

1. Smaller widths of the inductor for a fixed number of turns(N) do not impact the 푄

significantly.

2. Higher N improves the 푄 for similar inductance values.

3. High values of 푅 are achieved from N=3 and within smaller area of the inductor.

To save power and not compromise on the quality factor, a 3-turn inductor with a width of

6 µm is chosen for the ILFD. The inductor value is close to 1.4 nH at 18 GHz. The quality factor of 30 produces a very sharp magnitude response but when the tank is placed parallel to the injection device 푀, the effective magnitude and the phase responses flatten depending on the dimensions and the biasing of the 푀: the linear region resistance from 푀 is parallel to the tank.

2.2.2 Design of the transformer

A single turn secondary coil is added on the Metal 6 (M6) below the three turn M9 primary coil to drive the output buffer which reduces the layout complexity and the quality factor of the tank slightly. Since it’s a single turn secondary coil, the parasitic capacitance introduced is less and the secondary inductance is of very low value and has less impact on the response of the tank.

The electromagnetic (EM) simulations are performed to calculate the impedances of the transformer using a 3D-planar EM simulation tool by Keysight Technologies called Advanced

Design System (ADS)-Momentum that uses finite element analysis to solve Maxwell’s equations.

The s-parameters from the momentum are captured in the cadence schematic and post-layout simulations using an n-port in the Cadence Spectre view.

The values of Lp, Ls and the coupling coefficient are given by the expressions (12) – (18). The s- parameter analysis of the primary coil as port 1 and the secondary coil as port 2 (Figure 2.3) help estimate the inductance values. 12

∗ 퐿 = ( 13 ) , ∗

∗ 퐿 = , ( 14 ) , ∗

푅 = 푅푒푍, , ( 15 )

푅 = 푅푒푍, , ( 16 )

푄 = , ( 17 ) ∗

∗[,,] 푀 = ( 18 ) ,, ∗

k= ( 19 ) ×

The secondary inductance is estimated to be 0.2 nH at 18 GHz and the 푄 is slightly reduced from 30 to 27. The Mutual Inductance (M) is about 0.5 nH at 18 GHz and the coupling coefficient is estimated to be 0.9. The first peak in the magnitude response is estimated to be near

18GHz and the second peak near 50 GHz, which is far from the frequencies of interest. Hence the divider can still be considered a single order resonator within the 10 GHz to 20 GHz. In other words, there is no phase ripple created (Chapter 3.1). The small reduction in the quality factor widens the phase response of the tank and at the same time not hike the power consumption greatly.

The layout model of the direct ILFD designed is more elaborately shown in the Figure 2.3.

A bias-tee couples the external injection signal from an RF source (AC) with the appropriate DC biasing for the Injection device. A 50  polysilicon resistance (푅) is placed at the gate of the injection device 푀 to properly terminate the input signal from the external signal source and avoid any reflections at high frequencies of operation.

Figure 2.3 A direct injection locked frequency divider with a transformer for output

buffer.

2.2.3 Design of the active devices

A direct injection locked oscillator from a nMOS cross-coupled pair without a bias current source minimizes the power consumption [16]. The current source can be safely removed without any considerable effect on the phase noise (PN): In injection locking, the locked oscillator’s noise profile mostly adopts that of the input signal. Moreover, the transistors do not enter deep triode region as the minimum voltage at the drains do not reach a low of 0V or the overall peak-peak swings are at least not designed for twice the supply voltage (VDD) in the present design.

However, a voltage regulator is strongly recommended for better power supply noise rejection.

2.2.3.1 Dimensions and biasing of the injection device.

There is a design trade-off between the 푅, (linear resistance of 푀 when the transistors

푀 and 푀 are in saturation region) and the 푔,. The 푅, is in parallel with the tank. 푅, can be maximized with lower width and higher overdrive voltage of 푀 but there is a penalty on the mixer gain. Figure 2.4, Figure 2.5 display the magnitude and phase response from the simulated sp-analysis of Zin (Figure 2.4Figure 2.3) in Cadence Spectre for different Gate-Source bias voltages of 푀when VDD is fixed.

Figure 2.4 Magnitude response of 풁풊풏 with frequency for different 푽푮푺,ퟑ.

Figure 2.5 Phase response of 풁풊풏 with frequency for different 푽푮푺,ퟑ.

Figure 2.6 Magnitude response of 풁풊풏 with frequency for different 푾ퟑ. show the simulated sp-analysis results of Zin for different widths of 푀 and a fixed minimum length.

Figure 2.6 Magnitude response of 풁풊풏 with frequency for different 푾ퟑ.

Figure 2.7 Phase response of 풁풊풏 with frequency for different 푾ퟑ. 16

The Figures 2.4 - 2.7 explain the following:

1. Increasing 푉, flattens the phase response (Figure 2.5) but lowers the

magnitude response (Figure 2.4). This narrows the locking range since the

divider will not oscillate near the boundary frequencies due to insufficient 푅.

2. Increasing the 푊, (Figure 2.6, Figure 2.7) has the same influence as of 푉,

on the locking range and worsens the load capacitance for the VCO. Hence a

width of 10 µm is chosen for 푀 .

2.2.3.2 Dimensions of the cross-coupled pair

While designing the cross-coupled pair,

1. The dimensions of the cross-coupled pair 푀 and 푀 are to be chosen so that

2/푔,, is at least two - three times smaller than the resultant parallel resistance

of 푅 from the transformer and the equivalent linear-region resistance of

푀푅, when both the cross-coupled transistor pair are in saturation region.

2. The ratio of 푔, (α [(2/π) × 푔,] ) to 푔,, determines the maximum

phase (ϕ) for the locking range assuming the voltage swings of the input

2휔 and the output 휔 are similar. Increasing 푔,, can drop the locking range.

The total injection current into the tank (퐼,) is the sum of the mixer current (퐼,) from 푉, and the transconductance current from the 푉, [13].

퐼, = 푔, ∗ 푉, + 푔, × 푉, ( 20 )

Assuming similar 푉, and 푉, (~ 0dBm). The maximum phase which is 푠푖푛 of the ratio of 퐼, and 퐼, can be approximated to

,, ϕ α si푛 ( 21 ) ,,

Where 푔, α [(2/π) ∗ 푔,].

Table 2.2 estimates the 푔,, and ϕ for different widths of 푀, using the gm/Id analysis for 푉,,=0.5V and 푊=10 µm with lengths of the transistors minimum at 60 nm.

Table 2.2 Dimensions of the cross-coupled pair

ϕ = 푠푖푛 푔 + 푔 / 푊, 푔,, 푔,+ 푔, , ,

(µm) (mSiemen) (mSiemen) 푔,, (degrees)

8 5.811 4.627+0.836 70

10 7.269 4.627+0.836 49

12 8.727 4.627+0.836 40

From the Table 2.2, it is inferred that even though the ϕ is higher for smaller 푊, but the loop gain in the oscillator may not be sufficient for boundary frequencies and the divider’s locking range will be limited. Therefore, a width of 10 µm, where (2/푔,,) is 휙 can be

approximated to 50 and -2/푔,, is close to -275  which is way smaller than the 400  at ω.

(Note that in a free running oscillator it is required that -2/푔,, be at least two times less than the peak magnitude but in an injection locked oscillator, the injection current also contributes to oscillation.)

2.3 Design verification

The measurement setup should be captured in the simulations for better post-layout verification. The RF probes’ passive models (for high frequency signal pads), wire-bond models

(for DC signal pads), the off-chip bias-tee models are calculated from their respective data-sheets and included in the post layout simulations.

2.3.1 Input sensitivity curve

The input sensitivity curve is a measure of how strong of an injection signal is required to lock the oscillator at a frequency ∆ω from the peak frequency of the oscillator ω . At the peak frequency, with a minimum external injection signal the oscillator locks. As the frequency is drifted from ω, the external injection power must be increased.

Figure 2.8 captures the simulated input sensitivity curve for different VDD but the 푉, is kept constant at 0.5V. The x-axis represents the frequency of the input signal and the y-axis represents the injection power of the 2ω signal.

Figure 2.8 Simulated input sensitivity curve

From the Figure 2.8, following inferences can be drawn.

1. With VDD, the locking range improves. However, there is a penalty on the

power consumption.

2. The DC bias voltage of 푀 must be increased to keep 푡ℎ푒 푉, constant and

may cause gate-oxide breakdown.

2.3.2 Phase slipping in an ILFD

Phase slipping in the ILFD occurs when the oscillator has enough loop gain but insufficient injection power to properly lock the phase of the oscillator. The input injection signal power

(푃) can be strengthened to alleviate the phase slipping in the ILFD (Figure 2.9).

Figure 2.9 Increase of Pin at Fin = 30 GHz

2.3.3 Increase in the output power with the injection signal.

Near the boundary frequencies of the locking range, the external injection can be helpful to boost the oscillator output (Figure 2.10).

Figure 2.10 Increase of Pin at 43 GHz

2.3.4 Locking range for different 푽푮푺,ퟑ

The post layout simulations help in estimating the locking range for fixed VDD = 0.5 V and different overdrive voltages of the injection device 푉,. The results further emphasize that there is a tradeoff in increasing 푉, with the locking range.

Figure 2.11 LR vs VGS of M3

2.3.5 Process voltage temperature (PVT) effects on the locking range (LR)

The target 65-nm CMOS design kit has three process corners: SS (slow slow for nMOS and pMOS transistors plus passive devices, FF (fast fast), and TT (typical typical). The temperature of the device models is varied using the temperature parameter in Cadence simulation environment.

2.3.5.1 Locking range variations with VDD

Figure 2.12 LR vs VDD

VDD = 0.45V: LR = 22 GHz - 42 GHz, VDD = 0.5V: LR = 21 GHz - 43.5 GHz and VDD

= 0.55V: LR = 20.3 GHz - 44.5 GHz 22

2.3.5.2 Locking range variations with temperature of the devices.

Figure 2.13 LR vs temperature

Temp = -40C: LR = 20.8 GHz - 44.5 GHz, Temp = 70C: LR = 21 GHz - 43.5 GHz and

Temp = 120C: LR = 21.2 GHz - 42.5 GHz.

2.3.5.3 Locking range variations with process

Figure 2.14 LR vs process

Process = SS: LR = 23 GHz - 42 GHz, Process = TT: LR = 21 GHz - 43.5 GHz and Process

= FF: LR = 19 GHz - 44.8 GHz.

Following conclusions can be drawn from the Figure 2.12, Figure 2.13, Figure 2.14 :

1. The locking range drops with the power supply.

2. The locking range is less for SS corner when the transistors are slow, and the

loop gain is less for the oscillations along with lower mixer current.

3. Increase in temperature degrades the locking range.

4. Overall, the PVT variations in the locking range are within 10%.

2.4 Phase noise analysis in an ILFD

Intuitively, the jitter of the divider must be the same as that of the input signal as the transitions of the oscillator output are dependent on the input transition. The carrier frequency is changed from 2ω to ω resulting in a phase noise improvement of 6 dB since the jitter is same.

Reference [18] has derived the noise transfer function from output noise to the output phase.

For a given input signal 푣(푡), output signal 푣(푡), output noise signal 푣(푡), [18] derived the noise transfer function from output noise to the output phase.

푣(푡) = 푉푐표푠(ω푡) ( 22 )

푣(푡) = 푉푐표푠(휔푡 + 훳 ) ( 23 )

푣(푡) = 푉푐표푠(휔 + 휔)푡 + 훳 ( 24 )

The input (휃)-output (훳) phase difference can be written as

훳 = 휃 + 휃 ( 25 )

And the noise transfer function is

+ 푐표푠(휃) 휃 = 푐표푠(휃) 푠푖푛(휔푡 + 휃) ( 26 )

where 퐴 = and N=2 for divide by 2.

The noise from the incident signal is shaped by the low-pass characteristic of the noise transfer function, and the output signal tracks the phase variations of the incident signal within the

loop bandwidth 푐표푠(휃) . The loop bandwidth is larger for a higher input signal amplitude

푉. Within the loop bandwidth, the noise from the ILFD is suppressed by the ratio of the noise power to the incident power. Outside the loop bandwidth, the noise suppression increases by 20 dB per decade of offset frequency. The (1/N) in the Equation (25) translates to 20푙표푔(2) =6푑퐵 improvement in a divide by 2 ILFD. However, within certain MHz, the phase noise settles to a floor because of the buffer noises and the intrinsic divider noise.

In order to estimate the noise bandwidth within which the 6 dB phase noise improvement is observed, a PSS-Phase Noise analysis in Cadence is simulated for the post-layout netlist. One port in a Vector Network Analyzer (67GHz Keysight N5227A PNA) is used as the input signal source.

The phase noise at 25 GHz is measured using the Phase Noise Tester / Noise Analyzer 7000 Series

BNC. The data is fed into the simulation using a port. The simulated output phase noise is shown in the Figure 2.15. The estimated noise floor frequency is 6 MHz and a 6 dB phase noise improvement is observed at 1 MHz offset. If the noise floor is much less than the input phase noise, the 6dB difference is observed beyond 6 MHz. (Figure 2.16)

Figure 2.15 Simulated phase noise for Fin=25GHz

Figure 2.16 Simulated phase noise for Fin=34GHz.

Chapter 3: Design of multi-band injection-locked frequency divider

Multi-band injection locked dividers achieve wider locking ranges [19] in comparison to single-band resonators. The multiple bands can be created either from switchable capacitor banks or higher order resonators. The capacitive banks should be of high quality factor and might introduce unwanted parasitic. Therefore, in the proposed design, the multi-band is created from a higher order resonator and avoided any capacitor banks.

3.1 Multi-order resonators using transformers

Figure 3.1 (a) RLC Tank (b) Transformer (c) Phase improvement (d) Magnitude response

Injection locked dividers using multi-order resonators have multiple advantages [20], the first being the creation of a ripple in the phase response of the tank. To further explain, in higher order resonators such as a simple transformer shown in Figure 3.1, the magnitude response of the

tank Zt has multiple peaks because there can be more than one frequency at which the magnitude reaches its maximum and hence there is a phase ripple created if the peaks are closer.

The ripple in the phase response helps in extending the locking range as larger range of frequencies can be locked within the same ϕ. The red shaded region shows the locking range of a transformer which is much larger than the LC tank (blue region).

The phase ripple from a transformer is highly dependent on the coupling coefficient (k) between the primary (LP) and the secondary coils (LS). An sp-analysis of a simple transformer with LP =

LS = 1 nH and CP = CS = 50 fF and RP = RS = 1 K with different values of k is simulated. The

frequency span between the peaks ω = , ω = in the ××() ××() magnitude response of Zt vary with the value of k (Figure 3.2) and thereby the phase ripples

(Figure 3.3). The locking range improves with k as more frequencies are observed with in the same phase range. However, there is a limitation on the value of k which is explained in the next section.

Figure 3.2 Magnitude response with varying k in a simple transformer.

Figure 3.3 Phase response with varying k in a simple transformer.

ILFDs using transformers proved to achieve high locking ranges [16]. However, there are few drawbacks pertained to a transformer design including

a. Increase in the parasitic capacitance because of which smaller inductors are to

be chosen to keep the Resonant frequency same.

b. The Electromagnetic simulations must be very rigorous to avoid any

mismatches in the post-silicon fabricated die.

c. The quality factor is reduced depending on the layout of the transformer and the

d. Can cause in band loss of lock.

3.1.1 In-band loss of lock in a transformer based ILFD

The in-band loss of lock is the range of frequencies that the oscillator does not lock with in the expected band of the locking range [16]. This happens if either the phase or the magnitude requirements are not met. (Figure 3.4). The blank spaces in the shaded region of red represents the in-band loss of lock. The reasons include

1. Improper modelling of the coupling coefficient (k).

2. Post-silicon variations in the passive elements which might alter the magnitude

and the phase response of the tank.

Figure 3.4 In-band loss of lock in a transformer based ILFD.

Therefore, the aim of this work is to create a multi-order PVT resilient ILFD without an in-band loss of lock.

3.2 Design of a multi-band resonator.

The proposed multi-band ILFD in this thesis has been designed to create a higher-order resonator without the use of a transformer, thereby minimizing rigorous EM simulations but still benefitting from the multiple peaks to create phase ripple and enhance the locking range.

3.2.1 Inductive – peaking to enhance the magnitude response of an RLC tank.

Shunt inductor peaking technique [16] is often used to improve the magnitude response of the RLC tank (Figure 3.5). The additive inductance heightens the effective magnitude response of

Zt within a certain frequency range after which C1 overhauls, dropping the magnitude. Figure 3.6 displays the simulated magnitude response of Zt for L1= L2 = 250 pH of quality factor 10 at 20

GHz and C1 = 25 fF to the RLC (1 nH, 50 fF, 500 ) tank. Even though the peak frequency drops slightly, there is about 40 % improvement in the magnitude.

Figure 3.5 (a) Peaking differential inductors (b) Peaking center-tapped inductors

Figure 3.6 Inductive peaking in an LC tank

3.2.2 Switchable multi-band resonator

The inductors L1 and L2 in Figure 3.5(a) are two terminal differential inductors but if they are transformed to three terminal center-tapped inductors, a multi-order resonator with a distributed LC Oscillator can be created (Figure 3.5 (b)). The third terminal (center tap) is

connected to the RLC tank. Further, the tank’s magnitude response can be altered using the switch

SW thereby forming a “switchable multi-band resonator”. The distributed ILFD has other benefits like dual injection which is explained in the Chapter 3.3.

Simulating the tank with ideal values of L1, L2, L, estimated parasitic capacitance and parallel resistance assist in approximate the peak frequencies (SW on and off) and the span between them. For the initial values of L = 1.2 nH, L1 = L2 = L1′ = L2′ = 600 pH and C1 =

C2 = C = 30 fF, the two peak frequencies are at 17.5 GHz, 24 GHz and 31 GHz which are quite close to one another and can create switchable multi-order resonators. Therefore, if the peak frequencies are properly designed for overlaps in the bands, the problem of in-band loss of lock can be avoided.

Figure 3.7 displays the magnitude response of Zt for varying values of the inductance and capacitance. The nominal values are L = 1.2 nH, L1 = L2 = L1′ = L2′ = 600 pH and C1 =

C2 = C = 30 fF.

1. The values of L1 and C1 affect both the peak frequencies when SW is off.

2. The values of L and C impact only the lower peak when the SW is off. At higher

frequencies the points A and B are shorted to VDD because of higher parallel

capacitance of LC and the tank is dominated by L1.

3. When the SW is turned on, the tank’s magnitude response is dependent on both

L1 and L

4. The value of C1 affects the magnitude response more significantly than L1.

Figure 3.7 Magnitude response with (a) L1 (b) C1 (c) L (d) C (e) L1 (SW on) (f) L (SW on)

3.3 Distributed dual-injection

The second injection device 푀 transforms the oscillator to a distributed dual injection locked frequency divider as the injection is applied at two points 푀 and 푀. The two injection currents accumulate to an enlarged mixer current and hence higher ϕ. (Figure 3.8(b))

Figure 3.8 (a) Schematic of the dual-injection multi-band ILFD. (b) Improvement in 훟

from dual injection.

The layout model of the multi-band ILFD is shown in the Figure 3.9. The output signals to the buffers are tapped from the peaking inductors: The gate capacitance of the buffers is not directly contributed to the oscillator.

Figure 3.9 Layout model of the dual-injection based multi-band ILFD. 35

For the inductor values of L1+ L1′ = 700 pH, L=1.3 nH, and an injection device of size

10um and the cross coupled pair of sizes 10um (Chapter 2.2.3 explained the sizing of the transistors and similar sizes proved to present the highest locking range in this design as well), VDD = 0.55

V, 푉,, = 450 푚푉, the peaks are closer to 14 GHz , 20 GHz, 27 GHz for the magnitude response of Zin. (Figure 3.10, Figure 3.11).

Figure 3.10 Magnitude response of Zin

Figure 3.11 Phase response of Zin.

3.3.1 Series peaking of the input mixer.

The 퐿 placed in series with 푀 acts like a series inductor peaking [21] for the LO and the

IF ports of the mixer and strengthens the mixing of the input injection signal with the output signal.

To further prove the point, the ILFD is simulated with and without the dual-injection and the locking ranges are presented in the Figure 3.12. There is a discontinuity in the locking range if there is only one injection device.

Figure 3.12 Simulated locking range for dual-injection

3.4 Design verification of the multi-band ILFD

3.4.1 Overdrive voltage of the injection devices vs locking range

The post-layout magnitude response of 푍 for different overdrive voltages of the injection devices ( 푉,, ) and VDD = 0.55 V (Figure 3.13) prove that as 푉,, drops, the magnitude response near the peaks improve but the 푖 decreases thereby shrinking the locking range which is also proved from the measurements (Chapter 4.2.2.3).

Figure 3.13 Magnitude response of Zin for different 푽푮푺,ퟑ,ퟒ

The simulated locking range vs 푉,, for both SW on and off when VDD=0.55 V is displayed in the Figure 3.14. There is a continuous locking range obtained when the SW is turned off with appropriate biasing of the injection devices and the cross-coupled pair.

Figure 3.14 Locking range vs overdrive voltage of the injection devices

3.4.2 Overdrive voltage of the injection devices vs output power

The output signal is amplified for lower 푉,, near the peak frequencies: The effective resistance of the injection device increases boosting the effective parallel resistance of Zin.

Figure 3.15 Output power vs overdrive voltage of the injection devices

3.4.3 Advantages of multi - band resonator

The output signal for frequencies in between the two peaks (SW being turned off) can be strengthened by shifting the oscillator to a second state (SW turned on). In this case, there is no longer a significant dual injection but can still provide injection locking within the frequency range

32 GHz - 50 GHz. Post layout simulations show an improvement of 150mV in the peak-peak output voltage at 48GHz from SW being turned off to turned on. Further, the input injection signal can be alleviated in the 40 GHz to 50 GHz from SW being turned off to turned on proved by the measured input sensitivity curve. (Chapter 4.2.2.4)

3.4.2 PVT effects on the locking range

The post layout simulations help us estimate the error that can be accrued in the locking range due to PVT variations.

3.4.3.1 Locking range variations with VDD

With VDD, the Locking range improves but there is a penalty on power consumption.

Moreover, the improvement is not linear with VDD and hence it’s not optimum to hike the power supply.

Figure 3.16 Locking range vs VDD; process = TT, temperature = 70 C

3.4.3.2 Locking range variations with process

Figure 3.17 Locking range vs process; VDD = 0.55 V, temperature = 70 C

There is a discontinuity in the locking range for SS which can be alleviated by hiking the power supply.

3.4.3.3 Locking range variations with temperature

Figure 3.18 Locking range vs temperature; VDD = 0.55 V, process = TT

3.4.3 Phase noise simulations:

The post layout noise analysis for both states of the ILFD (SW off and SW on) are performed using Cadence PSS and Pnoise analysis. At 1 MHz, there is an expected 6 dB improvement from the divider (Figure 3.19).

Figure 3.19 Simulated phase noise for Fin=26 GHz with SW off.

Figure 3.20 Simulated phase noise for Fin=34 GHz with SW on.

Chapter 4: Measurement results of the two fabricated ILFDs.

4.1 Direct injection locked divider

The direct injection locked divider which is optimized for the locking range of 21GHz to

43GHz achieves a measured locking range of 24.5 GHz to 43 GHz for an average power consumption of 1.3 mW from a 0.48 V supply and 0 dBm input injection power.

The area of the core circuit is 160 × 200 µ푚.

Figure 4.1 Die micrograph of the direct ILFD

4.1.1 Measurement setup:

The chip is directly mounted on the Printed Circuit Board (PCB) which is commonly known as Chip on board (COB) configuration. The PCB design is layed out using Altium Design tool. The DC signal pads are wire-bonded to the PCB whereas probes are used for both the input and the output RF signal pads. Figure 4.11 represents the measurement setup for the ILFD1. 43

1. The input signal is from an internal PLL in the port 1 of the Agilent Technologies

VNA (10 MHz - 67 GHz).

2. The Bias-Tee (0 - 65 GHz) couples the AC signal from the VNA with the DC signal

from the power supply to properly bias the injection device (푀).

3. The output spectrum is analyzed using a Rhode & Schwarz FSW Spectrum

Analyzer (2 Hz - 26.5 GHz).

4. The phase noise of the output signal is measured using BNC Phase Noise

Tester/Analyzer.

5. For the input signals between the 26 GHz and 40 GHz the phase noise is analyzed

using a harmonic mixer which mixes the 8th harmonic of LO with the RF signal.

For example, if the RF signal is 28 GHz and the LO is 3.25 GHz then the IF is

28 퐺퐻푧 – 8 × 3.25 퐺퐻푧 = 2 퐺퐻푧. The LO signal is fed from the Holzworth

RF synthesizer.

Figure 4.2 Measurement setup.

Figure 4.3 Block diagram of the measurement setup for the direct ILFD.

4.1.2 Measurement results:

4.1.2.1 Output spectrum for different frequencies for an input injection power of 0dBm:

Figure 4.4 Measured spectrum for Fin=37GHz, Fout=18.5GHz, VDD=0.48V, VGS=0.5V.

Figure 4.5 Span=1MHz, resolution bandwidth (RBW) = 10 KHz at 18.5 GHz. 47

Figure 4.6 Measured spectrum for Fin=43 GHz, Fout=21.5 GHz, VDD=0.48 V, VGS=0.5 V.

4.1.2.2 Locking range input sensitivity vs VDD:

Figure 4.7 Measured input sensitivity curve

The locking range improves with VDD. 48

4.1.2.3 Phase noise measurements:

There is a 6dB phase noise improvement from the divider as shown in the Figure 4.8,

Figure 4.9 The phase noise settles to a floor around 2 MHz.

Figure 4.8 Measured phase noise for Fin=25GHz

Figure 4.9 Measured phase noise for Fin=30GHz.

The ripples in the output phase noise are because of the improper buffer design and decoupling-capacitors on the PCB which is rectified in the multi-band ILFD measurement.

4.2 Dual-injection, multi-band ILFD:

The multi-band ILFD achieves the best measured locking range of 18 GHz to 61 GHz while consuming a power of 1.8mW from a 0.5V supply. The core circuit’s area is about 270 × 440 µ푚.

Figure 4.10 Die micrograph of the dual-injection based multi-band ILFD.

4.2.1 Measurement setup:

The block diagram for the measurement setup is shown in the Figure 4.11 .

1. The measurement setup is the same as that of the direct ILFD except for few

RF connectors and cables.

2. The output signals above 26 GHz are down converted using the harmonic mixer

and analyzed. 50

Figure 4.11 Block diagram of the measurement setup for the multi-band ILFD. 51

4.2.2 Measurement results:

4.2.2.1 Output spectrum for different frequencies for an input injection power of 0dBm:

Figure 4.12 Measured spectrum for Fout = 8.5 GHz for VDD = 0.52 V, VGS = 0.51 V

Figure 4.13 Measured spectrum for Fout = 18 GHz for VDD = 0.5V VGS = 0.51V.

Figure 4.14 Spectrum at Fout =18 GHz and VDD = 0.5 V, VGS = 0.45 V

Figure 4.15 Measured spectrum for Fout = 28 GHz (2 GHz from the mixer). 53

퐹 = 3.25 GHz and the second harmonic is at 6.5 GHz.

4.2.2.2 Output power vs overdrive voltage of the injection devices

Figure 4.16 Output power vs 푽푮푺 for VDD=0.5V.

As expected, the output signal strengthens with lower overdrive voltage of the injection devices.

4.2.2.3 Locking range vs overdrive voltage of the injection devices

Figure 4.17 Locking range vs overdrive voltage of the injection devices for VDD=0.5 V. 54

There is a continuous locking range for VDD=0.5V and 푉,, = 0.51 V.

4.2.2.4 Input sensitivity vs VDD:

Figure 4.18 Input sensitivity curve

4.2.2.5 Phase noise measurements:

Figure 4.19 Measured phase noise at Fout=13GHz 55

The 6dB improvement from the divider is proved from the measurements. And the ripples are alleviated with proper placement of de-coupling capacitors on PCB.

Figure 4.20 Measured phase noise at Fout=17GHz

4.3 Performance comparison of dual-injection multi-band ILFD with the state-of-the-art

Table 4.1 Performance summary and comparison table

Y.Chao A.Imani J.Zhang This Work

(JSSC 2013) (JSSC 2017) (JSSC 2018) [16]

[13] [14]

Topology Frequency Distributed 4th-Order Multi-band

Tracking Transformer-Based plus Dual

Injection

Process 65nm CMOS 130nm SiGe 65nm CMOS 65nm CMOS

Input Freq (GHz) at 53.4–79.4 35-59.5 32.3-61.9 18-61

0dBm input power

Locking Range (%) 39.2 53 62.7 108.8

PN diff (dBc/Hz) at

100KHz 6 6 6 6

1MHz 6 0# 6 6

Supply Voltage (V) 0.8 1.15 0.42 0.5

Power ILFD only (mW) 2.9 3.8 1.2 1.8

Core Area (mm2) 0.126 0.046 0.07 0.119

FoM¥ (GHz/mW-1) 15.8 13.94 52.25 60.4

# Captured from the measurement phase noise plot.

¥ FoM=Locking Range (%) / Power.

The comparison table also supports the claim that the proposed dual-injection, multi- band ILFD achieves the widest locking range at mm-wave frequencies with a power consumption of 1.8 mW from a 0.5-V supply.

Chapter 5: Conclusion

This thesis explored and discussed design procedures for mm-wave injection-locked frequency dividers that achieve large locking ranges at lower power consumption. At first, the design procedures for the tank and the active devices in a direct-injection locked frequency divider were elaborated. The aim is to flatten the phase response of the tank to enhance the locking range while not dropping the magnitude response of the effective tank and the injection device. This helps lowering the power consumption and operate at lower supply voltages. Proof-of-concept prototypes confirm that the first design which is a simple direct ILFD achieves a locking range of about 18.5 GHz (24.5 to 43 GHz) within a core-circuitry silicon area of 160 × 200 µ푚.

The locking range is further improved by a factor of 2 (18 to 61 GHz) in the second design based on the dual-injection multi-band architecture. This widened locking range enables the dual- injection ILFD to be used in a multi-band mm-wave PLL. The key idea in the design is to transform the differential peaking inductors to three terminal center-tapped inductors and create a distributed multi-order resonator. The switch (SW) further transforms the ILFD to a switchable multi-band resonator. Finally, the second injection device 푀 provides an increase in the injection current into the tank thereby enhancing the locking range.

The multi-band ILFD achieves its best locking range of 108.8% at 39.5 GHz in a 65-nm

CMOS process while consuming 1.8 mW from a 0.5-V supply.

5.1 Future work - injection locked multiplier.

The concepts of injection locking can be extended to multipliers [22] in which the oscillator locks to the third harmonic of the input injection signal through transformer coupling.

The idea is that the fundamental frequency (ω) of the input signal when mixed with its second harmonic (2ω) generates the desired third harmonic (3ω) [23] and a transformer couples this mixer output (3ω) for injection locking of an nMOS cross-coupled oscillator (푀 and 푀).

The oscillator when injection locked, resonates at a frequency of 3ω denoted by Vout,3ω.

The 2ω current (I, 2ω) is obtained from the common drain of the input amplifiers ((푀 and 푀).) and is given to the pMOS mixer (푀 and 푀) through the common source. To strengthen the current at 2ω, a tank formed from the inductance (L) is added at the common-source node of the mixer [24] and the VDD2. The schematic for the proposed design for an output locking range of

36 GHz to 47 GHz is presented in the Figure 5.1.

Figure 5.1 Injection locked multiplier

Bibliography

[1] S.Onoe, "Evolution of 5G Mobile Technology Toward 2020 and Beyond," in IEEE

International Solid State Circuits Conference, 2016.

[2] K.H. Tsai, J.H. Wu and S.I. Liu, "Frequency dividers with enhanced locking range," in

IEEE Radio Frequency Integrated Circuits Symposium, June 2008.

[3] A. Ghilioni, A. Mazzanti and F. Svelto, "Analysis and design of mm-Wave frequency

dividers based on dynamic latches with load modulation," IEEE Journal of Solid-State

Circuits, vol. 48, no. 8, pp. 1842-1850, August 2013.

[4] A. I. Hussein and J. Paramesh, "Design and self-calibration techniques for inductor-less

millimeter-wave frequency dividers," IEEE Journal of Solid-State Circuits,, vol. 52, no. 6,

pp. 1521-1541, June 2017.

[5] J. Lee and B. Razavi, "A 40-GHz frequency divider in 0.18um 65nm CMOS technology,"

IEEE Journal of Solid-State Circuits,, vol. 39, no. 4, pp. 594-601, April 2004.

[6] Y. Lin and H. Wang, "A 35.7–64.2 GHz low power Miller divider with weak inversion

mixer in 65 nm CMOS," IEEE Microwave Wireless Component Letters, vol. 26, no. 11, pp.

948-950, November 2016.

[7] M. A. Tiebout, "A CMOS direct injection-locked oscillator topology as high-frequency

low-power frequency divider," IEEE Journal of Solid State Circuits, vol. 39, no. 7, pp.

1170-1174, July 2004.

[8] C.C. Chen, H.W. Tsao and H. Wang, "Design and analysis of CMOS frequency dividers

with wide input locking ranges," IEEE Transactions on Microwave Theory and

Techniques, vol. 57, no. 12, pp. 3060-3069, December 2009.

[9] C.Y. Wu and C.Y. Yu, "Design and analysis of a millimeter-wave direct injection-locked

frequency divider with large frequency locking range," IEEE Transactions on Microwave

Theory and Techniques, vol. 55, no. 8, pp. 1649-1658, August 2007.

[10] W.L. Chen, et al, "A 53.6 GHz direct injection-locked frequency divider with a 72%

locking range in 65 nm CMOS technology," in IEEE MTT-S International Microwave

Symposium Digest , June 2013.

[11] T.-N. Luo and Y.-J. E.Chen, "A 0.8-mW 55-GHz dual-injection-locked CMOS frequency

divider," IEEE Transactions on Microwave Theory and Techniques, vol. 56, no. 3, pp. 620-

625, March 2008.

[12] H. Wang, et al, "A 60 GHz wideband injection-locked frequency divider with adaptive-

phase-enhancing technique," in IEEE Radio Frequency Integrated Circuits Symposium,

2011.

[13] Y. Chao and H. C. Luong, "Analysis and design of a 2.9-mW 53.4–79.4-GHz frequency-

tracking injection-locked frequency divider in 65-nm CMOS," IEEE Journal of Solid State

Circuits, vol. 48, no. 10, pp. 2403-2418, October 2013.

[14] A. Imani and H. Hashemi, "Distributed injection-locked frequency dividers," IEEE Journal

of Solid State Circuits, vol. 52, no. 8, pp. 2083-2093, August 2017.

[15] Y.H. Wong, W.H. Lin, J.H. Tsai and T.W. Huang, "A 50-to-62 GHz wide-locking-range

CMOS injection-locked frequency divider with transformer feedback," in IEEE Radio

Frequency Integrated Circuits Symposium, June 2008.

[16] J. Zhang, Y. Cheng, C. Zhao, Y. Wu and K. Kang, "Analysis and Design of Ultra-

Wideband mm-Wave Injection-Locked Frequency Dividers Using Transformer-Based

High-Order Resonators," IEEE Journal of Solid State Circuits, vol. 53, no. 8, pp. 2177-

2189, 2018.

[17] B. Razavi, "A study of injection locking and pulling in oscillators," IEEE Journal of Solid

State Circuits, vol. 39, no. 9, pp. 1415-1424, September 2004 .

[18] H. Rategh and T. Lee, "Superharmonic injection-locked frequency dividers," IEEE Journal

of Solid State Circuits, vol. 34, no. 6, pp. 813 - 821, June 1999.

[19] A. Buonomo and A. L. Schiavo, "A study of injection locking in dual-band CMOS

frequency dividers," IEEE Transactions on Circuits and Systems Regular Papers, vol. 65,

no. 5, pp. 1225-1234, May 2017.

[20] K. Takatsu, et al, "A 60-GHz 1.65mW 25.9% locking range multi-order LC oscillator

based injection locked frequency divider in 65 nm CMOS," in IEEE Custom Integrated

Circuits Conference, September 2010.

[21] J.C. Chien and L.H. Lu, "40GHz Wide-Locking-Range Regenerative Frequency Divider

and Low-Phase-Noise Balanced VCO in 0.18μm CMOS," in IEEE Solid-State Circuits

Conference, 2007.

[22] J. Zhang, H. Liu, C. Zhao and K. Kang, "A 22.8-to-43.2GHz Tuning-Less Injection-

Locked Frequency Tripler Using Injection-Current Boostingwith 76.4% Locking Range for

Multiband 5G Applications," in IEEE International Solid-State Circuits Conference

(ISSCC), 2018.

[23] S. Z. A. Li, X. L. J. Yin and H. C. Luong, "A 21–48 GHz subharmonic injection-locked

fractional-n frequency synthesizer for multiband point-to-point backhaul communications,"

IEEE Journal of Solid State Circuits, vol. 49, no. 8, pp. 1785-1799, August 2014.

[24] A. Masnadi, R. M. A. Nikpaik, S. Mirabbasi and S. Shekhar, "A class-C self-mixing-VCO

architecture with high tuning range and low phase-noise for mm-wave applications," in

IEEE Radio Frequency Integrated Circuits Symposium, 2015.