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Reference Injected Phase-Locked Loops (PLL-Ris) Feiran Lei, Student Member, IEEE, and Marvin H

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Reference Injected Phase-Locked Loops (PLL-Ris) Feiran Lei, Student Member, IEEE, and Marvin H IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS 1 Reference Injected Phase-Locked Loops (PLL-RIs) Feiran Lei, Student Member, IEEE, and Marvin H. White, Life Fellow, IEEE Abstract—In this paper, we use synchronization to reduce Phase-Locked Loop (PLL) phase noise and improve its locking behavior with an attenuated reference signal injection (RI) into a voltage controlled CMOS delay-line ring-type oscillator. The transient and steady-state behavior of the PLL-RI are described by a nonlinear differential equation, which is further studied by the phase-plane method. The nonlinear equation is linearized for the small-signal condition and the s-domain noise transfer functions and noise bandwidths for different noise sources are derived. The effect of the loop parameters and the injection strength on the output phase noise, loop settling time, and lock in range is analyzed. Finally, the analysis is verified by the SPICE simulation and measurement results from an 1-GHz PLL- RI with 130nm standard RF CMOS technology. Simulation and (a) (b) measurement results show phase noise reduction and improved settling behavior of a PLL-RI compared to a conventional PLL. Fig. 1. Simplified system block diagrams for (a) a Reference Injected Phase- Locked Loop (PLL-RI) and (b) a Phase-Locked Loop (PLL) Index Terms—Phase-Locked Loops (PLLs), synchronization, CMOS ring oscillators, phase noise suppression, noise bandwidth. phase noise up to an offset of 1MHz [3]. If we consider these challenges, then new methodologies are needed to overcome these limitations. The driving force in almost all PLLs is I. INTRODUCTION an oscillator, therefore, a good understanding of oscillation- YNCHRONOUS clocking circuits, with their primary based phenomena, such as injection locking – which is a very S impact on modern practical computing systems, have useful and interesting phenomenon that happens in numerous been a significant contributor to the overall advancement physical systems especially in electronic oscillators – can be of communication technologies. It is typical in synchronous helpful in solving these problems. circuits to use a reference clock signal in a feedback control The injection locking technique, characterized by its simple loop to stabilize both frequency and phase, resulting in a structure and low noise performance in an oscillator design, phase-locked loop (PLL) architecture. Due to the rapid growth has been investigated by researchers. By comparing the os- of the CMOS technology, high-frequency, high-speed, low- cillator with a high stability reference signal source, injection noise and low-cost PLLs have become crucial elements in locking will cause the oscillator to be phase locked to the a variety of communication applications. In a typical PLL, reference source. Van Der Pol [4] first introduced the injection the total output phase noise is the summation of the low of an external signal to an oscillator to control its frequency; passed reference noise and Phase Detector (PD) noise, and however, the signal level was large and tended to ’quench’ the high passed Voltage Controlled Oscillator (VCO) noise, the output amplitude. Adler [5] developed a small signal therefore, an optimal noise performance can be achieved by model for the tracking and non-tracking characteristics of the properly selecting the loop bandwidth to suppress the noise injection locking phenomena where signal injection was at from the VCO, the PD, and the reference. However, the VCO low levels to modulate the phase only. Adler’s work provided noise becomes more difficult to suppress as its frequency a strong foundation for the subsequent work on injection- increases [1]. We could use a wider bandwidth to suppress locked oscillators [6]–[9]. In particular, injection locking is more VCO noise, but the loop stability may be affected and used widely in injection-locked clock multipliers (ILCMs) to more PD noise and input noise will be included. This is achieve superior phase noise over a PLL [6]. Runge [7] in especially a challenge in today’s nano-scaled processes where 1976 developed a reference injected (RI), discrete component, the low frequency noise (LFN), which arises from the random PLL with an analog multiplier PD and LC oscillator for use in capture and release of electrons by traps located in and near the Undersea Lightwave Systems, which have been in use since gate dielectric, is of concern, especially in high-K dielectrics 1988 in the Atlantic Ocean and 1989 in the Pacific Ocean. with large number of traps [2]. LFN in the device baseband However, the full potential of this method to improve the noise affects the oscillating frequency and dominates the measured and settling performance of Charge-Pump PLLs has yet to be analyzed and implemented in an integrated CMOS circuit The work is supported by the National Science Foundation ECCS #1201656 under program director Dimitris Pavlidis. technology. F. Lei is with the Department of Electrical and Computer Engineering, the We have applied the injection locked Synchronous Oscil- Ohio State University, Columbus, OH, 43202 USA (e-mail: [email protected]) lator (SO) [8] with voltage control capability to a modified M. H. White is with the Department of Electrical and Computer En- gineering, the Ohio State University, Columbus, OH, 43202 USA (e-mail: Charge-Pump (CP) PLL to replace the conventional VCO, as [email protected]) shown in Fig. 1. The Charge-Pump PLL, which employs a Digital Object Identifier: 10.1109/TCSI.2017.2668298 1558-0806 c 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications standards/publications/rights/index.html for more information. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS 2 nonlinear discriminator to aid the frequency acquisition [10], is an improvement over the phase comparator-type early PLLs in that it also provides a frequency error output as well as a phase error, so the PLL capture range is only limited by the VCO output frequency range. It also generates a coherent output phase as the CP together with a passive integrable filter is capable to provide a pole at the origin so as to increase the order of the type of the PLL. Based on Runge’s method [7], the injection signal is derived directly from the attenuated Fig. 2. Linearized models of a delay-line oscillator with low-level injection reference signal without additional circuit implementations. – synchronous oscillator (SO) Compared to a PLL, the new system, named a Reference Injected PLL (PLL-RI), provides further noise suppression and cycle, and the energy is restored to the resonator during the improved locking behavior. The phase noise shaping functions edges rather than at the voltage maxima [11]. In this paper, of a PLL-RI are formulated mathematically. PLL-RI provides a delay-line, ring-type CMOS oscillator architecture for the flexible design trade-offs by decoupling 3dB loop bandwidths VCSO is adopted to provide a large tuning range in a fully for different noise sources. integrated PLL. This paper is organized in the following manner. The next section theoretically analyzes the PLL-RI system from the aspect of dynamic equations to study its locking condition A. SO Dynamic Phase Equation and settling behavior. The phase noise of the PLL-RI with Modified from the linearized model of a delay-line oscil- noise contributions from different sources – reference/injection lator [12], Fig. 2 shows a linearized model of an N-stage signal, PFD/CP, and VCO, is described in Section III. The delay-line injection locked SO where Gm is the inverting system dynamic models and phase noise equations derived transconductance, R and C are the resistance− and capacitance in Section II and III are verified by SPICE and MATLAB at the output node of each delay component, respectively. j(ωit+φi) j(ωit+φo(t)) simulations in Section IV. In Section V, measurement results Vi = V¯ie and Vo = V¯oe are the injected on a 1GHz CMOS PLL-RI with injection-locking into a signal and output signal respectively. We define φ = φo (t) φi − CMOS ring-type VCO, fabricated with 130nm RF CMOS as the instantaneous differential phase, and ∆ω = ωo ωi as technology, and occupied 100µm 200µm, are provided to the frequency offset of the injected signal, ω , from the− VCO × i support the theories and simulations in this paper. Section VI resonant frequency, ωo, and Vx is the signal at the input of the offers conclusions. delay-line. The total phase shift φd (ω) of the delay line in Fig. 2 at frequency ω can be found in terms of the oscillating frequency II. PLL-RI SYSTEM DYNAMIC ωo and the number of stages N: The functional block diagram of the PLL-RI shown in −1 ω π Fig. 1(a) consists of a Phase Frequency Detector (PFD), a CP, φd (ω)= N tan tan (1) − ω N a Low Pass Filter (LPF), a voltage controlled SO (VCSO), and o an attenuator (ATTN). Normally, in a PLL, the PD compares The quality factor Q of this oscillator is defined as Q = the phase difference between the reference and the output ωo dφ(ω) 2 dω [13], which is a measure of how much the signals, and a control mechanism acts on the VCO in such a ωo closed-loop system opposes variations in the frequency of way that the phase error is reduced to a minimum. In PLL-RI, however, besides the loop phase tracking operation, the VCSO oscillation. Therefore, in a delay-line ring oscillator, also functions as a tracking device. In general, either of these ωo dφ (ω) ωo N 1 2π N 2π two mechanisms is sufficient for phase locking; however, they Q = = sin = sin (2) 2 dω 2 × 2 ωo N 4 N ωo are combined to realize a low phase noise performance and Equation (2) shows that Q cannot exceed π for this type of os- improved locking behavior.
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