Reference Injected Phase-Locked Loops (PLL-Ris) Feiran Lei, Student Member, IEEE, and Marvin H

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Reference Injected Phase-Locked Loops (PLL-RIs) Feiran Lei, Student Member, IEEE, and Marvin H. White, Life Fellow, IEEE

Abstract—In this paper, we use synchronization to reduce Phase-Locked Loop (PLL) phase noise and improve its locking behavior with an attenuated reference signal injection (RI) into a voltage controlled CMOS delay-line ring-type oscillator. The transient and steady-state behavior of the PLL-RI are described by a nonlinear differential equation, which is further studied by the phase-plane method. The nonlinear equation is linearized for the small-signal condition and the s-domain noise transfer functions and noise bandwidths for different noise sources are derived. The effect of the loop parameters and the injection strength on the output phase noise, loop settling time, and lock in range is analyzed. Finally, the analysis is verified by the SPICE simulation and measurement results from an 1-GHz PLL- RI with 130nm standard RF CMOS technology. Simulation and (a) (b) measurement results show phase noise reduction and improved settling behavior of a PLL-RI compared to a conventional PLL. Fig. 1. Simplified system block diagrams for (a) a Reference Injected Phase- Locked Loop (PLL-RI) and (b) a Phase-Locked Loop (PLL) Index Terms—Phase-Locked Loops (PLLs), synchronization, CMOS ring oscillators, phase noise suppression, noise bandwidth. phase noise up to an offset of 1MHz [3]. If we consider these challenges, then new methodologies are needed to overcome these limitations. The driving force in almost all PLLs is I.INTRODUCTION an oscillator, therefore, a good understanding of oscillation- YNCHRONOUS clocking circuits, with their primary based phenomena, such as injection locking – which is a very S impact on modern practical computing systems, have useful and interesting phenomenon that happens in numerous been a significant contributor to the overall advancement physical systems especially in electronic oscillators – can be of communication technologies. It is typical in synchronous helpful in solving these problems. circuits to use a reference clock signal in a feedback control The injection locking technique, characterized by its simple loop to stabilize both frequency and phase, resulting in a structure and low noise performance in an oscillator design, phase-locked loop (PLL) architecture. Due to the rapid growth has been investigated by researchers. By comparing the os- of the CMOS technology, high-frequency, high-speed, low- cillator with a high stability reference signal source, injection noise and low-cost PLLs have become crucial elements in locking will cause the oscillator to be phase locked to the a variety of communication applications. In a typical PLL, reference source. Van Der Pol [4] first introduced the injection the total output phase noise is the summation of the low of an external signal to an oscillator to control its frequency; passed reference noise and Phase Detector (PD) noise, and however, the signal level was large and tended to ’quench’ the high passed Voltage Controlled Oscillator (VCO) noise, the output amplitude. Adler [5] developed a small signal therefore, an optimal noise performance can be achieved by model for the tracking and non-tracking characteristics of the properly selecting the loop bandwidth to suppress the noise injection locking phenomena where signal injection was at from the VCO, the PD, and the reference. However, the VCO low levels to modulate the phase only. Adler’s work provided noise becomes more difficult to suppress as its frequency a strong foundation for the subsequent work on injection- increases [1]. We could use a wider bandwidth to suppress locked oscillators [6]–[9]. In particular, injection locking is more VCO noise, but the loop stability may be affected and used widely in injection-locked clock multipliers (ILCMs) to more PD noise and input noise will be included. This is achieve superior phase noise over a PLL [6]. Runge [7] in especially a challenge in today’s nano-scaled processes where 1976 developed a reference injected (RI), discrete component, the low frequency noise (LFN), which arises from the random PLL with an analog multiplier PD and LC oscillator for use in capture and release of electrons by traps located in and near the Undersea Lightwave Systems, which have been in use since gate dielectric, is of concern, especially in high-K dielectrics 1988 in the Atlantic Ocean and 1989 in the Pacific Ocean. with large number of traps [2]. LFN in the device baseband However, the full potential of this method to improve the noise affects the oscillating frequency and dominates the measured and settling performance of Charge-Pump PLLs has yet to be analyzed and implemented in an integrated CMOS circuit The work is supported by the National Science Foundation ECCS #1201656 under program director Dimitris Pavlidis. technology. F. Lei is with the Department of Electrical and Computer Engineering, the We have applied the injection locked Synchronous Oscil- Ohio State University, Columbus, OH, 43202 USA (e-mail: [email protected]) lator (SO) [8] with voltage control capability to a modified M. H. White is with the Department of Electrical and Computer En- gineering, the Ohio State University, Columbus, OH, 43202 USA (e-mail: Charge-Pump (CP) PLL to replace the conventional VCO, as [email protected]) shown in Fig. 1. The Charge-Pump PLL, which employs a Digital Object Identifier: 10.1109/TCSI.2017.2668298

1558-0806 c 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications standards/publications/rights/index.html for more information. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS 2 nonlinear discriminator to aid the frequency acquisition [10], is an improvement over the phase comparator-type early PLLs in that it also provides a frequency error output as well as a phase error, so the PLL capture range is only limited by the VCO output frequency range. It also generates a coherent output phase as the CP together with a passive integrable filter is capable to provide a pole at the origin so as to increase the order of the type of the PLL. Based on Runge’s method [7], the injection signal is derived directly from the attenuated Fig. 2. Linearized models of a delay-line oscillator with low-level injection reference signal without additional circuit implementations. – synchronous oscillator (SO) Compared to a PLL, the new system, named a Reference Injected PLL (PLL-RI), provides further noise suppression and cycle, and the energy is restored to the resonator during the improved locking behavior. The phase noise shaping functions edges rather than at the voltage maxima [11]. In this paper, of a PLL-RI are formulated mathematically. PLL-RI provides a delay-line, ring-type CMOS oscillator architecture for the flexible design trade-offs by decoupling 3dB loop bandwidths VCSO is adopted to provide a large tuning range in a fully for different noise sources. integrated PLL. This paper is organized in the following manner. The next section theoretically analyzes the PLL-RI system from the aspect of dynamic equations to study its locking condition A. SO Dynamic Phase Equation and settling behavior. The phase noise of the PLL-RI with Modified from the linearized model of a delay-line oscil- noise contributions from different sources – reference/injection lator [12], Fig. 2 shows a linearized model of an N-stage signal, PFD/CP, and VCO, is described in Section III. The delay-line injection locked SO where Gm is the inverting system dynamic models and phase noise equations derived transconductance, R and C are the resistance− and capacitance in Section II and III are verified by SPICE and MATLAB at the output node of each delay component, respectively. j(ωit+φi) j(ωit+φo(t)) simulations in Section IV. In Section V, measurement results Vi = V¯ie and Vo = V¯oe are the injected on a 1GHz CMOS PLL-RI with injection-locking into a signal and output signal respectively. We define φ = φo (t) φi − CMOS ring-type VCO, fabricated with 130nm RF CMOS as the instantaneous differential phase, and ∆ω = ωo ωi as technology, and occupied 100µm 200µm, are provided to the frequency offset of the injected signal, ω , from the− VCO × i support the theories and simulations in this paper. Section VI resonant frequency, ωo, and Vx is the signal at the input of the offers conclusions. delay-line. The total phase shift φd (ω) of the delay line in Fig. 2 at frequency ω can be found in terms of the oscillating frequency II.PLL-RISYSTEM DYNAMIC ωo and the number of stages N: The functional block diagram of the PLL-RI shown in −1 ω π Fig. 1(a) consists of a Phase Frequency Detector (PFD), a CP, φd (ω)= N tan tan (1) − ω N a Low Pass Filter (LPF), a voltage controlled SO (VCSO), and o an attenuator (ATTN). Normally, in a PLL, the PD compares The quality factor Q of this oscillator is defined as Q = the phase difference between the reference and the output ωo dφ(ω) 2 dω [13], which is a measure of how much the signals, and a control mechanism acts on the VCO in such a ωo closed-loop system opposes variations in the frequency of way that the phase error is reduced to a minimum. In PLL-RI, however, besides the loop phase tracking operation, the VCSO oscillation. Therefore, in a delay-line ring oscillator, also functions as a tracking device. In general, either of these ωo dφ (ω) ωo N 1 2π N 2π two mechanisms is sufficient for phase locking; however, they Q = = sin = sin (2) 2 dω 2 × 2 ωo N 4 N ωo are combined to realize a low phase noise performance and Equation (2) shows that Q cannot exceed π for this type of os- improved locking behavior. 2 In on-chip applications, VCOs are typically implemented cillators. Therefore, delay-line ring oscillators are considered with LC tank oscillators or delay-line ring-type oscillators to be low quality factor oscillators. based on the required specification. The LC-VCO has low Once the injection signal is impressed, the output frequency long-term and period jitter and low phase noise, but consumes ωout can be written as large layout area and has a narrow tuning frequency. On the dφo (t) dφ (t) other hand, for a given power budget, the ring-type VCO 1) is ωout = ωi + = ωi + (3) dt dt easier to integrate due to its compactness; 2) has little coupling to the other circuit components 3) can oscillate at a very high If we substitute Equation (3) into Equation (1) and combine frequency, and since it is tuned in frequency by a current, it has with Equation (2), then we obtain a broader tuning range than the LC-VCO. However, ring-type dφ(t) ∆ω dt oscillators suffer from the well-known degradation in phase tan φd 2Q − (4) noise performance because of the poor quality factor Q since ≈− ωo the energy stored in the node capacitances is discharged every A graphical phasor representation of the signals in Fig. 2, is IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS 3

(a) (b)

Fig. 3. SO (a) phasor representation to examine relations between φ, φd, V¯i (a) (b) and V¯o, (b) phase plane trajectory showing the locking range ωL and steady Fig. 4. Phase plane trajectories for (a) PLL-RI with K=1.3, A=0.248 (b) PLL state phase error φSS with K=0, A=0.248 (K and A are chosen based on the design in Section IV) shown in Fig. 3(a), where we obtain is the oscillator initial free running frequency, Ko in rad/V s · V¯i sin φ (t) is the tuning sensitivity of the VCSO. Therefore, Equation (7) tan ( φd (t)) = (5) − V¯o + V¯i cos φ (t) becomes ¯ Equating (5) and (4), we have dφ (t) ωfo + KoVctrl Vi ωfo + KoVc ωi sin φ (t) (9) dt ≈ − − 2Q V¯ dφ (t) ω V¯ sin φ (t) o =∆ω o i (6) V¯ From the block diagram shown in Fig. 1(a), if we neglect the dt − 2Q V¯o i 1+ V¯ cos φ (t) o effect of the second capacitor C2 since its capacitance is much If we consider low-level injection (i.e. a weak injection signal smaller than C1, the time domain control voltage is V¯i ¯ 1), then the system dynamics of a delay-line oscillator t Vo ≪ Kp under low-level signal injection become: Vctrl (t)= KpRφ (t) φ (t) dt (10) − − C −∞ 1 Z dφ (t) ωo V¯i (7) Ip ∆ω sin φ (t)=∆ω KSO sin φ (t) where Kp = is the gain of the PFD/CP and Ip is the dt ≈ − 2Q V¯o − 2π amplitude of the current source in the CP. If we substitute ωo V¯i where KSO , . Equation (7) is the same as the well 2Q V¯o Vctrl into Equation (9) and consider low-level injection: known Adler’s equation [5] where a LC tank oscillator was d2φ dφ K K used in the derivation. It is also identical to the first-order type- p o (11) 2 +(KpKoR + KSO cos φ) + φ = 0 one PLL phase equation [14], [15] which indicates that the SO dt dt C1 itself is basically a first-order PLL. However, it alleviates the The term KSO cos φ in Equation (11) represents the effect of needs for PD and feedback loop implementations, which are the injection on the output phase difference. essential in a conventional first-order PLL. We can eliminate some constants by normalizing the It is instructive to look at the SO system dynamic described time variable. Letting t = τ/ (KpKoR), so that dφ/dt = in Equation (7) by drawing the phase plane trajectory [14]. KpKoR (dφ/dτ), and defining K = KSO/ (KpKoR) and Fig. 3(b) shows dφ/dt, the frequency difference, as a function A = 1/ (KpKoR RC ), Equation (11) becomes · 1 of φ, the phase difference. The equilibrium resides at the point 2 −1 ∆ω d φ dφ where dφ/dt is zero and φ is a constant φss = sin . +(1+ K cos φ) + A φ = 0 (12) KSO 2 By examining the existence of the equilibrium point, we can dτ dτ · observe two regions of operation: 1) driven and locked when We may construct a phase plane trajectory of Equation (12) in which φ is the abscissa and dφ/dτ is the ordinate. Shown ∆ω KSO 0; 2) driven but unlocked when ∆ω KSO > 0. − ≤ − in Fig. 4 is the comparison of the trajectories for PLL-RI In the driven and locked region, a steady-state φss always dφ with K > 0 and the conventional PLL with K = 0. Certain exists such that dt = 0. However, in the driven but unlocked region, the output will never be able to phase lock to the observations can be made from the figures: dφ (1) At equilibrium, the steady-state phase error φSS is zero injected signal as dt > 0. Therefore, the lock-in range of the SO is given by when PLL-RI is phase-locked (dφ/dτ = 0). To better under- stand the property of this equilibrium point, we rephrase the ¯ ωoVi above system as: ∆ωL = 2 KSO = , (8) × QV¯o φ′ = dφ/dτ which can also be observed as the swing of the trajectory. The ′ (13) (dφ/dτ) = (1 + K cos φ)(dφ/dτ) Aφ SO injection parameter KSO is also known as the one-sided ( − − lock-in range. It is easy to see that (φ, dφ/dτ) = (0, 0) is the only equilibrium of the above system, and the Jacobian matrix of the B. PLL-RI Dynamic Phase Equation system (13) reads The SO is designed to have the voltage control capability. dφ 0 1 J φ, = dφ (14) The new VCSO frequency is ωo = ωfo + KoVctrl where ωfo dτ K sin φ A (1 + K cos φ) dτ − − IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS 4

(a) time domain

Fig. 5. Numerical result of pull-in time ratios log (tPLL/tPLL-RI) at different combinations of initial phase and normalized frequency difference; the PLL- RI settles faster than the PLL in 92% of the combinations. (b) linearized frequency domain and corresponding eigenvalues can be found: Fig. 6. Dual loop PLL-RI phase models with the injection loop and the 1 phase-locked loop λ , = [ (1 + K cos φ) 1 2 2 · − ± respectively. Based on Equation (16), the time domain phase dφ (1 + K cos φ)2 4 A K sin φ (15) in the PLL-RI system can be modeled as shown in Fig. 6(a), − − dτ s # which consists of dual loops, namely the original phase-locked Both eigenvalues have negative real parts, therefore, loop and the injection loop. We can linearize the phase model (φ = 0, dφ/dτ = 0) is the stable equilibrium and the global at the locked state by assuming the phase difference φ is small with sin φ φ. The linearized frequency domain phase model attractor for the system. ≈ (2) In comparison with the conventional PLL, the PLL-RI at locked state is shown in Fig. 6(b), from where the PLL-RI adds nonlinearity in the phase system given in Equation (13), phase-transfer function H (s) becomes: therefore, the speed of the convergence of the solution to the s (K K RC + K C )+ K K H (s)= p o 1 SO 1 p o (17) equilibrium depends on the initial solutions of the phase differ- 2 s C1 + s (KpKoRC1 + KSOC1)+ KpKo ence φ (0) and the normalized frequency difference dφ/dτ (0), Deﬁning resulting in a pull-in time difference between the PLL-RI with K > 0 and the conventional PLL with K = 0. Practically, ′ K K natural frequency ω = ω = p o we choose φ (0) [ 2π, 2π], and dφ/dτ (0) [0, 5π], a n n C ∈ − ∈ r 1 pull-in time comparison can then be plotted numerically by ′ RC1ωn KSO KSO calculating at each combination of the initial conditions, the damping factor ζ = + = ζ + 2 2ωn 2ωn ratio of log (tPLL/tPLL-RI) where tPLL and tPLL-RI are the pull-in KpKo RC1ωn time for the conventional PLL and the PLL-RI, respectively. where ωn = and ζ = are the natural C1 2 Fig. 5 illustrates, for a majority of cases (92%), this ratio frequency and dampingq factor for the conventional PLL. The is positive, which means the PLL-RI settles faster than the lock range within which a PLL locks in one single beat note conventional PLL. between the reference frequency and output frequency can be ′ ′ (3) The pull-in range of the PLL-RI is ideally inﬁnity but found [16] as ∆ωL = 4πζ ωn, an improvement of KSO/2 practically is limited by the VCSO operating frequency, which over the conventional PLL. is large in a ring-type delay-line VCSO. We may also derive the expression for the output phase φout III.PLL-RINOISE CONSIDERATIONS to have a better understanding of the injection behavior. The In this section, we will analyze the phase noise behavior of output phase becomes a PLL-RI under locked condition (∆ω = 0). Intuitively, the

φout = φPLL φINJ zero-crossing of the output signal in each period in the time − t t domain is correctly by the low noise reference injection to the = ωfot + Ko Vctrl (t) dt KSO sin φ (t) dt (16) oscillator, thereby, reducing jitter accumulation at the output. −∞ − −∞ Z Z t where φPLL (t) = ωfot + Ko −∞ Vctrl (t) dt and φINJ (t) = A. VCSO Phase Noise Transfer Functions t represent the instantaneous PLL phase Once a signal is injected into the VCSO, phase noise KSO −∞ sin φ (t) dt R and the instantaneous injection induced phase modulation, shaping functions can be calculated based on the methodology R IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS 5

phase noise can be regarded as a feedback loop, as shown in Fig. 8 (a). Incorporating the PLL-RI phase mechanism given in Fig. 6 recasts a model to a dual-loop conﬁguration as shown in Fig. 8 (b), from where the overall phase noise power spectral density (PSD) can be expressed as

Sout,n (ωos)= Hosc,nSosc,n + Hpfd,nSpfd,n + Hinj,nSinj,n (20)

Fig. 7. Inherent VCO noise shown at the output of the VCSO: the injection where suppresses VCO LFN s2 2 H (ω )= osc,n os s2 + (2ω ζ + K ) s + ω2 n SO n 2 2ω ζs + ω2 /K n n p Hpfd,n (ωos)= 2 2 s + (2ωnζ + KSO) s + ωn 2 2ω ζs + ω2 + K s (a) n n SO Hinj,n (ωos)= 2 2 s + (2ωnζ + KSO) s + ωn

showing that the overall phase noise is broken down into three major noise components: the inherent VCSO noise, the PFD/CP noise, and the reference/injection noise. Fig. 9 displays an added power spectra from each noise source through corresponding noise shaping functions with different KSO. With the introduction of the KSO, the RI results in (b) a noise suppression at lower frequencies as the HPF corner frequency increases, and a noise suppression at higher Fig. 8. Phase noise model for (a) a VCSO and (b) a PLL-RI frequencies as the LPF corner frequency decreases, which suppresses more VCSO noise and reference/PFDCP noise, of applying a small phase perturbation φinj,n and φosc,n on the injected and the oscillator signals, respectively, and finding a respectively. The same conclusion can be drawn from a noise bandwidth perspective. The noise bandwidth B is defined as phase perturbation φn of the differential phase φ as a result n of these phase perturbations. Thus, we find the integral [10]:

s Φosc,n KSO cos φss ∞ Φout,n = · + Φinj,n (18) 1 2 s + KSO cos φss s + KSO cos φss Bn = H (ω) df (21) 4π −∞ | | 2 ∆ω2 Z When the system is locked, cos φss = 1 K2 , then the − SO output phase noise can be written as: The narrower the noise bandwidth, the greater the noise performance of the PLL [16]. L (ω ) Losc(ωos) inj os (ω ) = 10 log 10 10 Hosc,n + 10 10 Hinj,n (19) 1) VCSO noise: The 3dB loop bandwidth for the VCSO L os noise transfer function Hosc,n from Equation (20) is where 2 ωos Hosc,n (ωos)= ′2 ′2 2 K2 ∆ω2 + ω2 ω3dB,osc = ωn 2ζ 1+ (2ζ 1) + 1 (22) SO − os r − − K2 ∆ω2 q H (ω )= SO ′ inj,n os 2 − 2 2 where ωn and ζ are defined in Section II. We can observe as KSO ∆ω + ωos − KSO increases, ω3dB,osc increases as well, which means more are the noise shaping functions for the oscillator phase noise VCSO noise is suppressed. and injected phase noise, respectively. As shown in Fig. 7, the Since the VCO noise is high passed, the integral in Equa- inherent oscillator noise is high pass filtered (HPF) as it is tion (21) is infinity, however, the effect of far-out VCO noise presented at the output. The 3dB loop bandwidth of the HPF is not under consideration in the PLL design since it 1) is ω = K2 ∆ω2 increases with K to suppress more 3dB SO SO usually low and 2) could be filtered out easily. If we change VCO noise. − p the integration limit of to an upper bound frequency ωup, the noise bandwidth for∞ VCO noise is then calculated from B. PLL-RI Phase Noise Transfer Functions and Noise Band- Equation (21): widths for Different Noise Sources In a PLL-RI, the center frequency of the VCSO is changing Bn,osc = ωup inside the loop to match the injection reference signal, there- − -1 -1 ωn F (X) tan G (X)+ F ( X) tanh G ( X) (23) fore, ∆ω = 0. Equation (19) then indicates the SO overall − − − IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS 6

Fig. 9. PLL-RI output phase noise with different injection levels where

′ X , 2ζ 2 1 − 2X2 1 + 2X√X2 1 F (X) , − − 2√X2 1 X + √X2 1 −ωup − G (X) , p 2 ωn X + √X 1 − ′ KpSO Knowing that ζ = ζ + ω , since Equation (23) is a monotone 2 n′ decreasing function on ζ , increasing KSO will decrease the noise bandwidth Bn,osc. Fig. 10(a) plots Bn,osc versus ζ as KSO increases, where we can easily see that increasing KSO and ζ will decrease the noise bandwidth. (a) VCO NBW decreases with increased KSO 2) PFD/CP noise: Usually in a conventional PLL, noise inside PFD/CP is low passed as it is shown at the output, therefore, reducing the loop bandwidth to suppress more PFD/CP noise will include more VCO noise in the picture. However, in a PLL-RI, the 3dB loop bandwidth for the PFD/CP noise transfer funtion Hpfd,n from Equation (20) is

4 2 ω3dB,pfd/cp = Y + ω + Y (24) − n q 1 p2 2 where Y = KSO KSO + 2ωnζ ω 1 + 2ζ . As KSO in- 2 n (b) PFD/CP NBW decreases with increased creases, ω decreases, which− means more PFD/CP noise KSO 3dB,pfd/cp is suppressed. Therefore, the parameter KSO can decouple loop bandwidths for VCO and PFD/CP to suppress both’s noise at the same time. The noise bandwidth due to PFD/CP noise:

ωn ζ 1 Bn,pfd/cp = 2ζ + (25) 2 KSO 4Kp ζ + 2ζ 2ωn

Thus, Bn,pfd/cp is a monotone decreasing function on KSO. Fig. 10 (b) plots Bn,pfd/cp versus ζ as KSO increases. Bn,pfd/cp has a minimum of (c) Input NBW decreases with increased KSO when KSO <ωn (1 − 2ζ)

Fig. 10. The normalized noise bandwidth (NBW) of a second-order PLL-RI 2 ωn KSO KSO as a function of the damping factor ζ for different KSO Bn,pfd/cp min = + 1 (26) 2K2 ω − 2ω p s n n IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS 7

Fig. 11. CMOS implementation of the PLL-RI system: a Phase Frequency Detector (PFD) drives a Charge Pump (CP) circuit, which supplies pump current, Ip, to a Low-Pass Filter (LPF) to create a control voltage, Vctrl for the Voltage Controlled Synchronous Oscillator (VCSO). The VCSO is also controlled by low-level injection Vinj from the Reference Injection (RI). at

2 1 KSO KSO ζ min = + 1 (27) 2 ω − 2ω s n n 3) Input noise: Unlike the conventional PLL where the input noise is only low-passed, the input noise of the PLL-RI is also band-passed due to the injection loop. 3dB bandwidth is not sufﬁcient to ﬁnd its noise dependence on KSO. Therefore, we need to study its noise bandwidth:

ω ′ 1 B = n ζ + (28) n,inj 2 4ζ′ In order to ﬁnd its dependence on Kso, we can ﬁnd dBn,inj : dKSO

dBn,inj (KSO + 2ωnζ + ωn)(KSO + 2ωnζ ωn) = 2 − (29) dKSO 4(KSO + 2ωnζ) Fig. 12. CMOS implementation of the ring-type, delay-line, VCSO with active inductor loads to compensate for parasitic capacitances Therefore, when KSO < ωn (1 2ζ), Bn,inj is a monotone − decreasing function on KSO, and KSO can dramatically reduce IV. EXAMPLE:PLL-RIIMPLEMENTATION AND the noise bandwidth. When KSO > ωn (1 2ζ), Bn,inj is a NUMERICAL RESULTS monotone increasing function on K . Fig.− 10 (c) plots B SO n,inj To further illustrate the utility of the theory discussed in versus ζ as K increases. B has a minimum of ωn at SO n,inj 2 Section II and III, a fully integrated PLL-RI with ring-type, ζ = 0.5 KSO . Since the noise bandwidth is fairly ﬂat in − 2ωn delay-line, VCSO has been designed. Loop dynamic parame- the neighborhood of ζ = 0.5 KSO , and when ζ > 0.5 − 2ωn − ters, noise shaping functions and noise bandwidth calculated KSO , increasing K does not noticeably worsen the noise 2ωn SO in MATLAB from the theory are compared against SPICE performance. simulations in this section and measurements in Section V. From the noise analysis above, KSO has a positive effect on The CMOS implementation of the PLL-RI with the block the noise performance of the PLL-RI. Practically, ζ is chosen diagram shown in Fig. 1(a) is given in Fig. 11. A True- between 0.5 and 2 for low period jitter and accurate reference Single-Phase-Clock (TSPC) dynamic DFF is used for high phase tracking, and KSO can be optimized for the minimum frequency operation in the PFD circuit implementation. In overal noise bandwidth by changing the injection level and the the LPF design, all the passive components are implemented design of the oscillator. We note, the injection level can not be with on-chip elements. The detailed VCSO design is shown in arbitrarily large to increase KSO, otherwise, the criteria of the Fig. 12, which employs a current mirror as a voltage to current ¯ small signal injection Vi 1 is violated and the injection converter (V2I) and a two-stage current controlled delay-line Vo¯ ≪ will tend to quench the output amplitude. oscillator to achieve a wide operating frequency range and a IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS 8

Fig. 13. Measured and simulated VCSO output frequency vs. input control voltage at different process variation corners for NMOS and PMOS carrier Fig. 15. Transient settling behavior of the control voltage in PLL-RI and mobilities. F, T, S refer to Fast, Typical and Slow. The measurements (details PLL: PLL-RI settles faster than the PLL in Section V) closely follows the Typical curve.

Fig. 16. PLL-RI phase noise comparison between theory implemented by Fig. 14. Simulated and Calculated VCO phase noise when Vinj=0V and MATLAB and SPICE simulation for different levels of injection VCSO phase noise when Vinj(p)=20mV : injection suppresses noise at low frequency offset from the carrier at 1GHz the two settling time is 1.9, which is comparable to the minimum chip area. The delay cell has a cross coupled NMOS simulated locking time ratio shown in Fig. 15. latch which can boost the stage gain and minimize the effect of The PLL-RI phase noise comparison between the theory in supply voltage ﬂuctuations once the latch is established. Active Section III and the simulation is given in Fig. 16 where the inductors realized by PMOS active loads and NMOS variable open loop (OL) phase noise of the VCSO, reference signal, and resistors are used to compensate for the parasitic capacitance PFD/CP mapped to the VCSO frequency are also plotted. Un- to increase the speed of the delay cell [17]. The conﬁguration like the previous transistor-level simulations, the PLL-RI phase of a differential delay cell is immune to supply disturbance. noise simulation has the VCSO and passive components as A Differential to Single (D2S) buffer is used to convert and actual devices, but the PFD/CP is implemented with Verilog- buffer the differential output signal. A behavior model in order to vary its noise contribution, and Fig. 13 plots the simulated VCSO transfer characteristics the phase noise is found from the transient noise simulation. In for different process corners. The designed VCSO achieves a the PLL without injection, the actual simulated noise around the offset of 10MHz peaks due to the nonlinear response of the linear gain K that varies by a factor of less than 1.3 for almost o PLL with the parasitics modeling. The PLL-RI with injection the entire range of the control voltage (V V V ) Tn ctrl DD helps to suppress the noise around this region and the strength where V is the threshold voltage of the NMOS≤ device≤ where Tn of the suppression is determined by the injection levels. The the control voltage is applied. The slight variation of Ko modestly impacts the loop dynamics of the PLL-RI. Fig. 14 theoretical phase noise for PLL-RI with different injection shows the phase noise in the VCO and VCSO for both levels (KSO) matches with the corresponding simulated results. analytical and simulated results. In the conventional VCO, Shown in Fig. 16, and calculated with Equations (22) and (24), device baseband LFN is up-converted to the RF regime with a the loop bandwidth for PFD/CP noise is reduced from 18MHz in a conventional PLL with to 0.95MHz in a PLL- slope of 1/f 3 while white noise is up-converted with a slope KSO = 0 RI with MHz, and the loop bandwidth for oscillator of 1/f 2. These slopes have been related analytically to the KSO = 47 physical device modeling parameters [9]. The analytical phase noise is increased from 11MHz in a conventional PLL with noise of the VCSO calculated from Equation (19) matches well KSO = 0 to 60.44MHz in a PLL-RI with KSO = 47MHz. with the simulated result. The SO reduces the phase noise in the low frequency region. V. MEASUREMENTS The transient simulation results in Fig. 15 shows the settling Measurements were performed on a 1GHz PLL-RI, shown behavior of the PLL-RI with and without injection. The in Fig. 17, which was fabricated with Global Foundries initial control voltage at the start-up is set to be 0.55V, from standard 130nm RF CMOS process with the core size of where the initial condition is calculated as (φ, dφ/dt) = 100µm 200µm. The topology of the PLL-RI was the same (0, 288MHz 2π). The pool in Fig. 5 gives the ratio between as shown× in Fig. 11. This prototype PLL-RI is measured with × IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS 9

Fig. 19. VCSO measured phase noise (unﬁltered): injection suppresses low offset VCO phase noise; the injection power determines the suppression strength. Measurement results show agreement with the simulation results in Fig. 14, which is overlaid here with dashed lines Fig. 17. Die photo of the 1-GHz PLL-RI fabricated in 130nm RF CMOS. The core size of the 1GHz PLL-RI is 100µm×200µm

Fig. 20. Measured PLL-RI output spectrum and phase noise (ﬁltered) of PLL- RI with different attenuation levels. Prediction on the PLL-RI phase noise with 10dB ATTN is also plotted.

Fig. 18. PLL-RI measurement setup. The noise injection into the PLL-RI control voltage noise is not considered in the SO phase noise is determined by the Pulse Generator. The VDD is supplied by a battery to model, and in the actual measurement, the noise from the reduce noise. testing equipment is involved. The measured output signal and phase noise at 1GHz are a Cascade Probe test system which consists of a RF probe shown in Fig. 20. The PLL-RI reduces the phase noise and station, ground-signal-ground (GSG) coplanar RF probes, and jitter peaking in the vicinity of the designed loop bandwidth, high-speed cables. The test set-up is shown in Fig. 18 where a which is around 18MHz in this example but can be optimized power splitter is used to split the pulse input from the RF signal for a particular application. The strength of the noise reduction generator to feed to both the injection port with an attenuator is dependent on the injection constant KSO which is propor- and the reference port. The pulse power is attenuated by 3dB tional to the intensity of the injection power. With a 10dB after the power splitter. A 1.2V battery is employed to supply attenuation, we also have applied the transfer functions (20) power to the chip with a low noise solution. A 50Ω variable directly on the measured phase noise of each components, resistor is used to provide the variable charge pump current. and plotted a theoretical PLL-RI output phase noise which The PLL-RI has a 1.2V power supply and operates from 0.5 agrees with the measurement. With a 20dB attenuation, Equa- to 1.7GHz, consuming 2.6mW power at 1GHz. The lock in tions (22) and (24) indicate the 3dB loop bandwidths for range of the PLL-RI is the same as the operating range for the inherent oscillator noise and PFD/CP noise is changed from VCSO, whose measured transfer characteristic is shown in Fig. 11MHz and 18MHz respectively in a conventional PLL with 13 which matches well with the typical corner simulation. The KSO = 0, to 78.6MHz and 0.7MHz respectively in a PLL-RI measured VCSO phase noise is shown in Fig. 19. Since the with KSO = 65MHz. Same results could be observed from VCSO noise is high passed as the result of the signal injection, Fig. 20 where loop bandwidths are decoupled for different the low frequency VCSO noise is reduced, and the injection types of noise sources: compared with a conventional PLL, level determines the strength of the noise suppression. Fig. 19 for PFD/CP and input noises, the 3dB loop bandwidth is also plots the theory in Fig. 14 where a 20mV peak injection reduced by around 14dB, and for oscillator inherent phase voltage is applied in the VCSO and its phase noise matches noise, the 3dB loop bandwidth is increased by 8.5dB. When a with the -24dBm power injection curve in the measurement. 30dB attenuation is applied, phase noise at 1MHz and 10MHz The slight phase noise deterioration is due to the reason that offset are reduced from -118.8dBc/Hz (PLL) to -121.9dBc/Hz IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS 10

(PLL-RI), and -102.3dBc/Hz (PLL) to -128.3dBc/Hz (PLL- [10] Floyd M. Gardner, Phaselock Techniques, John Wiley and Sons, New RI), respectively, with an integrated RMS jitter from 10KHz York, 2005 [11] T. H. Lee and A. Hajimiri, Oscillator phase noise: a tutorial, IEEE J. to 30MHz of 1.55ps. Solid-State Circuits, vol. 35, pp. 326-336, Mar. 2000 [12] B. Razavi, A study of phase noise in CMOS oscillators, IEEE J. Solid- State Circuits, vol. 31, pp. 331-343, Mar. 1996 VI.CONCLUSION [13] B. Razavi, RF Microelectronics, Prentice Hall PTR, 2001 This paper theoretically evaluated a Phase-Locked Loop [14] A. J. Viterbi, Principles of coherent communication, McGraw-Hill Book Company, 1966 (PLL) system under Reference Injection (RI). The dynamic [15] J. Klapper, J. T. Frankle, Phase-Locked and Frequency Feedbank Sys- behaviors including the settling time, lock in range, and the tems, Academic Press Inc, 1972 phase noise performance of the PLL-RI are studied. A PLL-RI [16] Roland E. Best, Phase Locked Loops: Design, Simulation, and Appli- cations, McGraw-Hill Book Company, 2007 system has been designed and fabricated with 130nm standard [17] S. Hara, T. Tokumitsu, T. Tanaka, and M. Aikawa, Broadband monolithic RF CMOS technology. The simulated and measured results microwave active inductor and its application to miniaturized wideband indicate excellent correlation between the analysis and the ampliﬁer, IEEE Trans. Microw. Theory and Tech., vol. 36, pp. 1920-1924, fabricated PLL-RI system. Compared with the conventional Dec. 1988 PLL, the PLL-RI offers faster settling time, wider lock in range and the ability to decouple loop bandwidths for VCO noise, reference noise, and PFD/CP noise, so that noise reduction is observed. When a 20dB attenuation is applied in the Feiran Lei was born in Xi’an, China. She received her M.S. degree in Electrical Engineering from the measurement, compared with a conventional PLL, the 3dB ElectroScience Laboratory at the Ohio State Uni- loop bandwidth for the VCO noise is increased by 8.5dB, versity (OSU), in 2011. From 2011 to 2012, she but the 3dB loop bandwidth for the PFD/CP noise is reduced was a research assistant at ATIC & Semiconduc- tor Research Center in Abu Dhabi, U.A.E. She is by 14dB. When a 30dB attenuation is applied, at the 10MHz currently a Ph.D. candidate under the supervision offset from 1GHz carrier frequency, the phase noise is reduced of Dr. Marvin H. White at the Nanoelectronics by 26dB in a PLL-RI. The PLL-RI discussed in this paper, Device Laboratory in the Department of Electrical and Computer Engineering at OSU. Her research without a frequency divider in the feedback path, tends to interests include the design of RF/analog ICs such focus on applications where the output is designed to track as voltage controlled oscillators, Phase-Locked Loops (PLLs), RF frequency the input signal, such as de-skewing, clock synchronization, synthesizers, charge sensitive preampliﬁers, and current mode detectors for clock regeneration [7], frequency/phase (de)modulation, etc. Built-in-self-test (BIST) applications. The theory formulated in Section II and III can be extend to be used in a frequency synthesizer where a divide-by-M is employed in the feedback loop, with the aid of a pulser- enabled harmonic injection [6]. Marvin H. White was born in the Bronx, NY. He is a Professor in the Electrical and Computer Engi- neering Department at Ohio State University (2010- ACKNOWLEDGMENT present) and Sherman Fairchild Professor Emeri- tus of Electrical Engineering at Lehigh University The authors would like to thank Dr. Waleed Khalil and his (1981-2010). He received B.S.E. degrees in En- group for providing on-chip test system and RF measurement gineering Physics and Mathematics (1960) and a M.S. degree in Physics (1961) from the University equipment at OSU ElectroScience Laboratory. of Michigan, and a PhD in Electrical Engineer- ing (1969) from Ohio State University. He joined REFERENCES Westinghouse (1961-1981) and, with his colleagues, he designed advanced integrated circuits and developed correlated double [1] J. Lee and H. Wang, Study of Subharmonically Injection-Locked PLLs, sampling (CDS) for noise suppression in imaging and sampled data systems. IEEE J. Solid-State Circuits, vol. 44, pp. 1539-1553, May 2009 He taught in the Westinghouse School of Applied Science, as an Adjunct [2] X. Zhang and M. H. White, A quantum mechanical treatment of low fre- Professor of Electrical Engineering at the University of Maryland, and in quency noise in high-K NMOS transistors with ultra-thin gate dielectrics, Belgium under a Senior Fulbright Fellowship. In 1981 he joined the ECE Solid-State Electronics, vol. 78, pp. 131-135, Jun. 2012 department at Lehigh University as the Sherman Fairchild Professor in [3] A. Abidi, Phase Noise and Jitter in CMOS Ring Oscillators, IEEE J. Electrical Engineering in the Sherman Fairchild Center for Solid-State Studies, Solid-State Circuits, vol. 41, pp. 1803-1816, Aug. 2006 where he and his colleagues established a graduate program in solid-state [4] B. Van Der Pol, The nonlinear theory of electric oscillations, Proc. IRE, devices and circuits. While at Lehigh, he took sabbaticals as a Visiting vol. 22, pp. 1051-1086, Sep. 1934 Research Scientist at the Naval Research Laboratory (1987-88) and as a [5] R. Adler, A study of locking phenomena in oscillators, Proc. IRE, vol. 34, Program Director (1995-96) at the National Science Foundation. From 1998- pp. 351-357, Jun. 1946 2010, he was the Director of Lehighs Sherman Fairchild Center. He is an IEEE [6] A. Elkholy, et al., A 6.75-to-8.25GHz, 250fsrms-Integrated-Jitter 3.25mW Life Fellow (1974) and member of the National Academy of Engineering Rapid On/Off/PVT-Insensitive Fractional-N Injection-Locked Clock Mul- (2001). He received the IEEE EDS J. J. Ebers Award (1997), the Masura Ibuka tiplier, ISSCC, pp. 192, 2016 Consumer Electronics Award (2000), the Aldert van der Ziel Award (2001), [7] P. Runge, Phase-locked loops with signal injection for increased pull-in and the EDS Distinguished Service Award (2010). In 2011, he received OSUs and reduced output jitter, IEEE Trans. Commun., vol. 24, pp. 636-644, College of Engineering Distinguished Alumnus Award. Dr. Whites research Jun. 1976 interest lies in custom integrated circuit design, signal processing, solid-state [8] V. Uzunoglu and M. H. White, The synchronous oscillator: a synchro- imaging, SONOS nonvolatile memories, CMOS transistor modeling, sensors, nization and tracking network, IEEE J. Solid-State Circuits, vol. sc-20, MEMS, SiC power devices, and BioMEMs, Dr. White has graduated 36 Ph.D.s pp. 1214-1226, Dec. 1985 and 62 M.S. students. His teaching areas concern Analysis and Design of [9] F. Lei and M. H. White, A study of the low frequency noise (LFN) in Integrated Circuits for Systems Applications and the Physics of Semiconductor reference injected phase locked loops (PLL-RIs), IEEE Dallas Circuits Devices. In the years he has been in industry and the university, Dr. White and Systems (DCAS), Oct. 2016 has nearly 300 papers and 28 U.S. Patents with colleagues and students.