Frequency Locking Techniques Based on Envelope Detection for Injection-Locked Signal Sources
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Martijn Huynen Injection Locking and Pulling EMC-Aware Design of A
EMC-Aware Design of a Low-Cost Receiver Circuit under Injection Locking and Pulling Martijn Huynen Supervisors: Prof. dr. ir. Dries Vande Ginste, Prof. dr. ir. Johan Bauwelinck Counsellors: Ir. Gert-Jan Stockman, Dr. ir. Frederick Declercq, Dr. Guy Torfs Master's dissertation submitted in order to obtain the academic degree of Master of Science in Electrical Engineering Department of Information Technology Chairman: Prof. dr. ir. Daniël De Zutter Faculty of Engineering and Architecture Academic year 2013-2014 EMC-Aware Design of a Low-Cost Receiver Circuit under Injection Locking and Pulling Martijn Huynen Supervisors: Prof. dr. ir. Dries Vande Ginste, Prof. dr. ir. Johan Bauwelinck Counsellors: Ir. Gert-Jan Stockman, Dr. ir. Frederick Declercq, Dr. Guy Torfs Master's dissertation submitted in order to obtain the academic degree of Master of Science in Electrical Engineering Department of Information Technology Chairman: Prof. dr. ir. Daniël De Zutter Faculty of Engineering and Architecture Academic year 2013-2014 Preface This master's dissertation is the conclusion to a lustrum at the faculty of Engineering and Architecture at Ghent University. Writing this preface is one of the final feats in this one-year work and makes you contemplate about the work that has been done and the help you received. This is why I want to seize the opportunity to express my sincerest gratitude to all those who helped bring this work to a successful ending. First and foremost, I would like to thank the chairman, prof. dr. ir. D. De Zutter, as well as prof. dr. ir. D. Vande Ginste and prof. -
Energy-Detecting Receivers for Wake-Up Radio Applications
Energy-Detecting Receivers for Wake-Up Radio Applications Vivek Mangal Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy under the Executive Committee of the Graduate School of Arts and Sciences COLUMBIA UNIVERSITY 2020 © 2019 Vivek Mangal All Rights Reserved Abstract Energy-Detecting Receivers for Wake-Up Radio Applications Vivek Mangal In an energy-limited wireless sensor node application, the main transceiver for communication has to operate in deep sleep mode when inactive to prolong the node battery lifetime. Wake-up is among the most efficient scheme which uses an always ON low-power receiver called the wake-up receiver to turn ON the main receiver when required. Energy-detecting receivers are the best fit for such low power operations. This thesis discusses the energy-detecting receiver design; challenges; techniques to enhance sensitivity, selectivity; and multi-access operation. Self-mixers instead of the conventional envelope detectors are proposed and proved to be op- timal for signal detection in these energy-detection receivers. A fully integrated wake-up receiver using the self-mixer in 65 nm LP CMOS technology has a sensitivity of −79.1 dBm at 434 MHz. With scaling, time-encoded signal processing leveraging switching speeds have become attractive. Baseband circuits employing time-encoded matched filter and comparator with DC offset compen- sation loop are used to operate the receiver at 420 pW power. Another prototype at 1.016 GHz is sensitive to −74 dBm signal while consuming 470 pW. The proposed architecture has 8 dB better sensitivity at 10 dB lower power consumption across receiver prototypes. -
EE426/506 Class Notes 4/23/2015 John Stensby
EE426/506 Class Notes 4/23/2015 John Stensby Chapter 2: Basic Modulation Techniques In most communication systems, the modulated signal has the form xcc (t) A(t)cos[ t (t)], (2-1) where c is known as the carrier frequency, A(t) is the envelope and (t) is the phase. Amplitude A(t) and phase (t) may depend on message m(t). When A(t) depends linearly on the message, and is a constant independent of m, we have linear modulation. When (t) depends on m(t), we have nonlinear modulation. Linear Modulation Double Sideband (DSB) is the first form of linear modulation we will consider. The general form of a DSB signal is x(t)Am(t)cos[tDSB cc0 ], (2-2) where Ac and are constants. For convenience, we will assume that = 0. Figures 2-1a through 2-1c depict a block diagram of a DSB modulator, a sinusoidal message m and the DSB time domain wave form xDSB(t), respectively. Note that every sign change in m(t) results in a ° 180 phase shift in the transmitted signal xDSB(t). DSB is very popular when used to transmit digital data. In this application, m(t) is a digital waveform that switches between +1 and -1 volts. Hence, m(t) switches the phase of the transmitted carrier by radians. For this reason, for a ±1 binary message, the modulation is called phase-shift keying. The Fourier transform of xDSB is A X(j)x(t)M(jj)M(jj)F c , (2-3) DSB DSB2 c c Latest Updates at http://www.ece.uah.edu/courses/ee426/ 2-1 EE426/506 Class Notes 4/23/2015 John Stensby m(t) a) xDSB(t) = Acm(t)cosct Accosct m(t) b) t (t) DSB x c) t Figure 2-1: a) Block diagram of a DSB modulator. -
Signi\L PURITY CONS IDERI\TIONS for FREQUEN<:Y Sn1 Tiles I ZED Llel\DEND EQU I Pr1ent David L. Kel:Na General Instrument
SIGNi\L PURITY CONS IDERI\TIONS FOR FREQUEN<:Y Sn1 TilES I ZED llEl\DEND EQU I Pr1ENT David L. Kel:na General Instrument, Jerrold Division ABSTRACT BASIC OVERVIEW OF THE PLL As cabl~ television system band Before we evoluate the system for wirlths increase and frequency plans pro its noise performance, let us first re liferate, more manufacturers are turning view the b~sic operation of a chase to synth~sized frequency agile head~nd locked loop. A simple phase-locked loop channel converters. Uith this new ap consists of a voltage controlled oscil proach using phased lo~ked loops and dual lator, or VCO, a digital divider, a chase conversion come spurious signals and detector, a reference frequency sour~e, nois~ sources not encountered before in and an integrator or loop filter. Figure crystal controlled channel converters. 1 represents such a system. Important characteristics of these These system components function ~s headend converters including phas~ noise, a s~rvo loop sue~ that when the·vco is spurious sign3ls generated by the compar phase-locked to the reference, the output ison frequ~ncy, and residual frequency frequency and phase of the digital divi a~d phase modulation, are evaluated for der is equal to the frequency and phase their subjective impact on the output of the referenc~. This makes the average signal to the cable. D3ta is presented output of the phase detector zero and, which shows the correlation between sub therefore, the output of the loop filter jective picture degradation and measured remains unchanged. Should a disturbance headend synthesizer noise contribution. -
Amplitude Modulation “AM” with Envelope Detector
Amplitude Modulation “AM” with Envelope Detector Large S/N limit m1< s(t) ≅ sin ωm t ≤ 1 Recei ved = y(t) = Ac [1 + m s( t)] cos ωc t + nc (t)cos ωc t + ns (t)s in ωct j ωct = Re {Y (t)e } slowly varying y, low-pass filtered (envelope) “overmodulation” = distortion (“undermodulation = wasted power) Lec 16b.6-1 2/2/01 T1 Amplitude Modulation “AM” with Envelope Detector Recei ved = y(t) = Ac [1 + m s( t)] cos ωc t + nc (t)cos ωc t + ns (t)s in ωct j ωct = Re {Y (t)e } slowly varying Im {Y (t)} Y(f ) 2W Y(t) ns(t) n(t) R e {Y(t) } f 0 0 fc A [1 + m s(t)] nc(t) N = kT c o 2 Lec 16b.6-2 2/2/01 T2 Amplitude Modulation “AM” with Envelope Detector Im {Y (t)} Y(f ) 2W Y(t) ns(t) n(t) R e {Y(t) } f 0 0 fc A [1 + m s(t)] nc(t) N = kT c o 2 Y(t) ≅ A [1 + m s(t)] + n (t) N c c envelope = detected signal + noise 2 2 2 2 2 Note: 4WNo = nc cos ωc t + ns sin ωc t = nc 222 Sout 222 2 Ac ms (t) ≅ Ac m s (t) nc (t) = Nout 4WNo Lec 16b.6-3 2/2/01 T3 Amplitude Modulation “AM” with Envelope Detector 222 Sout 222 2 Ac ms (t) ≅ Ac m s (t) nc (t) = Nout 4WNo 2 2 A 2 (1 + m s(t)) Sin ( c ) 2 ≅ where Sin = y signal(t) Nin 4WNo 22 ∆ SNi i 1m+ s (t) 11+ 2 Noi se figure FAM = = ≥ = 3 2 ⇒ FAM ≥ 3 2 SNo o 2m 22s 1 provided that Ac >> nc (large S/N limit) Lec 16b.6-4 2/2/01 T4 AM Performance (small S/N limit) Im {Y } φ (t) n A1c [ + m s(t)] n(t) ≅ Ac [1 + m s( t)] cos φn (t) φn (t) R e {}Y Y(t) ≅ n(t) + A cos φ (t) + A m s( t)cos φ (t) c n c n multiplicative noise! Want Sin Nin ≥ 10 for fully i ntel ligibl e AM ⇒ "AM threshold" ( i.e. -
Low-Power RFED Wake-Up Receiver Design for Low-Cost Wireless Sensor Network Applications
sensors Article Low-Power RFED Wake-Up Receiver Design for Low-Cost Wireless Sensor Network Applications David Galante-Sempere , Dailos Ramos-Valido, Sunil Lalchand Khemchandani and Javier del Pino * Institute for Applied Microelectronics (IUMA), University of Las Palmas de Gran Canaria (ULPGC), 35017 Las Palmas de Gran Canaria, Spain; [email protected] (D.G.-S.); [email protected] (D.R.-V.); [email protected] (S.L.K.) * Correspondence: [email protected] Received: 28 September 2020; Accepted: 6 November 2020; Published: 10 November 2020 Abstract: The development of wake-up receivers (WuR) has recently received a lot of interest from both academia and industry researchers, primarily because of their major impact on the improvement of the performance of wireless sensor networks (WSNs). In this paper, we present the development of three different radiofrequency envelope detection (RFED) based WuRs operating at the 868 MHz industrial, scientific and medical (ISM) band. These circuits can find application in densely populated WSNs, which are fundamental components of Internet-of-Things (IoT) or Internet-of-Everything (IoE) applications. The aim of this work is to provide circuits with high integrability and a low cost-per-node, so as to facilitate the implementation of sensor nodes in low-cost IoT applications. In order to demonstrate the feasibility of implementing a WuR with commercially available off-chip components, the design of an RFED WuR in a PCB mount is presented. The circuit is validated in a real scenario by testing the WuR in a system with a pattern recognizer (AS3933), an MCU (MSP430G2553 from TI), a transceiver (CC1101 from TI) and a T/R switch (ADG918). -
Optical Injection Locking: from Principle to Applications Zhixin Liu, Senior Member, IEEE, Radan Slav´Ik, Senior Member, IEEE (Invited Tutorial)
JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. XX, NO. X, JANUARY 2020 1 Optical Injection Locking: from Principle to Applications Zhixin Liu, Senior Member, IEEE, Radan Slav´ık, Senior Member, IEEE (Invited Tutorial) Abstract—This paper reviews optical injection locking (OIL) of semiconductor lasers and its application in optical communications and signal processing. Despite complex OIL dynamics, we attempt to explain the operational principle and main features of the OIL in an intuitive way, aiming at a wide understanding of the OIL and its asso- ciated techniques in the optic and photonic communities. We review and compare different control techniques that Figure 1. Schematics of optical injection-locked laser system. (a) enable robust OIL in practical systems. The applications Reflection type and (b) Transmission type. are reviewed with a focus on new developments in the past decade, under the categories of ‘High Speed Directly Modulated Lasers’ and ‘Optical Carrier Recovery’. Finally, laser will also follow any slow frequency drift of the we draw our vision for future research directions. master laser with a relatively constant output power. Index Terms—Laser dynamics, Optical communications, Laser synchronization plays important roles in nu- Optical transmitters, Optical injection locking, Direct mod- merous applications. In optical communications, syn- ulation, Coherent receiver, Carrier recovery, Frequency chronized lasers are used as local oscillators (LOs) to comb, Time and frequency transfer reduce the complexity and latency in coherent receivers [2]–[5]. In conjunction with optical frequency comb, OIL coherently demultiplexes optical tones for dense I. INTRODUCTION wavelength division multiplexed (DWDM) systems or PTICAL injection locking (OIL) is an optical fre- super channel transmitters [6]–[9], enabling high spec- O quency and phase synchronization technique based tral efficiency communications. -
On the Design of Injection-Locked Frequency Dividers for Mm
ON THE DESIGN OF INJECTION-LOCKED FREQUENCY DIVIDERS FOR MM- WAVE APPLICATIONS by Lakshmi Lavanya Bodepu B.Tech., Indian Institute of Technology, Kharagpur, 2016 A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF APPLIED SCIENCE in THE FACULTY OF GRADUATE AND POSTDOCTORAL STUDIES (Electrical and Computer Engineering) THE UNIVERSITY OF BRITISH COLUMBIA (Vancouver) Novemeber 2019 © Lakshmi Lavanya Bodepu, 2019 The following individuals certify that they have read, and recommend to the Faculty of Graduate and Postdoctoral Studies for acceptance, a thesis entitled: ON THE DESIGN OF INJECTION-LOCKED FREQUENCY DIVIDERS FOR MM- WAVE APPLICATIONS submitted by Lakshmi Lavanya Bodepu in partial fulfillment of the requirements for the degree of Master of Applied Science in Electrical and Computer Engineering Examining Committee: Prof. Shahriar Mirabbasi, Electrical and Computer Engineering Supervisor Prof. Sudip Shekhar, Electrical and Computer Engineering Supervisory Committee Member Prof. Alireza Nojeh, Electrical and Computer Engineering Supervisory Committee Member ii Abstract This work presents the design and measurement results of two injection-locked frequency dividers (ILFDs) that are intended for mm-wave applications. The two prototypes are fabricated in a 65-nm CMOS process. The first direct-injection ILFD achieves a measured locking range of 24.5 GHz to 43 GHz while consuming 1.3 mW from a 0.48-V supply with a 0 dBm input injection power. The second ILFD design is based on the dual-injection multi-band architecture and as compared to the first design enhances the locking range by a factor of 2. The dual-injection ILFD achieves a locking range of 18 GHz to 61 GHz while consuming 1.8 mW from a 0.5-V supply with a 0 dBm input injection power. -
Injection Locking Techniques for CMOS-Based Mm-Wave Frequency Synthesis
Faculteit Ingenieurswetenschappen Department of Electronics and Informatics (ETRO) Department of Fundamental Electricity and Instrumentation (ELEC) Injection Locking Techniques for CMOS-Based mm-Wave Frequency Synthesis Proefschrift voorgelegd voor het behalen van Doctor in de Ingenieurswetenschappen door Giovanni Mangraviti Promotoren: Prof. Dr. ir. Piet Wambacq Prof. Dr. ir. Gerd Vandersteen Jury: Prof. Dr. ir. H. Ottevaere, voorzitter, VUB Prof. Dr. ir. R. Pintelon, vice-voorzitter, VUB Prof. Dr. ir. Y. Rolain, secretaris, VUB Dr. ir. J. Craninckx, imec Prof. Dr. ir. M. Kuijk, VUB Prof. Dr. ir. S. Levantino, Politecnico di Milano In samenwerking met imec vzw, Kapeldreef 75 B-3001 Leuven, Belgie¨ Onderzoek gefinancierd met een specialisatiebeurs van het Instituut voor de Aanmoediging van Innovatie door Wetenschap en Technologie in Vlaanderen (IWT- Vlaanderen) Januari 2015 Preface Dear reader, with gladness I present you my Ph.D. thesis. It deals with Injection Locking Tech- niques for CMOS-Based mm-Wave Frequency Synthesis. Thanks to injection locking, high frequencies such as millimeter waves can be handled on a standard digital CMOS technology. The fascinating challenge of injection locking resides in the fact that we want to synchronize, with an external reference signal, the oscillatory response of an unstable system such as an oscillator. This duality between synchronization and oscillatory re- sponse has been inspiring me along the whole Ph.D. research. I think I can say that this duality has been translated into another one, typical of so many Ph.D. students: giving structure to a passionate research. i Acknowledgments As Ph.D. student and as young man, I feel grateful to so many people, who have accom- panied me during this journey towards the Ph.D. -
Easy Fourier Analysis
SpectrumDCInformationSignal term at 2won signal cthe positivenegative Half is up This half is .3 x-axis .5 shifted. down shifted. Charan Langton, TheEditor Carrier fm = -1 fm = 1 -9 9 -9, fc-9, -8, = -8, -8-7 -7 -7 7, fc7 7,8,= 8 8,9 9 -9, -8, -7 7, 8, 9 SIGNAL PROCESSING & SIMULATION NEWSLETTER Baseband, Passband Signals and Amplitude Modulation The most salient feature of information signals is that they are generally low frequency. Sometimes this is due to the nature of data itself such as human voice which has frequency components from 300 Hz to app. 20 KHz. Other times, such as data from a digital circuit inside a computer, the low rates are due to hardware limitations. Due to their low frequency content, the information signals have a spectrum such as that in the figure below. There are a lot of low frequency components and the one-sided spectrum is located near the zero frequency. .......... Figure 1 - The spectrum of an information signal is usually limited to low frequencies The hypothetical signal above has four sinusoids, all of which are fairly close to zero. The frequency range of this signal extends from zero to a maximum frequency of fm. We say that this signal has a bandwidth of fm. In the time domain this 4 component signal may looks as shown in Figure 2. Figure 2 - Time domain low frequency information signal Now let’s modulate this signal, which means we are going to transfer it to a higher (usually much higher) frequency. Just as information signals are characterized by their low frequency, the transmission medium, or carriers are characterized by their high frequency. -
Architectures and Circuits Leveraging Injection-Locked Oscillators For
Architectures and Circuits Leveraging Injection-Locked Oscillators for Ultra-Low Voltage Clock Synthesis and Reference-less Receivers for Dense Chip-to-Chip Communications Gautam R. Gangasani Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in the Graduate School of Arts and Sciences COLUMBIA UNIVERSITY 2018 ○c 2018 Gautam R. Gangasani All rights reserved Architectures and Circuits Leveraging Injection-Locked Oscillators for Ultra-Low Voltage Clock Synthesis and Reference-less Receivers for Dense Chip-to-Chip Communications Gautam R. Gangasani Abstract High performance computing is critical for the needs of scientific discovery and eco- nomic competitiveness. An extreme-scale computing system at 1000x the performance of today’s petaflop machines will exhibit massive parallelism on multiple vertical fronts, from thousands of computational units on a single processor to thousands of processors in a single data center. To facilitate such a massively-parallel extreme-scale computing, a key challenge is power. The challenge is not power associated with base computation but rather the problem of transporting data from one chip to another at high enough rates. This thesis presents architectures and techniques to achieve low power and area footprint while achieving high data rates in a dense very-short reach (VSR) chip-to-chip (C2C) communication network. High-speed serial communication operating at ultra-low supplies improves the energy-efficiency and lowers the power envelop of a system doing an exaflop of loops. One focus area of this thesis is clock synthesis for such energy-efficient interconnect applications operating at high speeds and ultra-low supplies. -
A Novel Wide-Band Envelope Detector
RMO3B-5 A Novel Wide-Band Envelope Detector Yanping Zhou, Guochi Huang, Sangwook Nam* and Byung-Sung Kim School of Information and Communication, Sungkyunkwan University, Suwon, Korea *School of Electrical Engineering and INMC, Seoul National University, Seoul, Korea Abstract — In this paper, we present a novel wide-band envelope detector comprising a fully-differential operational transconductance amplifier (OTA), a full-wave rectifier and a peak detector. To enhance the frequency performance of the envelop detector, we utilize a gyrator-C active inductor load in the OTA for wider bandwidth. Additionally, it is Fig. 1. Envelope detector with OTA-rectifier-peak-detector shown that the high-speed rectifier of the envelope detector requires high bias current instead of the sub-threshold bias open loop. condition. The experimental results show that the proposed envelope detector can work from 100-Hz to 1.6-GHz with an input dynamic range of 50-dB at 100-Hz and 40-dB at 1.6- GHz, respectively. The envelope detector was fabricated on the TSMC 0.18-um CMOS process with an active area of 0.652 mm2. 3BIndex Terms — Envelope detector, Peak detector, OTA, Rectifier, Gyrator-C active inductor, Wide-band. I. INTRODUCTION The envelope detector is extensively applied in the control and energy estimation systems [1]-[3] to track the amplitude of input signals. Recently, many systems require envelope detectors capable of treating with high frequency input signals, such as embedded RFIC test bench [4], AM/ASK receiver and so on. For this reason, Fig. 2. Schematic diagram of the cascode OTA circuit. this work is dedicated to realize a high-frequency and wide-band envelope detector.