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A 11-15 Ghz CMOS ÷2 FREQUENCY DIVIDER for BROAD-BAND I/Q GENERATION Annamaria Tedesco, Andrea Bonfanti, Luigi Panseri, Andrea Lacaita

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A 11-15 Ghz CMOS ÷2 FREQUENCY DIVIDER for BROAD-BAND I/Q GENERATION Annamaria Tedesco, Andrea Bonfanti, Luigi Panseri, Andrea Lacaita View metadata, citation and similar papers at core.ac.uk brought to you by CORE provided by Archivio istituzionale della ricerca - Politecnico di Milano A 11-15 GHz CMOS ÷2 FREQUENCY DIVIDER FOR BROAD-BAND I/Q GENERATION Annamaria Tedesco, Andrea Bonfanti, Luigi Panseri, Andrea Lacaita Dipartimento di Elettronica ed Informazione - Politecnico di Milano, P.za Leonardo da Vinci 32, I-20133 Milano, Italy E-mail: [email protected] ABSTRACT solutions, as LC injection locking topology. Then we discuss the circuit topology and we show why this circuit This paper presents a 0.13 µm CMOS frequency divider can achieve a wide tuning range. We present the circuit for I/Q generation. To achieve a wide locking range, a implementation, some experimental results and, then, the novel topology based on a two stages injection-locking conclusions will follow. ring oscillator is adopted. This architecture can reach a larger input frequency range and better phase accuracy 2. HIGH-SPEED DIVIDERS with respect to injection-locking LC oscillators, because of the smoother slope of its phase-frequency plot. Post layout High-speed dividers are typically realized as two latches in simulations show that the circuit is able to divide an input a negative feedback loop [1]. For multi-GHz input signals, signal spanning from 6 to 24 GHz, although the available these circuits have a differential current-steering structure tuning range of the signal source (integrated VCO) limited that allows fast current switching, usually called source- the experimental verification to the interval 11-15 GHz, coupled logic (SCL). To reduce the dissipation a dynamic with a consequent measured 31% locking range. A single logic was employed in [2], but it does not provide I/Q divider dissipates 3 mA from 1.2 V power supply. outputs. Probably, the best solution in term of power consumption is to differentially drive two injection 1. INTRODUCTION locking LC oscillators, as in [3]. With respect to the SCL dividers the dissipation reduces by about Q, the quality High-speed frequency dividers are among the most critical factor of the divider’s resonant tank, at the cost of a large building blocks in modern CMOS wireless tranceivers. area occupation. Unfortunately, this topology is They are employed both in the feedback path of Phase intrinsically narrow band: to increase the divider locking Locked Loops (PLL) and to generate the I/Q quadrature range the quality factor Q of the LC tanks must be signals necessary in zero- or low-IF receivers. The design lowered with a resulting rise in dissipation. Our locking of a fully integrated CMOS divider is critical, above all for range requirements demand a low Q, close to two, its power consumption that is comparable to the one of the practically voiding the effect of the LC resonance. In this Voltage Controlled Oscillator (VCO). This problem sense, power is traded not only with speed, but also with becomes even more severe when a wide input frequency input locking range. A further example of this trend is the range is required, since in this case it is not possible to 40 GHz divider presented in [4], which demonstrates good adopt resonant loads, that would allow power reduction. power performance but features 6 % locking range. Moreover, the dissipation of a broad-band buffer, usually interposed between the VCO and the divider itself, must 2.1 Proposed injection-lock ring divider be also taken in to account in the total power budget. We discuss a topology for a ÷2 frequency divider for I/Q Our approach was to injection-lock a wide tuning range generation in a WLAN transceiver for IEEE 802.11a/b/g oscillator, namely a two-stages ring oscillator. Self standards. In the frequency synthesizer only one VCO will oscillating dividers have also the useful property of be employed, and a first divider provides the I/Q signals requiring less power from the driving signal, avoiding the for the 802.11a channels without using an input buffer. use of a power consuming buffer. Fig.1 shows the circuit Then, a following divider makes the signals for the 2.5 scheme and the detail of one stage. Simulations show that GHz band available. The key advantage of this the transfer function of the single stage can be architecture is that VCO pulling is avoided. Given the approximated as: channellizations of the standards, the input frequency of the first divider must vary between 9.6 and 11.6 GHz, 1j−ωωz Tj()ω= T0 (1) leading to 18 % input tuning, or locking, range. However, 1j+ωωp a more conservative figure for the locking range is 35%, to account for the process spreads in the VCO. In the next The small signal dc gain is T = g R/(1 – g R), being g section we will recall why such high tuning range makes 0 mi mc mI and g the transconductances of transistors M -M and M - not possible to adopt some recently presented low-power mc 1 2 3 1° Stage I Q IDC@0 ϕ αv2 + _ ω ω i @2ω ω in _ in in in in + V1 VDD gmc v2 α R R M3 M 0° 180° _ 4 IDC@0 + ω in -i @2ω _ ϕ in in 2ω M1 M2 in + gmi -1 V1 M5 2ω 2° Stage in V bias Figure 2. The injection locking mechanism in Figure 1. Ring frequency divider driven by a the two stages ring oscillator. differential VCO. The scheme of one stage is also superimposed to the dc tail bias current IDC. In this way the ω ω M4 respectively. The dominant pole frequency is P=(1– ring is forced to oscillate at in, which is in general g R)/C R, where C is the output load capacitance. ω mc O O different from 0. The mechanism of injection locking has Owing to the gate-drain overlap capacitance of the input been rigorously discussed by many authors, see for couple M1-M2, the transfer function also exhibits a right instance [3], [6], [7] and is intuitively recalled with the ω half-plane zero at higher frequency, Z = gmi/Cgd To satisfy help of Fig. 2. the Barkhausen criterion for loop phase, a lag of – π/2 A steady condition is reached when the ring oscillates at radians is required for each stage, providing in this way ω . In this case the input pair M -M in Fig. 1 behaves as a the quadrature outputs. The cross-connection between the in 1 2 mixer for the signal coming from the tail and thus two stages in Fig.1 gives the remaining phase shift of π. converts I and i to ω . The dominant pole of each stage The – π/2 delay is reached only thanks to the right zero, DC in in filters out the higher-frequency products. Since ω differs and it is straightforward from (1) to evaluate that this shift in from ω , the lag of each stage is not exactly –π/2 but it is – is achieved at a frequency corresponding to the geometric 0 π ϕ mean between the pole and the zero. The ring oscillation /2– . The mixer stage must balance this phase shift ϕ frequency is thus ω = (ω ω )1/2. Using (1) and the adding the opposite shift to its output. That is sketched 0 p z ω Barkhausen criterion for loop magnitude, we obtain the in Fig. 2, where all the represented phasors rotate at in. V1 condition for the dc gain: T (ω /ω )1/2 = 1. Then, when represents the output signal as a result of the dc current, 0 p z while v is the additional signal caused by the injected the amplitude rises, the “effective” transconductance of 2 the cross-coupled pair M -M reduces with respect to the current. The loop adjusts the phasors, by settling the angle 3 4 α, in order to obtain an additional shift ϕ, with respect to initial small signal value gmc/2, until the oscillation becomes stable. It’s important to note, from the expression the state in which there’s not injection of current. It is easy to see that when a differential signal, iin and –iin, is forced of the dominant pole frequency, that also ωP and, ω ω ω in the two stages, their outputs are still in quadrature. It is accordingly, 0 vary. Both P and 0 increase when the also possible to evaluate which is the the maximum transconductance of the pair M3-M4 lowers. In an ∆ω ω frequency deviation, , from 0 so that the divider can oscillator this effect would lead to very poor performance properly operate, [7]. If we call SL the magnitude of the in term of frequency stability and phase noise. In our slope, evaluated at ω , of the phase vs. frequency application we do not face this problem, since the circuit is 0 characteristic of T(jω), it results SL ≅ ϕ/∆ω. If we define driven by an input signal. the injection strength m = v2/V1 = iin/IDC, Fig.2 shows that, ϕ ≅ A similar analysis can be found in [5], though the circuit with a good approximation, is max m, and consequently in that case is a standard SCL divider, and only simulation ∆ω ≅ max m/SL. Consequently the lock range increases with results are shown. In our case the cross-coupled pair acts m, and it is also inversely proportional to SL. From as a gain-boosting stage at the start-up and then as an equation (1) it is possible to simply evaluate the amplitude limiter to stabilize the oscillation, and not as a magnitude of the slope.
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