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UNIVERSITY of CALIFORNIA, IRVINE 100Gbps Half-Rate UNIVERSITY OF CALIFORNIA, IRVINE 100Gbps Half-Rate Referenceless Injection-Locking Clock/Data Recovery Circuit in 0.18 µm BiCMOS Process DISSERTATION submitted in partial satisfaction of the requirements for the degree of DOCTOR OF PHILOSOPHY in Electrical and Computer Engineering by Behzad Samavaty Dissertation Committee: Professor Michael Green, Chair Professor Ender Ayanoglu Professor Nader Bagherzadeh 2017 ©2017 Behzad Samavaty DEDICATION To my wonderful parents, brother and sister, for their enduring love and support, and my beautiful wife for her dedication and partnership ii TABLE OF CONTENTS LIST OF FIGURES ................................................................................................................. v LIST OF TABLES ................................................................................................................ vii ACKNOWLEDGEMENTS .................................................................................................... viii CURRICULUM VITAE .......................................................................................................... ix ABSTRACT OF THE DISSERTATION ................................................................................... x 1. INTRODUCTION .............................................................................................................. 1 1.1 NRZ and RZ Data Formats...............................................................................................3 1.2 Clock/Data Recovery System .........................................................................................5 1.2.1 Phase Detector-based CDR ................................................................................................... 7 1.2.2 Blind ADC-based CDR .......................................................................................................... 12 1.2.3 Injection-Locking-based CDR ............................................................................................. 14 1.3 Dissertation Outline ..................................................................................................... 16 2. INJECTION LOCKING ..................................................................................................... 18 2.1 Background ................................................................................................................... 18 2.2 Injection Locking Analysis ........................................................................................... 22 2.3 Injection Locking in Electrical Oscillators ................................................................... 26 2.4 Injection Locking Jitter Analysis .................................................................................. 29 2.5 Injection locking for Clock/Data Recovery ................................................................. 31 3. INJECTION LOCKING for CLOCK/DATA RECOVERY APPLICATIONS .......................... 32 3.1 Pulse Generation ........................................................................................................... 32 3.2 Pulse Generation in the Prior Art ................................................................................ 36 3.3 Pulse Generation in the Proposed Architecture ......................................................... 40 3.3.1 Circuit Model and Analysis ................................................................................................. 44 3.3.2 Simulation Results ............................................................................................................... 47 4. 100 GBPS HALF-RATE REFERENCELESS INJECTION LOCKING CLOCK/DATA RECOVERY CIRCUIT .......................................................................................................... 52 4.1 Referenceless Injection Locking CDR Architecture .................................................... 52 4.2 VCO Frequency Tuning ................................................................................................. 54 4.2.1 Capacitive Tuning ................................................................................................................ 54 iii 4.2.2 Inductive Tuning .................................................................................................................. 57 4.2.3 Inductive Tuning Mismatch Analysis ................................................................................. 60 4.2.4 Fully Differential Active Tuning Circuit Topology ............................................................ 62 4.2.5 Tuning Circuitry analysis .................................................................................................... 66 4.2.6 Phase Noise .......................................................................................................................... 70 4.3 High-Speed CML Buffers ............................................................................................... 73 4.4 Variable-Delay Buffer ................................................................................................... 78 4.5 Dynamic D Flip-Flops .................................................................................................... 81 4.6 Referenceless Frequency Acquisition Loop ................................................................ 83 4.6.1 Second-Harmonic 100GHz Mixer ....................................................................................... 86 4.6.2 Transition Detector ............................................................................................................. 88 4.7 Time-Domain Test ........................................................................................................ 89 4.7.1 PRBS Generator ................................................................................................................... 90 4.7.2 8X Clock Multiplier .............................................................................................................. 94 4.8 Chip Top Level ............................................................................................................... 97 5. Conclusions ................................................................................................................. 100 Bibliography ............................................................................................................................ 101 iv LIST OF FIGURES Figure 1. Optical communication system .................................................................................... 1 Figure 2. Broadband communication receiver ........................................................................... 3 Figure 3. (a) NRZ and (b) RZ data formats .................................................................................. 4 Figure 4. Spectrum of NRZ and RZ data ....................................................................................... 5 Figure 5. Conventional PD based CDR ......................................................................................... 8 Figure 6. Hogge phase detector .................................................................................................. 10 Figure 7. Binary phase detector ................................................................................................. 11 Figure 8. Blind sampling ADC based CDR[5] ............................................................................. 13 Figure 9. Time-interleaved ADC architecture ........................................................................... 13 Figure 10.Injection locking clock recovery ............................................................................... 16 Figure 11. Simple mechanical modeling of injection locking, pendulum and drum .............. 20 Figure 12. Unwanted injection locking in multi-channel systems [8] .................................... 21 Figure 13. Resonator model ....................................................................................................... 23 Figure 14.Resonator with a phase shifter in the loop resonating off the resonance frequency ............................................................................................................................................... 24 Figure 15. Injection Locking model in electrical oscillators .................................................... 25 Figure 16. Oscillator under injection ......................................................................................... 27 Figure 17. Injection Locking vector analysis ............................................................................. 27 Figure 18. Maximum phase shift resulted from injection ........................................................ 28 Figure 19. Injection locking jitter analysis ................................................................................ 30 Figure 20. (a) NRZ signal; (b) 0101 pulses with phase change; (c) random pulses. ............. 33 Figure 21. Spectrum of the PRBS7 100Gb/s data ..................................................................... 34 Figure 22. Spectrum of the phase-varying 0101 sequence, a phase modulated 50 GHz signal ............................................................................................................................................... 35 Figure 23. (a) Random NRZ sequence (b) Neutralized generated pulses from random NRZ sequence suitable for injection .......................................................................................... 35 Figure 24. XOR based pulse
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