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Iiâ•Fivi Epitaxial Films in Nonvolatile Memory, 3-State Fets, and Solar

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Iiâ•Fivi Epitaxial Films in Nonvolatile Memory, 3-State Fets, and Solar University of Connecticut OpenCommons@UConn Doctoral Dissertations University of Connecticut Graduate School 5-11-2013 II–VI Epitaxial Films in Nonvolatile memory, 3-state FETs, and Solar Cells Ernesto Suarez [email protected] Follow this and additional works at: https://opencommons.uconn.edu/dissertations Recommended Citation Suarez, Ernesto, "II–VI Epitaxial Films in Nonvolatile memory, 3-state FETs, and Solar Cells" (2013). Doctoral Dissertations. 92. https://opencommons.uconn.edu/dissertations/92 II–VI Epitaxial Films in Nonvolatile memory, 3-state FETs, and Solar Cells Ernesto Suarez PhD University of Connecticut 2013 ABSTRACT This thesis presents design and fabrication of improved performance FETs, nonvolatile memories, and solar cells. The key feature is the use of wide band gap II-VI quantum well layers and/or quantum dots which are grown using UltraViolet (UV) low temperature Metal-Organic Chemical Vapor Deposition (MOCVD) heteroepitaxy. These layers serve as an insulating substitute for gate insulators such as SiO 2 or HfO 2. The motivation behind using II-VI lattice- matched gate dielectrics is two-fold: (1) to reduce interface states and their adverse impact on threshold voltage, in particular its variation from device-to- device in sub-22nm structures, and (2) to utilize the higher dielectric constant of ZnMgS with respect to SiO 2. The material structure for this tunneling layer is ZnS/Zn 0.95 Mg 0.05 S/ZnS. A 5 nm layer of ZnSe is grown on both sides of this stack to aide with heteroepitaxial adhesion. Auger SIMS surface scan and depth profile data is presented. This ZnSe layer is less than the critical layer thickness therefore is negligible to additional dislocations due to lattice mismatch strain. These II-VI layers are grown at 333 o C with a vertical chamber pressure of 250 torrs at 14.25 slm of hydrogen carrier gas. The metal-organic sources used are dimethylzinc (DMZn), dimethylselenide (DMSe), diethylsulfide (DES), and bismethyl- cyclopentadienylmagnesium ((MeCp)2Mg). Three state FETs have a quantum dot gate comprised of two monolayers of germanium oxide cladded germanium quantum dots (GeO x-Ge). These dots trap charge creating an intermediate state “i” within the FET characteristics. The II-VI tunneling layer provides a smoother transition between ON, i, and OFF states by reducing interface states between the channel and the gate. Nonvolatile memory FETs transfer charge from the channel to a floating gate. As the gate width approaches sub 22nm, the threshold voltage variation is significantly controlled by interface states between the floating gate and the channel. A heteroepitaxial tunneling layers greatly reduces this threshold voltage variation by reducing the trapped charge states. Substrate material platforms such as InGaAs/InP and Si are been explored. In addition, 3-state quantum dot gate FETs (having QDs assembled on II-VI layers) and nonvolatile memories on SOI have been designed, fabricated, and tested. II-VI layers, used as the wide energy gap window region, provide efficient solar cell structures. Fabrication of nZnSe-pGe cells is presented. These devices are constructed using a mesa etch and Indium metal top contacts. Photoluminescence characterization (30 K 4x10 -5 Torrs) on ZnS(Cl -) films resulted with a bandgap of 2.87 eV. (Run 1857) ii II–VI Epitaxial Films in Nonvolatile memory, 3-state FETs, and Solar Cells Ernesto Suarez B.S. University of Connecticut 2006 M.S. University of Connecticut 2010 A Dissertation Submitted in Partial Fullfillment of the Requirements for the Degree of Doctor of Philosophy at the University of Connecticut 2013 iii Copyright by Ernesto Suarez 2013 iv APPROVAL PAGE Doctor of Philosophy Dissertation II–VI Epitaxial Films in Nonvolatile memory, 3-state FETs, and Solar Cells Presented by Ernesto Suarez B.S., M.S. Major Advisor _______________________________________ Faquir Jain Associate Advisor _______________________________________ John E. Ayers Associate Advisor _______________________________________ Lei Wang Associate Advisor _______________________________________ John Chandy University of Connecticut 2013 v Table of Contents ABSTRACT ........................................................................................................... i APPROVAL PAGE ............................................................................................... v List of Tables ........................................................................................................xi List of Figures ...................................................................................................... xii Acknowledgements ............................................................................................ xvi Chapter 1 Introduction .......................................................................................... 1 Chapter 2 Background .......................................................................................... 3 2.1 Background ................................................................................................. 3 2.2 Wide gap semiconductor devices ................................................................ 4 2.3 Dislocations ................................................................................................. 4 2.4 II-VI Semiconductors ................................................................................... 6 2.4.1 Zinc Sulfide (ZnS) and Zinc Magnesium Sulfide (ZnMgS) .................... 8 2.4.2 Zinc Selenium Telluride (ZnSeTe) – Zinc Magnesium Selenium Telluride (ZnMgSeTe) .................................................................................... 8 2.5 Characterization Techniques ....................................................................... 9 2.5.1 Auger SIMS Surface Scan Microscopy and Depth Profile .................... 9 vi 2.5.2 X-Ray Diffraction ................................................................................. 10 2.5.3 Photoluminescence ............................................................................. 12 2.6 II-VI Epitaxial Growth ................................................................................. 13 2.7 II-VI Devices .............................................................................................. 14 2.7.1. 3-state FETs ...................................................................................... 15 2.7.2 Non Volatile Memory Devices ............................................................. 20 2.7.3 Quantum Dot Floating Gate Nonvolatile Memories ............................. 24 2.7.4 FET on SOI Substrates ....................................................................... 28 2.7.5 InGaAs/InP FET .................................................................................. 32 2.8 Self Organization of Quantum Dots ........................................................... 33 2.8.1 Self Organized Quantum Dot Gate FET .............................................. 34 2.9 Solar Cells ................................................................................................. 36 2.9.1 Advantages of ZnSe/GaAs Solar Cell ................................................. 36 Chapter 3 Simulations ........................................................................................ 38 3.1 Introduction ............................................................................................... 38 3.2 3-state Simulations .................................................................................... 39 3.3 NVMFET Simulations ................................................................................ 43 3.4 Simulations of 3-state FET on SOI ............................................................ 46 3.5 Simulations of NVMFET on SOI ................................................................ 49 Chapter 4 Fabrication ......................................................................................... 54 vii 4.1 Sample Preparation ................................................................................... 54 4.1.1 Wafer Preparation Silicon Wafer <100> ............................................. 55 4.1.2 InGaAs/InP Wafer Preparation ............................................................ 56 4.1.3 GaAs Wafer Preparation ..................................................................... 57 4.2 MOVPE Growth materials and equipment ................................................. 59 4.2.1 Source materials ................................................................................. 61 4.2.2 Reactor ............................................................................................... 62 4.3 Growth Procedures ................................................................................... 64 4.3.1 MOCVD loading procedure ................................................................. 64 4.3.2 MOCVD Tunnel growth procedure ..................................................... 65 4.4 Silicon FET Fabrication ............................................................................. 67 4.5 Fabrication of 3-state FET on silicon ......................................................... 67 4.6 Deposition of II-VI Gate Insulator Layers ................................................... 68 4.7 GeO x-Ge Quantum Dot Floating gate deposition ...................................... 69 4.8 Fabrication of II-VI Nonvolatile Memory Structure on Bulk Silicon ............ 71 4.9 SOI NVMFET Fabrication .........................................................................
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