DOCSLIB.ORG

VT82C686B ¦Super South§ South Bridge

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
VT82C686B ¦Super South§ South Bridge 9,$ 7HFKQRORJLHV 'HOLYHULQJ 9DOXH 97&% ¦6XSHU6RXWK§6RXWK%ULGJH 36,3& 3&,6XSHU,2,QWHJUDWHG3HULSKHUDO&RQWUROOHU 3&&203/,$173&,72,6$%5,'*( :,7+,17(*5$7('683(5,2 )'&/37&20$1',5 ,17(*5$7('6281'%/$67(5',5(&76281'$&$8',2 8/75$'0$0$67(502'(3&,(,'(&21752//(5 86%&21752//(5.(<%2$5'&21752//(557& ',675,%87(''0$6(5,$/,543/8*$1'3/$< $&3,(1+$1&('32:(50$1$*(0(1760%86$1' 7(03(5$785(92/7$*($1')$163(('021,725,1* 5HYLVLRQ $XJXVW 9,$7(&+12/2*,(6,1& &RS\ULJKW1RWLFH &RS\ULJKW 9,$ 7HFKQRORJLHV ,QFRUSRUDWHG 3ULQWHG LQ WKH 8QLWHG 6WDWHV $// 5,*+76 5(6(59(' 1R SDUW RI WKLV GRFXPHQW PD\ EH UHSURGXFHG WUDQVPLWWHG WUDQVFULEHG VWRUHG LQ D UHWULHYDO V\VWHP RU WUDQVODWHG LQWR DQ\ ODQJXDJH LQ DQ\ IRUP RU E\ DQ\ PHDQV HOHFWURQLF PHFKDQLFDO PDJQHWLF RSWLFDO FKHPLFDO PDQXDO RU RWKHUZLVH ZLWKRXW WKH SULRU ZULWWHQ SHUPLVVLRQ RI 9,$ 7HFKQRORJLHV ,QFRUSRUDWHG 97&$ 97&% DQG 6XSHU 6RXWK PD\ RQO\ EH XVHG WR LGHQWLI\ SURGXFWV RI 9,$ 7HFKQRORJLHV ,QF LD D UHJLVWHUHG WUDGHPDUN RI 9,$ 7HFKQRORJLHV ,QFRUSRUDWHG 3670 LV D UHJLVWHUHG WUDGHPDUN RI ,QWHUQDWLRQDO %XVLQHVV 0DFKLQHV &RUS 3HQWLXP70 3HQWLXP3UR70 3HQWLXP,,70 3HQWLXP,,,70 &HOHURQ70DQG *7/70 DUH UHJLVWHUHG WUDGHPDUNV RI ,QWHO &RUS :LQGRZV 70 :LQGRZV 70 :LQGRZV 1770 DQG 3OXJ DQG 3OD\70 DUH UHJLVWHUHG WUDGHPDUNV RI 0LFURVRIW &RUS 3&,70 LV D UHJLVWHUHG WUDGHPDUN RI WKH 3&, 6SHFLDO ,QWHUHVW *URXS $OO WUDGHPDUNV DUH WKH SURSHUWLHV RI WKHLU UHVSHFWLYH RZQHUV 'LVFODLPHU1RWLFH 1R OLFHQVH LV JUDQWHG LPSOLHG RU RWKHUZLVH XQGHU DQ\ SDWHQW RU SDWHQW ULJKWV RI 9,$ 7HFKQRORJLHV 9,$ 7HFKQRORJLHV PDNHV QR ZDUUDQWLHV LPSOLHG RU RWKHUZLVH LQ UHJDUG WR WKLV GRFXPHQW DQG WR WKH SURGXFWV GHVFULEHG LQ WKLV GRFXPHQW 7KH LQIRUPDWLRQ SURYLGHG E\ WKLV GRFXPHQW LV EHOLHYHG WR EH DFFXUDWH DQG UHOLDEOH WR WKH SXEOLFDWLRQ GDWH RI WKLV GRFXPHQW +RZHYHU 9,$ 7HFKQRORJLHV DVVXPHV QR UHVSRQVLELOLW\ IRU DQ\ HUURUV LQ WKLV GRFXPHQW )XUWKHUPRUH 9,$ 7HFKQRORJLHV DVVXPHV QR UHVSRQVLELOLW\ IRU WKH XVH RU PLVXVH RI WKH LQIRUPDWLRQ LQ WKLV GRFXPHQW DQG IRU DQ\ SDWHQW LQIULQJHPHQWV WKDW PD\ DULVH IURP WKH XVH RI WKLV GRFXPHQW 7KH LQIRUPDWLRQ DQG SURGXFW VSHFLILFDWLRQV ZLWKLQ WKLV GRFXPHQW DUH VXEMHFW WR FKDQJH DW DQ\ WLPH ZLWKRXW QRWLFH DQG ZLWKRXW REOLJDWLRQ WR QRWLI\ DQ\ SHUVRQ RI VXFK FKDQJH 2IILFHV 86$ 2IILFH 7DLSHL 2IILFH 0LVVLRQ &RXUW WK )ORRU 1R )UHPRQW &$ &KXQJ&KHQJ 5RDG +VLQ7LHQ 86$ 7DLSHL 7DLZDQ 52& 7HO 7HO )D[ )D[ 2QOLQH6HUYLFHV +RPH 3DJH http://www.via.com.tw ¤RU http://www.viatech.com )73 6HUYHU ftp.via.com.tw %%6 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH VT82C686B REVISION HISTORY Document Release Date Revision Initials Revision 1.6 5/22/00 Initial release based on 82C686A Data Sheet revision 1.6 DH “CD/CE” info and “CD-CG”silicon revision comments removed Added Function 0 Rx8 Revision ID of “2x” for 686B Revision 1.7 6/8/00 Added UDMA100 support to title, feature bullets, and overview DH Removed external APIC support, added IRQ0 input & internal THRM# output Updated pin descriptions: MCCS# (U5/U8 select), GPI3, GPI10, GPI11, GPO6, GPO10, GPO11, GPO21, GPIOC, GPIOD, CHAS, ATEST, THRM, LID Updated bit descriptions F0 Rx8,41[6],59,74[7],75[6],76[4-3],77[4],85[7-6] Updated bit descriptions F1 Rx41[3-0],42,44[4,2],45[4,1-0],46[5-0],4E-4F, 53-50[28,26-24,20-19,12,4-3],54[5,1,0],70[1-0],74-5,78[1-0],7C-D,C0-7 Updated bit descriptions F2/3 Rx43 Updated bit descriptions F4 Rx41[1], 4D[3], 55[2], 57[0], D2[2] Updated bit descriptions ACPI I/O Rx5-4[8], Updated bit descriptions SMBus I/O Rx Updated bit descriptions F5 Rx Revision 1.71 6/9/00 Changed Audio / Game / MIDI ports to dedicated pins (SDD removed) DH Strap description removed from SPKR pin Revision 1.72 6/15/00 Fixed SA pin description; fixed 686B part # in figures 1 & 7 DH Added 1.5V interface note to FERR# and APCD1-0 Removed RTC ports 72-73 and Rx75[6] (and fixed GPO6 description) Fixed Func 1 Rx45[5-4] & default, PM I/O Rx20-25[5], 2A[10] Added Func 2/3/4 Rx6[4]/Rx34, F4Rx68-6F power management capabilities Added Func 4 SMB I/O Rx54, 90-93, D2-D6 and Func 5/6 Rx48[3] Fixed mechanical drawing for proper orientation of marking relative to pin 1 Revision 1.8 8/1/00 Removed Super-I/O “high speed baud rate support” DH Fixed VREF pin direction and voltage, Added F4 Rx55[3] Removed ambient temp spec and added max power dissipation Revision 1.8 August 1, 2000 -i- Revision History 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH VT82C686B TABLE OF CONTENTS 3& &203/,$17 3&,72,6$ %5,'*( .....................................................................................................................................I 7(03(5$785( 92/7$*( $1' )$163((' 021,725,1*..............................................................................................I REVISION HISTORY........................................................................................................................................................................I TABLE OF CONTENTS.................................................................................................................................................................. II LIST OF FIGURES..........................................................................................................................................................................IV LIST OF TABLES ...........................................................................................................................................................................IV OVERVIEW ....................................................................................................................................................................................... 4 PINOUTS............................................................................................................................................................................................ 6 PIN DIAGRAM................................................................................................................................................................................. 6 PIN LISTS........................................................................................................................................................................................ 7 PIN DESCRIPTIONS......................................................................................................................................................................... 9 REGISTERS..................................................................................................................................................................................... 27 REGISTER OVERVIEW ................................................................................................................................................................. 27 REGISTER DESCRIPTIONS............................................................................................................................................................ 39 Legacy I/O Ports ................................................................................................................................................................... 39 Keyboard Controller Registers.............................................................................................................................................................. 40 DMA Controller I/O Registers.............................................................................................................................................................. 42 Interrupt Controller Registers ............................................................................................................................................................... 43 Timer / Counter Registers ..................................................................................................................................................................... 43 CMOS / RTC Registers......................................................................................................................................................................... 44 Super-I/O Configuration Index / Data Registers ............................................................................................................... 45 Super-I/O Configuration Registers ..................................................................................................................................... 45 Super-I/O I/O Ports .............................................................................................................................................................. 48 Floppy Disk Controller Registers.......................................................................................................................................................... 48 Parallel Port Registers........................................................................................................................................................................... 49 Serial Port 1 Registers........................................................................................................................................................................... 50 Serial Port 2 Registers........................................................................................................................................................................... 51 SoundBlaster Pro Port Registers......................................................................................................................................... 52 FM Registers........................................................................................................................................................................................
Load more

Recommended publications
  • Direct Memory Access Components Verification System
    ТРУДЫ МФТИ. — 2012. — Том 4, № 1 Frolov P. V. et al. 1 УДК 004.052.42 P. V. Frolov, V. N. Kutsevol, A. N. Meshkov, N. Yu. Polyakov, M. P. Ryzhov AO «MCST» PAO «INEUM» Direct Memory Access components verification system A method of direct memory access subsystem verification used for Elbrus series micro- processors has been described. A peripheral controller imitator has been developed in order to reduce verification overhead. The model of imitator has been included into the functional machine simulator. A pseudorandom test generator for verification of the direct memory access subsystem has been based on the simulator. Ключевые слова: system verification, functional model, direct memory access, pseu- dorandom test generation. Direct Memory Access components verification system 1. Introduction Modern computer systems require very intensive data exchange between the peripheral de- vices and the random-access memory. In the most cases this exchange is performed by the direct memory access (DMA) subsystem. The increasing demands for the performance of the subsys- tem lead to an increase in its complexity, therefore requiring development of effective approaches to DMA subsystem verification [1,2]. This article is based on a result of a comprehensive project than combined implementation of a there co-designed verification techniques based on the consecutive investigation of theDMA subsystem employing one the three models: 1) a functional model written in C++ that corre- sponds to behaviour of the subsystem in the environment determined by a real computer system configuration, 2) RTL model in Verilog and 3) FPGA-based prototype. This article describesthe first method that enables verifying correctness of the design at an early stage of the verification and eliminate a large quantity of bugs using simple tests.
    [Show full text]
  • VIA RAID Configurations
    VIA RAID configurations The motherboard includes a high performance IDE RAID controller integrated in the VIA VT8237R southbridge chipset. It supports RAID 0, RAID 1 and JBOD with two independent Serial ATA channels. RAID 0 (called Data striping) optimizes two identical hard disk drives to read and write data in parallel, interleaved stacks. Two hard disks perform the same work as a single drive but at a sustained data transfer rate, double that of a single disk alone, thus improving data access and storage. Use of two new identical hard disk drives is required for this setup. RAID 1 (called Data mirroring) copies and maintains an identical image of data from one drive to a second drive. If one drive fails, the disk array management software directs all applications to the surviving drive as it contains a complete copy of the data in the other drive. This RAID configuration provides data protection and increases fault tolerance to the entire system. Use two new drives or use an existing drive and a new drive for this setup. The new drive must be of the same size or larger than the existing drive. JBOD (Spanning) stands for Just a Bunch of Disks and refers to hard disk drives that are not yet configured as a RAID set. This configuration stores the same data redundantly on multiple disks that appear as a single disk on the operating system. Spanning does not deliver any advantage over using separate disks independently and does not provide fault tolerance or other RAID performance benefits. If you use either Windows® XP or Windows® 2000 operating system (OS), copy first the RAID driver from the support CD to a floppy disk before creating RAID configurations.
    [Show full text]
  • Get More out of the Intel Foxhollow Platform
    Get More Out Of the Intel Foxhollow Platform Akber Kazmi, Marketing Director, PLX Technology Introduction As being reported by the mainstream technology media, Intel is leveraging the technology from its latest server-class Nehalem CPU to offer the Lynnfield CPU, targeted for high-end desktop and entry-level servers. This platform is codenamed “Foxhollow “. Intel is expected to launch this new platform sometime in the second half of 2009. This entry-level uni-processor (UP) server platform will feature two to four cores as Intel wants to pack a lot of processing power in all its platforms. The Foxhollow platform is quite different from the previous Desktops and UP servers in that it reduces the solution from three chips to two chips by eliminating the northbridge and replacing the southbridge with a new device called the Platform Controller Hub (or PCH) code named Ibexpeak (5 Series Chipset). As Intel has moved the memory controller and the graphics function into the CPU, there's no need for an MCH (Memory Controller Hub), so Intel has simplified its chipset design to keep costs down in the entry-level and mainstream segments. The PCH chip interfaces with the CPU through Intel’s DMI interconnect. The PCH will support eight PCIe lanes, up to four PCI slots, the GE MAC, display interface controllers, I/O controllers, RAID controllers, SATA controllers, USB 2.0 controllers, etc. Foxhollow Motherboards Foxhollow motherboards are being offered in two configurations, providing either two or three x8 PCIe ports for high performance I/Os. However, motherboard vendors can use an alternate configuration that provides one more PCIe x8 port with no significant burden and instead offers 33% more value than the three port solution and 50% more value than the two port solution.
    [Show full text]
  • Motherboards, Processors, and Memory
    220-1001 COPYRIGHTED MATERIAL c01.indd 03/23/2019 Page 1 Chapter Motherboards, Processors, and Memory THE FOLLOWING COMPTIA A+ 220-1001 OBJECTIVES ARE COVERED IN THIS CHAPTER: ✓ 3.3 Given a scenario, install RAM types. ■ RAM types ■ SODIMM ■ DDR2 ■ DDR3 ■ DDR4 ■ Single channel ■ Dual channel ■ Triple channel ■ Error correcting ■ Parity vs. non-parity ✓ 3.5 Given a scenario, install and configure motherboards, CPUs, and add-on cards. ■ Motherboard form factor ■ ATX ■ mATX ■ ITX ■ mITX ■ Motherboard connectors types ■ PCI ■ PCIe ■ Riser card ■ Socket types c01.indd 03/23/2019 Page 3 ■ SATA ■ IDE ■ Front panel connector ■ Internal USB connector ■ BIOS/UEFI settings ■ Boot options ■ Firmware upgrades ■ Security settings ■ Interface configurations ■ Security ■ Passwords ■ Drive encryption ■ TPM ■ LoJack ■ Secure boot ■ CMOS battery ■ CPU features ■ Single-core ■ Multicore ■ Virtual technology ■ Hyperthreading ■ Speeds ■ Overclocking ■ Integrated GPU ■ Compatibility ■ AMD ■ Intel ■ Cooling mechanism ■ Fans ■ Heat sink ■ Liquid ■ Thermal paste c01.indd 03/23/2019 Page 4 A personal computer (PC) is a computing device made up of many distinct electronic components that all function together in order to accomplish some useful task, such as adding up the numbers in a spreadsheet or helping you to write a letter. Note that this defi nition describes a computer as having many distinct parts that work together. Most PCs today are modular. That is, they have components that can be removed and replaced with another component of the same function but with different specifi cations in order to improve performance. Each component has a specifi c function. Much of the computing industry today is focused on smaller devices, such as laptops, tablets, and smartphones.
    [Show full text]
  • Shuttle XPC Cube Barebone SH370R6V2 – Connectors
    Product Specification Supports 8th/9th generation Intel Core XPC cube Barebone CPUs and up to three UHD displays SH370R6V2 The Shuttle XPC Barebone SH370R6V2 shows how discreet a modern PC can look and at the same time how powerful it can be. Its black- brushed aluminium case has barely a volume of 14 litres, but packs everything you need for a high-performance workstation for example. This includes the power of 8th/9th gen. Intel Core processors, a dual- slot graphics card, fast M.2 NVMe SSD drives, two 3.5’’ hard drives in 8/9th.Gen. 4x DDR4 Dual Triple UHD RAID and up to 128 GB of DDR4 memory, plus a Blu-ray drive. Even Intel Core max. 128GB LAN Display without a dedicated graphics card, up to three UHD displays are supported optionally [3]. Feature Highlights only. purposes illustration for Pictures . Black aluminium chassis (13.6-litre) R6 Chassis Dimensions: 33.2 x 21.5 x 19.0 cm (LWH) Bays: 1x 5.25“, 2x 3.5“ (1x external) Socket LGA 1151v2 supports the 8th and 9th generation Intel Core processors “Coffee Lake” Does not support older LGA 1151 processors. CPU Supports Intel Core i9/i7/i5/i3, Pentium Gold and Celeron Shuttle I.C.E. Heatpipe cooling system Operating Supports Windows 10 and Linux (64-bit) System Optional Optional Intel graphics (depends on CPU [3]) Graphics Supports three digital UHD displays at once Chipset Intel H370 PCH Supports up to 4x 32 GB DDR4-2400/2666 DIMM Memory memory modules (total max. 128 GB) [5] 1x PCIe x16 (v3.0) supports dual-slot graphics Slots cards up to 273 mm length (PCI-E and 1x PCIe x4 (v3.0) M.2) 1x M.2-2280 (SATA / PCIe X4) supports M.2 SSDs 1x M.2-2230 supports WLAN cards SATA 4x SATA 3.0 (6Gb/s) supports RAID and RST Video: HDMI 2.0a and 2x DisplayPort 1.2 Other 4x USB 3.2 Gen 2, 4x USB 3.2 Gen 1, 4x USB 2.0 Connectors 2x Intel LAN.
    [Show full text]
  • J7F3 Mini-ITX Motherboard Series
    Mainboard Diagram J7F3 Mini-ITX Motherboard Series -SiS 741CX Northbridge + SiS 964 Southbridge Chipsets -Support Socket-462 AMD Geode NX processor -Support Front Side Bus 133MHz -Single Channel DDR2 400 Memory DIMM -Support 2 Serial ATA Devices with RAID 0, 1 -Support 2xAD Connector With Expansion Daughter-boards -Ethernet LAN Supported -AC’97 6 Channel Audio CODEC -VIA VT6307S IEEE1394a Controller for J7F3E -17 x 17CM Mini-ITX Form Factor Features and Benefits Support Socket 462 AMD Geode™ NX Processor The AMD Geode™ NX processor family gives product designers a wide range of options in low-power, high-performance processors. Based on Mobile AMD Athlon™ processor technology, AMD NX processors deliver superior computing performance for applications including thin-client, point-of-sale terminals, kiosks, high-end printers, and home media systems. AMD Geode Solutions have received new model numbers to better reflect total performance beyond just megahertz. This presentation of attributes gives designers greater understanding of the capabilities of AMD Geode Solutions. SiS 741CX Northbridge Chipset and SiS964 Southbridge Chipset The SiS741CX chipset can be combined with three different AMD Geode NX processors, including the AMD Geode™ NX 1250@6W processor*, AMD Geode™ NX 1500@6W processor** and AMD Geode™ NX 1750@14W processor***, enabling development of a wider variety of products for different market segments. The SiS741CX chipset supports the AMD Geode NX processor family, DDR266 front side bus, as well as high-speed DDR333 DRAM. Furthermore, the SiS741CX chipset incorporates SiS's revolutionary HyperStreaming™ Technology, which provides multiple divided pipelines for data, allows data to be sent concurrently, and separates data for easier memory retrieval, resulting in a remarkable reduction in latency versus traditional chipsets.
    [Show full text]
  • PCIE-Q870-I2 PICMG 1.3 CPU Card
    PCIE-Q870-i2 PICMG 1.3 CPU Card MODEL: PCIE-Q870-i2 Full-Size PICMG 1.3 CPU Card Supports LGA1150 Intel® Core™ i7/i5/i3, Pentium® or Celeron® CPU, Intel® Q87 Chipset, DDR3, VGA, iDP, Dual Intel® PCIe GbE, SATA 6Gb/s, PCIe Mini, mSATA, RS-232, HD Audio, iRIS-2400 and RoHS User Manual Page i Rev. 1.05 – November 13, 2015 PCIE-Q870-i2 PICMG 1.3 CPU Card Revision Date Version Changes November 13, 2015 1.05 Updated Section 1.6: Technical Specifications Updated Section 2.4: Optional Items Updated Chapter 5: BIOS March 23, 2015 1.04 Updated Section 4.3.3: Flash Descriptor Security Override Jumper November 5, 2014 1.03 Updated PCIe specifications on page 7 June 16, 2014 1.02 Modified LAN pinouts Updated Chapter 2: Packing List March 24, 2014 1.01 Deleted I2C information Updated Section 2.4: Optional Items January 14, 2014 1.00 Initial release Page ii PCIE-Q870-i2 PICMG 1.3 CPU Card Copyright COPYRIGHT NOTICE The information in this document is subject to change without prior notice in order to improve reliability, design and function and does not represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages. This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.
    [Show full text]
  • ISC101.2-1-06-Motherboard.Pdf
    Here you can see an annotated photo of a motherboard. It dates from 2007, so some of its components and connectors are a little outdated, but most of them stay the same in nowadays personal computers. In a modern personal computer motherboard we have: Power connectors to get electrical power from the power supply A socket to install a CPU. In some cases the CPU is directly soldered to the computer Slots to install the system’s main memory A chipset which interfaces the CPU with the main memory and the peripheral buses Non-volatile memory chips containing the system’s firmware needed to load the operating system from the hard disk (known as BIOS for Basic Input/output System) A CMOS memory chip and its battery A clock generator which produces the system’s clock signal to synchronize the various components Slots for expansion cards, that give access to the peripheral bus managed by the chipset An integrated controller for permanent storage devices, typically a SATA bus driver, and its connectors An integrated controller for keyboard and mouse. In legacy computers we will find also a serial and parallel port. All of them have been substituted by USB bus. One or several integrated USB bus controllers to connect external peripherals. The current USB standard is 3.1 Heat sinks and mounting points for fans to dissipate excess heat In modern motherboards a lot of functions that were initially provided with expansion cards are now integrated, so we can find a graphics controller, a sound card and a gigabit ethernet network controller and their connectors.
    [Show full text]
  • User's Manual
    User’s Manual 3301570 3301570 Revision History Title 3301570 Intel Pentium D/Pentium 4 LGA775 CPU board Revision Number Description Date of Issue 1.0 Initial release March 2006 Copyright Notice The information in this document is subject to change without prior notice in order to improve reliability, design and function and does not represent a commitment on the part of the manu- facturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages. This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer. Trademarks IBM PC is a registered trademark of International Business Machines Corporation. INTEL is a registered trademark of INTEL Corporation. AMI is registered trademarks of American Megatrends Inc. Other product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective owners. Page 2 3301570 Table of Contents Revision History ·························································································································· 2 Copyright Notice·························································································································· 2 Trademarks···································································································································
    [Show full text]
  • TECHNICAL MANUAL of Intel 945GC +Intel 82801G Based Mini-ITX M/B
    TECHNICAL MANUAL Of Intel 945GC +Intel 82801G Based Mini-ITX M/B For Intel Atom Processor NO.G03-NC92-F Rev1.0 Release date: Oct., 2008 Trademark: * Specifications and Information contained in this documentation are furnished for information use only, and are subject to change at any time without notice, and should not be construed as a commitment by manufacturer. Environmental Protection Announcement Do not dispose this electronic device into the trash while discarding. To minimize pollution and ensure environment protection of mother earth, please recycle. ii TABLE OF CONTENT USER’S NOTICE .................................................................................................................................. iv MANUAL REVISION INFORMATION ............................................................................................ iv ITEM CHECKLIST.............................................................................................................................. iv CHAPTER 1 INTRODUCTION OF THE MOTHERBOARD 1-1 FEATURE OF MOTHERBOARD..................................................................................... 1 1-2 SPECIFICATION.................................................................................................................. 2 1-3 LAYOUT DIAGRAM ........................................................................................................... 3 CHAPTER 2 JUMPER SETTING, CONNECTORS AND HEADERS 2-1 JUMPER SETTING ..............................................................................................................6
    [Show full text]
  • Intel Motherboard Hardware V1.0
    Intel Motherboard Hardware v1.0 Author: Harry Li, Engineer 1 Scope This document defines the technical specifications for the Intel motherboard used in Open Compute Project servers. 2 Contents 1 Scope ......................................................................................................................................... 2 2 Contents .................................................................................................................................... 2 3 Overview ................................................................................................................................... 5 3.1 License ............................................................................................................................. 5 4 Motherboard Features .............................................................................................................. 6 4.1 Block Diagram .................................................................................................................. 6 4.2 CPU and Memory ............................................................................................................. 6 4.3 Northbridge ..................................................................................................................... 7 4.4 Southbridge/Peripheral Bus Controller ........................................................................... 7 4.5 Network Interfaces .........................................................................................................
    [Show full text]
  • "Design Rules, Volume 2: How Technology Shapes Organizations
    Design Rules, Volume 2: How Technology Shapes Organizations Chapter 17 The Wintel Standards-based Platform Carliss Y. Baldwin Working Paper 20-055 Design Rules, Volume 2: How Technology Shapes Organizations Chapter 17 The Wintel Standards-based Platform Carliss Y. Baldwin Harvard Business School Working Paper 20-055 Copyright © 2019 by Carliss Y. Baldwin Working papers are in draft form. This working paper is distributed for purposes of comment and discussion only. It may not be reproduced without permission of the copyright holder. Copies of working papers are available from the author. Funding for this research was provided in part by Harvard Business School. © Carliss Y. Baldwin Comments welcome. Please do not circulate or quote. Design Rules, Volume 2: How Technology Shapes Organizations Chapter 17 The Wintel Standards-based Platform By Carliss Y. Baldwin Note to Readers: This is a draft of Chapter 17 of Design Rules, Volume 2: How Technology Shapes Organizations. It builds on prior chapters, but I believe it is possible to read this chapter on a stand-alone basis. The chapter may be cited as: Baldwin, C. Y. (2019) “The Wintel Standards-based Platform,” HBS Working Paper (November 2019). I would be most grateful for your comments on any aspect of this chapter! Thank you in advance, Carliss. Abstract The purpose of this chapter is to use the theory of bottlenecks laid out in previous chapters to better understand the dynamics of an open standards-based platform. I describe how the Wintel platform evolved from 1990 through 2000 under joint sponsorship of Intel and Microsoft. I first describe a series of technical bottlenecks that arose in the early 1990s concerning the “bus architecture” of IBM-compatible PCs.
    [Show full text]