9,$ 7HFKQRORJLHV 'HOLYHULQJ 9DOXH 97&% ¦6XSHU6RXWK§6RXWK%ULGJH 36,3& 3&,6XSHU,2,QWHJUDWHG3HULSKHUDO&RQWUROOHU 3&&203/,$173&,72,6$%5,'*( :,7+,17(*5$7('683(5,2 )'&/37&20$1',5 ,17(*5$7('6281'%/$67(5',5(&76281'$&$8',2 8/75$'0$0$67(502'(3&,(,'(&21752//(5 86%&21752//(5.(<%2$5'&21752//(557& ',675,%87(''0$6(5,$/,543/8*$1'3/$< $&3,(1+$1&('32:(50$1$*(0(1760%86$1' 7(03(5$785(92/7$*($1')$163(('021,725,1* 5HYLVLRQ $XJXVW 9,$7(&+12/2*,(6,1& &RS\ULJKW1RWLFH &RS\ULJKW 9,$ 7HFKQRORJLHV ,QFRUSRUDWHG 3ULQWHG LQ WKH 8QLWHG 6WDWHV $// 5,*+76 5(6(59(' 1R SDUW RI WKLV GRFXPHQW PD\ EH UHSURGXFHG WUDQVPLWWHG WUDQVFULEHG VWRUHG LQ D UHWULHYDO V\VWHP RU WUDQVODWHG LQWR DQ\ ODQJXDJH LQ DQ\ IRUP RU E\ DQ\ PHDQV HOHFWURQLF PHFKDQLFDO PDJQHWLF RSWLFDO FKHPLFDO PDQXDO RU RWKHUZLVH ZLWKRXW WKH SULRU ZULWWHQ SHUPLVVLRQ RI 9,$ 7HFKQRORJLHV ,QFRUSRUDWHG 97&$ 97&% DQG 6XSHU 6RXWK PD\ RQO\ EH XVHG WR LGHQWLI\ SURGXFWV RI 9,$ 7HFKQRORJLHV ,QF LD D UHJLVWHUHG WUDGHPDUN RI 9,$ 7HFKQRORJLHV ,QFRUSRUDWHG 3670 LV D UHJLVWHUHG WUDGHPDUN RI ,QWHUQDWLRQDO %XVLQHVV 0DFKLQHV &RUS 3HQWLXP70 3HQWLXP3UR70 3HQWLXP,,70 3HQWLXP,,,70 &HOHURQ70DQG *7/70 DUH UHJLVWHUHG WUDGHPDUNV RI ,QWHO &RUS :LQGRZV 70 :LQGRZV 70 :LQGRZV 1770 DQG 3OXJ DQG 3OD\70 DUH UHJLVWHUHG WUDGHPDUNV RI 0LFURVRIW &RUS 3&,70 LV D UHJLVWHUHG WUDGHPDUN RI WKH 3&, 6SHFLDO ,QWHUHVW *URXS $OO WUDGHPDUNV DUH WKH SURSHUWLHV RI WKHLU UHVSHFWLYH RZQHUV 'LVFODLPHU1RWLFH 1R OLFHQVH LV JUDQWHG LPSOLHG RU RWKHUZLVH XQGHU DQ\ SDWHQW RU SDWHQW ULJKWV RI 9,$ 7HFKQRORJLHV 9,$ 7HFKQRORJLHV PDNHV QR ZDUUDQWLHV LPSOLHG RU RWKHUZLVH LQ UHJDUG WR WKLV GRFXPHQW DQG WR WKH SURGXFWV GHVFULEHG LQ WKLV GRFXPHQW 7KH LQIRUPDWLRQ SURYLGHG E\ WKLV GRFXPHQW LV EHOLHYHG WR EH DFFXUDWH DQG UHOLDEOH WR WKH SXEOLFDWLRQ GDWH RI WKLV GRFXPHQW +RZHYHU 9,$ 7HFKQRORJLHV DVVXPHV QR UHVSRQVLELOLW\ IRU DQ\ HUURUV LQ WKLV GRFXPHQW )XUWKHUPRUH 9,$ 7HFKQRORJLHV DVVXPHV QR UHVSRQVLELOLW\ IRU WKH XVH RU PLVXVH RI WKH LQIRUPDWLRQ LQ WKLV GRFXPHQW DQG IRU DQ\ SDWHQW LQIULQJHPHQWV WKDW PD\ DULVH IURP WKH XVH RI WKLV GRFXPHQW 7KH LQIRUPDWLRQ DQG SURGXFW VSHFLILFDWLRQV ZLWKLQ WKLV GRFXPHQW DUH VXEMHFW WR FKDQJH DW DQ\ WLPH ZLWKRXW QRWLFH DQG ZLWKRXW REOLJDWLRQ WR QRWLI\ DQ\ SHUVRQ RI VXFK FKDQJH 2IILFHV 86$ 2IILFH 7DLSHL 2IILFH 0LVVLRQ &RXUW WK )ORRU 1R )UHPRQW &$ &KXQJ&KHQJ 5RDG +VLQ7LHQ 86$ 7DLSHL 7DLZDQ 52& 7HO 7HO )D[ )D[ 2QOLQH6HUYLFHV +RPH 3DJH http://www.via.com.tw ¤RU http://www.viatech.com )73 6HUYHU ftp.via.com.tw %%6 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH VT82C686B REVISION HISTORY Document Release Date Revision Initials Revision 1.6 5/22/00 Initial release based on 82C686A Data Sheet revision 1.6 DH “CD/CE” info and “CD-CG”silicon revision comments removed Added Function 0 Rx8 Revision ID of “2x” for 686B Revision 1.7 6/8/00 Added UDMA100 support to title, feature bullets, and overview DH Removed external APIC support, added IRQ0 input & internal THRM# output Updated pin descriptions: MCCS# (U5/U8 select), GPI3, GPI10, GPI11, GPO6, GPO10, GPO11, GPO21, GPIOC, GPIOD, CHAS, ATEST, THRM, LID Updated bit descriptions F0 Rx8,41[6],59,74[7],75[6],76[4-3],77[4],85[7-6] Updated bit descriptions F1 Rx41[3-0],42,44[4,2],45[4,1-0],46[5-0],4E-4F, 53-50[28,26-24,20-19,12,4-3],54[5,1,0],70[1-0],74-5,78[1-0],7C-D,C0-7 Updated bit descriptions F2/3 Rx43 Updated bit descriptions F4 Rx41[1], 4D[3], 55[2], 57[0], D2[2] Updated bit descriptions ACPI I/O Rx5-4[8], Updated bit descriptions SMBus I/O Rx Updated bit descriptions F5 Rx Revision 1.71 6/9/00 Changed Audio / Game / MIDI ports to dedicated pins (SDD removed) DH Strap description removed from SPKR pin Revision 1.72 6/15/00 Fixed SA pin description; fixed 686B part # in figures 1 & 7 DH Added 1.5V interface note to FERR# and APCD1-0 Removed RTC ports 72-73 and Rx75[6] (and fixed GPO6 description) Fixed Func 1 Rx45[5-4] & default, PM I/O Rx20-25[5], 2A[10] Added Func 2/3/4 Rx6[4]/Rx34, F4Rx68-6F power management capabilities Added Func 4 SMB I/O Rx54, 90-93, D2-D6 and Func 5/6 Rx48[3] Fixed mechanical drawing for proper orientation of marking relative to pin 1 Revision 1.8 8/1/00 Removed Super-I/O “high speed baud rate support” DH Fixed VREF pin direction and voltage, Added F4 Rx55[3] Removed ambient temp spec and added max power dissipation Revision 1.8 August 1, 2000 -i- Revision History 7HFKQRORJLHV ,QF 'HOLYHULQJ 9DOXH VT82C686B TABLE OF CONTENTS 3& &203/,$17 3&,72,6$ %5,'*( .....................................................................................................................................I 7(03(5$785( 92/7$*( $1' )$163((' 021,725,1*..............................................................................................I REVISION HISTORY........................................................................................................................................................................I TABLE OF CONTENTS.................................................................................................................................................................. II LIST OF FIGURES..........................................................................................................................................................................IV LIST OF TABLES ...........................................................................................................................................................................IV OVERVIEW ....................................................................................................................................................................................... 4 PINOUTS............................................................................................................................................................................................ 6 PIN DIAGRAM................................................................................................................................................................................. 6 PIN LISTS........................................................................................................................................................................................ 7 PIN DESCRIPTIONS......................................................................................................................................................................... 9 REGISTERS..................................................................................................................................................................................... 27 REGISTER OVERVIEW ................................................................................................................................................................. 27 REGISTER DESCRIPTIONS............................................................................................................................................................ 39 Legacy I/O Ports ................................................................................................................................................................... 39 Keyboard Controller Registers.............................................................................................................................................................. 40 DMA Controller I/O Registers.............................................................................................................................................................. 42 Interrupt Controller Registers ............................................................................................................................................................... 43 Timer / Counter Registers ..................................................................................................................................................................... 43 CMOS / RTC Registers......................................................................................................................................................................... 44 Super-I/O Configuration Index / Data Registers ............................................................................................................... 45 Super-I/O Configuration Registers ..................................................................................................................................... 45 Super-I/O I/O Ports .............................................................................................................................................................. 48 Floppy Disk Controller Registers.......................................................................................................................................................... 48 Parallel Port Registers........................................................................................................................................................................... 49 Serial Port 1 Registers........................................................................................................................................................................... 50 Serial Port 2 Registers........................................................................................................................................................................... 51 SoundBlaster Pro Port Registers......................................................................................................................................... 52 FM Registers........................................................................................................................................................................................
Details
-
File Typepdf
-
Upload Time-
-
Content LanguagesEnglish
-
Upload UserAnonymous/Not logged-in
-
File Pages130 Page
-
File Size-