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Benefits of the AMD Opteron Processor for LS-DYNA

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Benefits of the AMD Opteron Processor for LS-DYNA th 4 European LS -DYNA Users Conference MPP / Linux Cluster / Hardware I Benefits of the AMD Opteron™ Processor for LS-DYNA Dawn Rintala Sr. Developer Engineer Computation Products Group Advanced Micro Devices, Inc. Demands on System from Explicit/Implicit Analysis •Explicit – Quick Communication between processors – Good FPU •Implicit – Low memory latency – High memory bandwidth AMDCopyright Opteron™ delivers: by DYNAmore 1.Breakthrough 64-bit performance 2.Complete 32-bit compatibility 3.Industry leading price/performance 22 May 2003 LS-DYNA Users Conference 2003 2 K – I - 43 th MPP / Linux Cluster / Hardware I 4 European LS -DYNA Users Conference Benefits of AMD Opteron™ for LS-DYNA •Performance – Raw Performance – Price Performance •Scalability – On-Chip Cache – HyperTransport™ •Low Memory Latency •Memory Addressability 4P, 32GB AMD Opteron™ Processor-based System 22 May 2003 LS-DYNA Users Conference 2003 3 AMD Opteron™ SOC Architecture Overview AMD Opteron™ Architecture •First AMD64 processor •Aggressive out-of-order, 9-issue DDR Memory superscalar processor Controller L1 •Integrated DDR memory controller Instruct. AMD Opteron™ Cache Processor L2 •Leading performance in integer, Core L1 Cache floating point and multimedia Data Cache – AMD64, x87, MMX™, 3DNow!™, SSE, SSE2 HyperTransport™ technology •GluelessCopyright multiprocessing throughby DYNAmore HyperTransport™ •Expandable IO through HyperTransport 22 May 2003 LS-DYNA Users Conference 2003 4 K – I - 44 th 4 European LS -DYNA Users Conference MPP / Linux Cluster / Hardware I AMD Opteron™ Processor Technology Overview • Processor Core Overview DRAM – Support for AMD’s 64-bit technology – 12-stage int, 17-stage fp pipelines – Enhanced TLB structures – TLB flush filter – Enhanced branch prediction MCT – 1MB L2 cache CPU SRQ – ECC protection • Memory Controller Overview – Dual-channel DDR memory XBAR – PC2700, PC2100, or PC1600 DDR memory support – Registered or Unbuffered DIMMs – ECC and Chip Kill HT HT – High bandwidth (up to 6.4GB/s) HT • HyperTransport™ Technology Overview – One, two, or three links – 2, 4, 8, 16, or 32-bits full duplex – Up to 6.4 GB/s bandwidth per link – 19.2 GB/s aggregate external bandwidth HT = HyperTransport™ technology 22 May 2003 LS-DYNA Users Conference 2003 5 AMD Opteron™ processor-based 4P Server AMDAMD Opteron Opteron™™ AMDAMD Opteron Opteron 200-333MHz 940 mPGA 940 mPGA 200-333MHz 144-Bit Reg DDR 940 mPGA 940 mPGA 144-Bit Reg DDR 16x16 coherent HyperTransportTM @ 1600MT/s AMDAMD Opteron Opteron AMDAMD Opteron Opteron 200-333MHz 200-333MHz 940940 mPGA mPGA 940 mPGA 144-Bit Reg DDR 940 mPGA 144-Bit Reg DDR 16x16 HyperTransport@ 1600MT/s 64-bits @ 64-bits @ 8x8 HyperTransport @ 400MT/s 133Mhz AMDAMD-8131-8131ää 133Mhz PCI-X PCI-X PCI-X PCI-X Legacy PCI Hot Plug Hot Plug PCI VGA Graphics Copyright8x8 HyperTransport @ 1600MT/s by DYNAmoreAMD-8111ä AMD-8111ä Southbridge FLASH Southbridge LPC 64-bits @ 64-bits @ 1000 BaseT SIO Zircon BMC 66Mhz AMD-8131 66Mhz Gbit Ethernet AMD-8131 USB PCI-X U320 AC97 100 BaseT PCI-X PCI-X PCI-X UDMA100 SCSI 10/100 Ethernet Management LAN 1000 BaseT Gbit Ethernet 22 May 2003 LS-DYNA Users Conference 2003 6 K – I - 45 th MPP / Linux Cluster / Hardware I 4 European LS -DYNA Users Conference The Rewards of Good Plumbing •High Bandwidth – 2P system is designed to achieve 7 GB/s aggregate memory Read bandwidth – 4P system is designed to achieve 10 GB/s aggregate memory Read bandwidth •Low Latency – Average 2P unloaded latency (page hit) is designed to be < 120 ns – Average 4P unloaded latency (page hit) is designed to be < 140 ns – Latency under load increases slowly due to excess Interconnect Bandwidth – Latency shrinks quickly with increasing CPU clock speed and HyperTransport™ link speed 22 May 2003 LS-DYNA Users Conference 2003 7 Integrated Memory Controller Latency (Local Memory Access, Registered Memory, CAS2) Read Latency Accessing Local Memory, PC2100 200 180 AMD Athlon™ latency = 180ns 160 140 120 PageHit 0 Hop PageMiss 0 Hop 100 Prb Miss 1 Hop (2 node case) Prb Miss 2 Hop (4 node case) Latency (ns) 80 Copyright60 by DYNAmore 40 20 0 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000 3200 3400 3600 3800 4000 Frequency (MHz) 22 May 2003 LS-DYNA Users Conference 2003 8 K – I - 46 th 4 European LS -DYNA Users Conference MPP / Linux Cluster / Hardware I Floating-Point Performance SPECfp®_rate2000 Performance SPECfp®_rate2000 Performance and (Peak, 4P) Scalability (Peak, 2-4P scaling) Itanium 2 49.3 Itanium 2 1.0GHz 49.3 244% 1.0GHz (4P) 161% Itanium 2 30.7 100% AMD Opteron™ 844 49.2 244% 1.0GHz (2P) AMD Opteron™ 49.2 844 (4P) 184% AMD Opteron 842 45 223% AMD Opteron 26.7 100% 244 (2P) AMD Opteron 840 40.7 201% Xeon MP 20.2 2.0GHz (4P) 146% Xeon MP 13.8 Xeon 2.0GHz 20.2 100% 2.0GHz (2P) 100% www.amd.com/opteronperformance © 2003 Advanced Micro Devices. AMD, the AMD Arrow Logo, AMD Opteron and any combinations thereof are trademarks of Advanced Micro Devices. Microsoft and Windows are trademarks of Microsoft Corporation. SPEC and the benchmark named SPECfp are registered trademarks of the Standard Performance Evaluation Corporation. Competitive benchmark results stated above reflect results published on 22 Maywww.spec.org 2003 as of Apr 14, 2003. SPEC benchmark scores for AMD Opteron processorLS-DYNA-based systems Users are Conference under submission 2003 to the SPEC organization. For complete configuration information visit www.spec.org9. The Result AMD Opteron™ delivers: 1. Breakthrough 64-bit performance 2. Complete 32-bit compatibility 3. Industry leading price/performance Copyright by DYNAmore 22 May 2003 LS-DYNA Users Conference 2003 10 K – I - 47 th MPP / Linux Cluster / Hardware I 4 European LS -DYNA Users Conference Cautionary Statement Trademark Attribution •This presentation contains forward-looking statements, which are made pursuant to the safe harbor provisions of the U.S. Private Securities Litigation Reform Act of 1995. Forward-looking statements are generally preceded by words such as “expects,” “plans,” “believes,” “anticipates,” or “intends.” Investors are cautioned that all forward-looking statements in this presentation involve risks and uncertainties that could cause actual results to differ materially from current expectations. Forward-looking statements in this presentation involve the risks that AMD OpteronTM processors will not perform pursuant to their design specifications, will not achieve customer and/or market acceptance, and that third-party solution vendors will not provide the infrastructure necessary to support these products. We urge investors to review in detail the risks and uncertainties in the company’s U.S. Securities and Exchange Commission filings, including the most recently filed Form 10-K. •AMD, the AMD Arrow logo, AMD Opteron, AMD Athlon, and combinations thereof, AMD-8111 and AMD-8131 are trademarks of Advanced Micro Devices, Inc. HyperTransport is a licensed trademark of the HyperTransport Technology Consortium. Other product and company names used in this publication are for identification purposes only and may be trademarks of their respective companies. 22 May 2003 LS-DYNA Users Conference 2003 11 Copyright by DYNAmore K – I - 48.
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