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Hypertransport Extending Technology Leadership HyperTransport Extending Technology Leadership International HyperTransport Symposium 2009 February 11, 2009 Mario Cavalli General Manager HyperTransport Technology Consortium Copyright HyperTransport Consortium 2009 HyperTransport Extending Technology Leadership HyperTransport and Consortium Snapshot Industry Status and Trends HyperTransport Leadership Role February 11, 2009 Mario Cavalli General Manager HyperTransport Technology Consortium Copyright HyperTransport Consortium 2009 HyperTransport Snapshot Low Latency, High Bandwidth, High Efficiency Point-to-Point Interconnect Leadership CPU-to-I/O CPU-to-CPU CPU-to-Coprocessor Copyright HyperTransport Consortium 2009 Adopted by Industry Leaders in Widest Range of Applications than Any Other Interconnect Technology Copyright HyperTransport Consortium 2009 Snapshot Formed 2001 Controls, Licenses, Promotes HyperTransport as Royalty-Free Open Standard World Technology Leaders among Commercial and Academic Members Newly Elected President Mike Uhler VP Accelerated Computing Advanced Micro Devices Copyright HyperTransport Consortium 2009 Industry Status and Trends Copyright HyperTransport Consortium 2009 Global Economic Downturn Tough State of Affairs for All Industries Consumer Markets Crippled with Long-Term to Recovery Commercial Markets Strongly Impacted Copyright HyperTransport Consortium 2009 Consequent Business Focus Cost Effectiveness No Redundancy Frugality Copyright HyperTransport Consortium 2009 Downturn Breeds Opportunities Reinforced Need for More Optimized, Cost-Effective Computing Infrastructure Good for HPC Sector Copyright HyperTransport Consortium 2009 Creating Demand for New Technology Delivering: More Value for Same Power and Cost Same Value for Less Power and Cost Best Investment Preservation Minimized Total Cost of Ownership Through Better: Performance and Power Efficiency Resource Flexibility and Adaptability System Virtualization Æ Consolidation Copyright HyperTransport Consortium 2009 Producing New Computing Trends Cloud Computing Æ Hosted Software, Software as a Service (SaaS) Replace Costly In-House Infrastructure and Management Resources Infrastructure Centralization Demands Efficient Data Centers, Server Farms Copyright HyperTransport Consortium 2009 Producing New Computing Trends (cont.) Netbook over Notebook / Desktop New? No Innovative? No Same for Less? No Less for Much Less? Yes! Good Enough if Budget Tight? Yes! Right-Time, Right-Place Products? Right! Copyright HyperTransport Consortium 2009 HyperTransport Leadership Role Copyright HyperTransport Consortium 2009 Answers Market Trend Expectations With Core Values Leading Performance Full Scalability Power Efficiency Low Design Cost Market-Proven Solidity Vast Product Ecosystem Copyright HyperTransport Consortium 2009 Continued Technology Progression With Expanding Market Presence HT 1.0 HT 1.1 2001 2002 HT 2.0 17.7M HT-Based Systems Shipped (Note 1) HT 3.1 2003 2004 HTX HT 3.0 HNC 1.0 HTX3 (Note 3) 2005 2006 2008 2009 62.7M HT-Based Systems Shipped Note 1: by end of 2003 – Source InStat (Note 2) Note 2: by end of 2008 – Source InStat Note 3: High Node Count HT Specification 1.0 - Accessible/Useable by HTC Promoter and Contributor Members Only Copyright HyperTransport Consortium 2009 HT 3.1 Specification Keeps HT Ahead of Industry Requirements Feature Current Use HT 3.1 Max Max Headroom Clock Rate 2.0 GHz 3.2 GHz 60% HT 3.1 Bandwidth 16 GB/s 51.2 GB/s 220% 51.2 GB/s (32-Bit) Link Width 16-bit 32-bit 100% 25.6 GB/s (16-Bit) Solidifies HT Leadership HT 3.0 Reinforces HT ROI 41.6 GB/s (32-Bit) 20.8 GB/s (16-Bit) The Only 32-Bit-Capable Processor Interconnect 2.6 GHz 2.8 GHz 3.0 GHz 3.2 GHz Clock In Industry Copyright HyperTransport Consortium 2009 HTX3TM Specification 3x Bandwidth of HTXTM Connector Standard • HT3.0 Performance • HT3.0 Link Splitting Support • More Power Mgmt. Features • 100% Backward Compatibility For Highest Performance Subsystems Copyright HyperTransport Consortium 2009 High Node Count HT Specification 1.0 Enables Scalable HPC Systems and Clusters with Low Latency Non-Coherent Shared Memory Architecture Server 2 Server 1 Server n Mx+3 M8 M4 Mx+2 M7 M3 Mx+1 M6 M2 Mx M5 M1 Direct Network / Switched Network Copyright HyperTransport Consortium 2009 High Node Count HT Specification 1.0 (cont.) Answers Ever Compounding On-Chip + In-System Addressing Challenge Exponential Exponential Number of CPU Number of Cores Clusters/Subclusters You are Here Copyright HyperTransport Consortium 2009 (cont.) High Node Count Specification 1.0 Supports Global Sharing of Localized Data Storage Server Z Server Y Server X Network Copyright HyperTransport Consortium 2009 High Node Count Specification 1.0 (cont.) Supports Global Sharing of Localized Data Storage Server Z Server Y Server X High-Density DRAM Flash Memory Subsystem N etwork Especially High-Density DRAM Copyright HyperTransport Consortium 2009 High Node Count Specification 1.0 (cont.) Supports Global Sharing of Localized Data Storage Server Z Server Y Server X High-Density DRAM Flash Memory Subsystem N etwork Especially High-Density DRAM and Low Power Flash-Based Memory Subsystems Copyright HyperTransport Consortium 2009 High Node Count Specification 1.0 (cont.) Best System and Performance Scalability Minimized Power Consumption Optimized Total Cost of Ownership Copyright HyperTransport Consortium 2009 Mature Stability, Mission-Critical Reliability Field-Proven Dependability for Demanding Markets 63 Million HT-Powered Products by end of 2008 2007 2007 Capture Market Yr/Yr Growth 8% Defense Applications 17% 32% Top500 Supercomputers 28% 11% Core Routers 1.2% 22% Edge Routers 34% 15% SAN 11% 23% Servers 38% Source: InStat Copyright HyperTransport Consortium 2009 Ever Expanding Product Ecosystem • From HT IP to HT Software • 12 HT-Based Processor Brands • Fosters Technology Strength • Widespread Market Utilization X86 Computing Graphics Security Packet Media Comm Acceleration System Virtualization Copyright HyperTransport Consortium 2009 Expanding Product Ecosystem (cont.) New Godson Multi-Core Server-Class CPU • Petascale Performance Target by 2010 • Backed by China’s Government • MIPS-Based with 200+ More Instructions for x86 Translation and Acceleration • 16 GFLOPS at 1GHz and 10W of Power • Earlier versions (non-HT), produced by ST Institute of Computing Technology Microelectronics and sold to 40 companies Chinese Academy of Sciences in set-top boxes, laptops, etc. • @200 developers working on Godson HW, @100 on SW and Compilers Copyright HyperTransport Consortium 2009 HyperTransport Book Covers all HT Link and HTX Specification 700 Pages of Must-Have Tutorial Co-Authored by HTC’s Brian Holden Available Online from MindShare www.mindhsare.com in Paper and eBook Formats Copyright HyperTransport Consortium 2009 Thank You! Mario Cavalli General Manager HyperTransport Technology Consortium Copyright HyperTransport Consortium 2009 Corollary Information Not Part of Live Presentation Copyright HyperTransport Consortium 2009 HyperTransport Everywhere! Also in PowerPC-Based and Intel-Based Products Copyright HyperTransport Consortium 2009 Godson Server-Class CPU Institute of Computing Technology - Chinese Academy of Sciences 4-Core Reconfigurable Architecture 65-nm Technology Directory-Based Coherence 8 Config. Address Protocol Safeguards Windows of Each Master Port Allow Cache Data Pages Migration Across L2 and Memory Nodes Organized in Mesh ncHT1.0 ncHT1.0 8x8 AXI Switch PCIe PCIe Shared L2 Configurable DMA Engine Supports As Internal RAM, DMA 2 Links for Each Node’s Pre-Fetch and Matrix To Internal RAM Directly 4 Connection Points (Stream Processor) Copyright HyperTransport Consortium 2009 Godson Server-Class CPU (cont.) Institute of Computing Technology - Chinese Academy of Sciences Godson Versions 8-Core Multi-Chip 20W Version Possible in 2009 Copyright HyperTransport Consortium 2009 Godson Server-Class CPU (cont.) Institute of Computing Technology - Chinese Academy of Sciences Godson Cores Profile Copyright HyperTransport Consortium 2009 HTXTM Spotlight How and Why HyperTransport HTX Proves Best Choice for Compute-Intensive Applications Copyright HyperTransport Consortium 2009 HTXTM Values Snapshot Enables • HPC Products Demanding Performance Beyond the Reach of PCI-Class Interconnects • Integration of System Functionality Too New/Complex/Costly for MB Integration Empowers • HPC Solution Providers with a Competitive Edge – No Risks of Premature MB Integration – Shortest Time-to-Market – One MB Fits Multiple Markets/Applications – Up-Sell Factor Copyright HyperTransport Consortium 2009 HTXTM Applications Compute Intensive • High Bandwidth + Low Latency • Multi-Processing, Co-Processing Target Markets • Database Analytics • High Traffic Web Services • Stock Trading Acceleration • Server Clustering and SMP • Streaming Media Servers • Financial Modeling Copyright HyperTransport Consortium 2009 Expanding HTXTM Product Ecosystem Server / MB Data Analysys Coprocessor HTXTM Content-Aware Routing Processor High-Perf Server Clustering Controller Content/Security Processor Content/Security Processor 10GE NIC Ref Design Universal HTX/HTX3 Board Ref Design FPGA Ref Design Board More Innovative HTXTM Systems and Subsystems in the Pipeline Copyright HyperTransport Consortium 2009 TM Systems NewHTX ProLiant DL165-G5 PCIe PCIe PCIe PCIe PCIe PCIe PCIe x4 x4 x16 x4 x4 x4 x8 HTX HTX x16 x16 ProLiant DL785-G5 Blank 9 Blank 8 7 6 5 4 3 2 1 Slot Copyright HyperTransport Consortium 2009 New HTXTM Subsystems NumaChip Technology Cache-Coherent Shared Memory Processor
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