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Altera Product Overview AlteraAltera ProductProduct OverviewOverview TimTim ColleranColleran ViceVice President,President, ProductProduct MarketingMarketing © 2001 AlteraAltera ProductProduct OverviewOverview High Density + Programmable High-Speed Embedded High Performance Low Cost High Bandwidth ASSP with CDR Product Term Processor All Copper 2.5 V I/O Phase-Locked Loop CAM Multiplier Termination FIFO Resistors CDR Embedded Software Processors © 2001 1 AlteraAltera I/OI/O AchievementsAchievements 1st 11stst 1.25-Gbps LVDS + CDR 1st 1-Gbps Support 1st LVDS Support 1.8-V I/O 840-Mbps Product-Term LVDS Family, Support SSTL-2/-3 1st PLL 1996 1999 2000 2001 2001 FLEXFLEX®® 10K10K APEX™ 20KE MAX® 7000B APEX II Mercury™Mercury™ © 2001 TypicalTypical CommunicationsCommunications DatapathDatapath Example: OC-192 Data Path DDR, ZBT & QDR Interfacing SRAMs & SDRAMs Dedicated Timing Circuitry Multiple I/O Registers 10-Gbps CDR POS-PHY UTOPIA Dedicated CDR Circuitry 622-MHz LVDS Flexbus CSIX CDR Switch Packet PMD Fabric Transceiver Framer Processing HSTL Buffers Half Rate Clock Half Rate Clock 311-MHz Clock 311-MHz Clock 17-32 Channels RapidIO Host HyperTransport Processor 311-MHz Half Rate Clock HyperTransport Buffers © 2001 2 TheThe I/OI/O AllAll StarsStars APEX II: Complete I/O Flexibility − Maximum Bandwidth in a PLD − Broadest Protocol Support in a PLD Mercury: The Programmable ASSP − Clock Data Recovery / SERDES − Highest Performance PLD MAX 7000B − I/O Super Glue Logic Intellectual Property − A Key Ingredient for Success © 2001 © 2001 3 APEXAPEX IIII I/OI/O SupportSupport High-Speed I/O Capabilities − 1-Gbps True-LVDS™ Solution, LVPECL, PCML & HyperTransport − 624-Mbps, Flexible-LVDS™ Solution, LVPECL & HyperTransport − RapidIO, UTOPIA IV, Flexbus CSIX, POS-PHY Level 4 − 250-MHz HSTL Internal & External Maximized Chip-to-Chip Memory Options Performance − 4-Kbit Memory Blocks with − Clock-Data Synchronization Bidirectional Read / Write − 1-Gbps LVDS & LVPECL Ports − Up to 124 High-Speed Channels − External Interface Support − Programmable Output Drive for ZBT, DDR & QDR RAMs © 2001 APEXAPEX IIII ProductProduct OfferingsOfferings Device Logic RAM LVDS Channels (Input/Output) Max. Elements Bits 1-Gbps 624-Mbps User True-LVDS* Flexible-LVDS** I/O Pins EP2A15 16,640 416K 36 / 36 56 / 56 492 EP2A25 24,320 608K 36 / 36 56 / 56 607 EP2A40 38,400 640K 36 / 36 88 / 88 735 EP2A70 67,200 1,120K 36 / 36 88 / 88 1,060 EP2A90 89,280 1,488K 36 / 36 88 / 88 1,140 * True-LVDS Channels Also Support LVPECL, PCML & HyperTransport I/O ** Flexible-LVDS Channels Also Support LVPECL Inputs & HyperTransport I/O (3$Ã6DPSOHVÃ6KLSSLQJÄ © 2001 4 APEXAPEX IIII True-LVDSTrue-LVDS CircuitryCircuitry Dedicated True-LVDS Circuitry Enables 1-Gbps Differential Signaling 36 Input & Output Channels per Device LVDS, LVPECL, PCML & HyperTransport Features 2 Improved & Independent Clock Domains (1-Gbps, x8 Example) 1-Gbps 1-Gbps 1-Bit Data 1-Bit Data System Logic Serializer (x8) Deserializer (x8) 1-GHz 125-MHz 1-GHz Dedicated LVDS 100-MHz Clock Clock Clock 100-MHz Circuitry Clock Clock LVDS LVDS General-Purpose PLL (x10) PLL (x10) Programmable Logic © 2001 APEXAPEX IIII Clock-DataClock-Data SynchronizationSynchronization CDS Circuitry Synchronizes True-LVDS Channels to System Clock − Performed Independently on All Channels Source-Synchronous Transfer Chip-to-Chip Transfer with CDS Limited to 2 Devices Unlimited Chip-to-Chip Communication Clock Must Be Forwarded with Data $3(;Ã.( $3(;Ã.( Clock Clock © 2001 5 APEXAPEX IIII Phase-LockedPhase-Locked LoopsLoops (8 Global Clocks) PLL Applications G3 G2 PLL G7 G6 PLL True-LVDS Double Data Rate I/O 8 Flexible-LVDS G1 G0 Internal Clock Management PLL G5 G4 PLL Frequency Synthesis TxPLL G2 G1 RxPLL External System Clock Management Physical Layer I/O Standards TxPLL G4 G3 RxPLL General-Purpose PLL Dedicated LVDS PLL © 2001 I/OI/O StandardsStandards SupportedSupported I/O Standard Performance Type LVPECL 1 Gbps Differential PCML 1 Gbps Differential HyperTransport 1 Gbps Differential HSTL Class I, II 250 MHz Single-Ended SSTL-2 Class I, II 332 Mbps Single-Ended SSTL-3 Class I, II 167 MHz Single-Ended PCI-X 133 MHz Single-Ended © 2001 6 CompleteComplete MemoryMemory SolutionSolution External Memory Interfacing Memory Type Performance Internal RAM Blocks ZBT SRAM 200 MHz 4 Kbits per Block SDR SDRAMs 200 MHz True Dual-Port RAM Mode DDR SRAMs 334 Mbps Packing Mode QDR SRAMs 668 Mbps Mixed Port Widths DDR SDRAMs 334 Mbps QDR DDR ESBESB ZBT © 2001 UnparalleledUnparalleled TotalTotal DeviceDevice BandwidthBandwidth UpUp toto 366366 GbpsGbps 36 Input 36 Output 1-Gbps True-LVDS Channels Channels 88 Input 88 Output 624-Mbps Flexible-LVDS Channels Channels 270+ Input EP2A70 270+ Output 334-Mbps General-Purpose I/O Channels Channels Compare Device Bandwidths Previously Today Device EP20K1500E EP2A70 True-LVDS 27 Gbps 72 Gbps Flexible-LVDS - 110 Gbps General-Purpose + 110 Gbps + 184 Gbps Totals 137 Gbps 366 Gbps © 2001 7 © 2001 TheThe MercuryMercury SolutionSolution = 1.25-Gbit CDR + PLD CDR Comma Custom Detect Logic Receive 125 Mbps Bandwidth- 1.25 Gbps Data Dedicated Optimized Circuitry Programmable Logic 125 Mbps 1.25 Gbps Data Encode/ CDR DSP Transmit Decode © 2001 8 MercuryMercury ProductProduct OfferingsOfferings The Programmable ASSP Device CDR Logic RAM Max. Channels Elements Bits User I/O EP1M120 8 4,800 48 K 303 EP1M350 18 14,400 112 K 486 (30Ã6DPSOHVÃ6KLSSLQJÄ © 2001 MercuryMercury Clock-DataClock-Data RecoveryRecovery Single-Ended I/O Standards Single-Ended Standards Hit Noise Limitations at ~250 MHz 100 MHz 250 MHz Differential I/O Standards (LVDS) Clock Skew Overwhelms Differential I/O Standards at ~ 1 Gbps 100 Mbps 250 Mbps 500 Mbps 750 Mbps 1 Gbps Clock Data Recovery (CDR) CDR Eliminates Barriers CLOCK CLOCK CLOCK CLOCK CLOCK CLOCK CLOCK CLOCK CLOCK CLOCK CLOCKCLOCKCLOCK 1.25 Gbps & Beyond 100 Mbps 250 Mbps 500 Mbps 750 Mbps 1 Gbps © 2001 9 MercuryMercury 1M1201M120 Vs.Vs. APEXAPEX 20KC20KC Mercury on a 0.15-um Copper Process Is the World’s Fastest PLD 300.0 46%46% PerformancePerformance 250.0 AdvantageAdvantage APEX 20KC 200.0 150.0 100.0 Performance (MHz)Performance 50.0 0.0 Quartus II v1.1 B111, Synplify v6.2R83 EP1M120–5 vs. EP20K100C-7/EP20K200C-7200C–7 Design © 2001 High-SpeedHigh-Speed SerialSerial BackplanesBackplanes High-End Systems Exceed PCI Capabilities CDR Enables Multi-Crystal Operation CDR Enables High-Speed Backplanes Standardized Backplane Common Protocols Mercury Device & Implementations Serial Proprietary Backplane Differentiation & Connection Value Proposition for System Architects Multiple Line Cards with Independent Clocks © 2001 10 InterfacesInterfaces SupportedSupported byby Altera Altera Interface Bandwidth Number Needed I/O I/O Mercury APEX II Standard (Gbps) Of Performance Standard Channels (Mbps) POS-PHY Level 4 10G 16 + 1* 622 LVDS 9 9 UTOPIA IV 10G 32 416** LVDS 9 9 RapidIO 16G 16 + 1* 1,000 LVDS 9 9 Hyper- 16G 16 + 1* 1,000 Hyper- 9 Transport Transport 1G Ethernet 1.25G Any 1,250 LVDS 9 + CDR Fibre Channel 1G Any 1,062 LVPECL 9 + CDR OC-12/SDH-4 0.622G Any 622 LVDS 9 SONET + CDR CSIX 32G 128 250 MHz HSTL 9 9 * Control Signal, ** Overhead Included © 2001 © 2001 11 MAX 7000B: I/O Standards Two I/O Blocks Can Be Configured Separately Programmable I/O Blocks • GTL+ • SSTL-3 Class I & II • SSTL-2 Class I & II • LVCMOS • LVTTL Individual Power Buses ,QFUHDVHGÃ,2Ã3HUIRUPDQFH © 2001 UniqueUnique AdvancedAdvanced I/OI/O SupportSupport I/O Standard MAX 7000A MAX 7000B (3.3 V) (2.5 V) GTL+ 9 SSTL-2 Class I & II 9 SSTL-3 Class I & II 9 LVTTL 9 9 LVCMOS 9 9 5.0 V 9 3.3 V 9 9 2.5 V 9 9 1.8 V 9 64-Bit, 66-MHz PCI 9 © 2001 12 ApplicationsApplications Processor GTL+ SSTL – 2/-3 3.3 –V PCI High-Bandwidth SDRAM MAX 7000B LVTTL Communications 2.5 V I/O Standard Applications GTL/GTL+ High-Speed Processor Interface High-Speed Backplane Driver 125 MHz SSTL-3 High-Speed Memory Interfacing to SDRAMs 150 MHz © 2001 © 2001 13 IncreasingIncreasing InterfacesInterfaces EthernetEthernet POS-PHYPOS-PHY AMBAAMBA OCPOCP CoreCore Infiniband UTOPIA VCIVCI Infiniband UTOPIA ConnectConnect CoreCore PCIPCI FlexbusFlexbus FrameFrame USBUSB IPbus DDR/DDR/ QDRQDR IPbus FISPbusFISPbus Board-to-Board Chip-to-Chip On-Chip © 2001 BridgingBridging InterfacesInterfaces withwith AlteraAltera Multiple Interfaces on Board Need for Altera to Bridge Different Interfaces Example: POS-PHY Level 3 to PCI Bridge ASSP: ASIC: Proprietary Different Interface Interface X X Y Y Y Y Interface Interface Interface Interface Interface Interface PMC SierraPOS-PHY 3 PCI ASIC with Interface Interface PCI Interface © 2001 14 AtlanticAtlantic InterfaceInterface Atlantic Is an on-Chip PLD Packet-Based Interface − Full-Duplex, Synchronous Bus Protocol − High Performance − Simple to Implement − Scalable Specification Available Today Supported by AMPPSM Partners Atlantic POS-PHY UTOPIA Interface © 2001 High-SpeedHigh-Speed InterfaceInterface MegafunctionsMegafunctions Atlantic™ Interface POS-PHYPOS-PHY CSIX-L1CSIX-L1 LevelLevel 2,2, 33 && 44 FlexbusFlexbus LevelLevel 33 && 44 IX-BusIX-Bus UTOPIAUTOPIA LevelLevel 22 && 33 RapidIORapidIO HyperTransportHyperTransport © 2001 15 LookingLooking ForwardForward © 2001 High-SpeedHigh-Speed I/OI/O RoadmapRoadmap 10.0 )XWXUHÃ,,, CDR 10 Gbps )XWXUHÃ,, 6.4 CDR 6.4 Gbps )XWXUH CDR 3.2 3.125 Gbps Data Rate (Gbps) CDR 1.25 Gbps 1.25 ,, .( True-LVDS True-LVDS 1 Gbps 840 Mbps 2000 2001 2002 2003 2004 © 2001 16 ProvenProven High-SpeedHigh-Speed I/OI/O DesignDesign ExpertiseExpertise 2.5-Gbps CDR Test Chip 3.125-Gbps Chip in Joint Development
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