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SAS Storage Architecture: Serial Attached SCSI, 2005, Mike Jackson, 0977087808, 9780977087808, Mindshare Press, 2005
SAS Storage Architecture: Serial Attached SCSI, 2005, Mike Jackson, 0977087808, 9780977087808, MindShare Press, 2005 DOWNLOAD http://bit.ly/1zNQCoA http://www.barnesandnoble.com/s/?store=book&keyword=SAS+Storage+Architecture%3A+Serial+Attached+SCSI SAS (Serial Attached SCSI) is the serial storage interface that has been designed to replace and upgrade SCSI, by far the most popular storage interface for high-performance systems for many years. Retaining backward compatibility with the millions of lines of code written to support SCSI devices, SAS incorporates recent advances in high-speed serial design to provide better performance, better reliability and enhanced capabilities, all at a lower cost. SAS will be a significant part of many future high-performance storage systems, and hardware designers, system validation engineers, device driver developers and others working in this area will need a working knowledge of it.SAS Storage Architecture provides a comprehensive guide to the SAS standard. The book contains descriptions and numerous examples of the concepts presented, using the same building block approach as other MindShare offerings. This book details important concepts relating to the design and implementation of storage networks.Specific topics of interest include:SATA Compatibility Expander devices Discovery Process Connection protocols Arbitration of competing connection requests Flow Control protocols ACK/NAK protocol Primitives ? construction and uses Frames ? format, definition, used of each field Error checking mechanisms -
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SAS Enters the Mainstream Although Adoption of Serial Attached SCSI
SAS enters the mainstream By the InfoStor staff http://www.infostor.com/articles/article_display.cfm?Section=ARTCL&C=Newst&ARTICLE_ID=295373&KEYWORDS=Adaptec&p=23 Although adoption of Serial Attached SCSI (SAS) is still in the infancy stages, the next 12 months bode well for proponents of the relatively new disk drive/array interface. For example, in a recent InfoStor QuickVote reader poll, 27% of the respondents said SAS will account for the majority of their disk drive purchases over the next year, although Serial ATA (SATA) topped the list with 37% of the respondents, followed by Fibre Channel with 32%. Only 4% of the poll respondents cited the aging parallel SCSI interface (see figure). However, surveys of InfoStor’s readers are skewed by the fact that almost half of our readers are in the channel (primarily VARs and systems/storage integrators), and the channel moves faster than end users in terms of adopting (or at least kicking the tires on) new technologies such as serial interfaces. Click here to enlarge image To get a more accurate view of the pace of adoption of serial interfaces such as SAS, consider market research predictions from firms such as Gartner and International Data Corp. (IDC). Yet even in those firms’ predictions, SAS is coming on surprisingly strong, mostly at the expense of its parallel SCSI predecessor. For example, Gartner predicts SAS disk drives will account for 16.4% of all multi-user drive shipments this year and will garner almost 45% of the overall market in 2009 (see figure on p. 18). -
For Immediate Release
an ellisys company FOR IMMEDIATE RELEASE SerialTek Contact: Simon Thomas, Director, Sales and Marketing Phone: +1-720-204-2140 Email: [email protected] SerialTek Debuts PCIe x16 Gen5 Protocol Analysis System and Web Application New Kodiak™ Platform Brings SerialTek Advantages to More Computing and Data Storage Markets Longmont, CO, USA — February 24, 2021 — SerialTek, a leading provider of protocol test solutions for PCI Express®, NVM Express®, Serial Attached SCSI, and Serial ATA, today introduced an advancement in the PCIe® test and analysis market with the release of the Kodiak PCIe x16 Gen5 Analysis System, as well as the industry’s first calibration-free PCIe x16 add-in-card (AIC) interposer and a new web-based BusXpert™ user interface to manage and analyze traces more efficiently than ever. The addition of PCIe x16 Gen5 to the Kodiak analyzer and SI-Fi™ interposer family brings previously unavailable analysis capabilities and efficiencies to computing, datacenter, networking, storage, AI, and other PCIe x16 Gen5 applications. With SerialTek’s proven calibration-free SI-Fi interposer technology, the Kodiak’s innovative state-of-the-art design, and the new BusXpert analyzer software, users can more easily set up the analyzer hardware, more accurately probe PCIe signals, and more efficiently analyze traces. Kodiak PCIe x16 Gen5 Analysis System At the core of the Kodiak PCIe x16 analyzer is an embedded hardware architecture that delivers substantial and unparalleled advancements in capture, search, and processing acceleration. Interface responsiveness is markedly advanced, searches involving massive amounts of data are fast, and hardware filtering is flexible and powerful. “Once installed in a customer test environment the Kodiak’s features and benefits are immediately obvious,” said Paul Mutschler, CEO of SerialTek. -
Serial Attached SCSI (SAS) Interface Manual
Users Guide Serial Attached SCSI (SAS) Interface Manual Users Guide Serial Attached SCSI (SAS) Interface Manual ©2003, 2004, 2005, 2006 Seagate Technology LLC All rights reserved Publication number: 100293071, Rev. B May 2006 Seagate, Seagate Technology, and the Seagate logo are registered trademarks of Seagate Technology LLC. SeaTools, SeaFAX, SeaFONE, SeaBOARD, and SeaTDD are either registered trademarks or trade- marks of Seagate Technology LLC. Other product names are registered trademarks or trademarks of their owners. Seagate reserves the right to change, without notice, product offerings or specifications. No part of this publication may be reproduced in any form without written permission of Seagate Technology LLC. Revision status summary sheet Revision Date Writers/Engineers Notes Rev. A 11/11/04 J. Coomes Initial release. Rev. B 05/07/06 C. Chalupa, J. Coomes, G. Houlder All. Contents 1.0 Interface requirements. 1 1.1 Acknowledgements . 1 1.2 How to use this interface manual . 1 1.2.1 Scope . 2 1.2.2 Applicable specifications . 2 1.2.3 Other references . 3 1.3 General interface description. 3 1.3.1 Introduction to Serial Attached SCSI Interface (SAS) . 3 1.3.2 The SAS interface . 3 1.3.3 Glossary . 5 1.3.4 Keywords . 16 1.4 Physical interface characteristics. 17 1.5 Bit and byte ordering . 17 2.0 General . 19 2.1 Architecture . 19 2.1.1 Architecture overview . 19 2.1.2 Physical links and phys . 19 2.1.3 Ports (narrow ports and wide ports) . 20 2.1.4 SAS devices . 21 2.1.5 Expander devices (edge expander devices and fanout expander devices) . -
Comparing Fibre Channel, Serial Attached SCSI (SAS) and Serial ATA (SATA)
Comparing Fibre Channel, Serial Attached SCSI (SAS) and Serial ATA (SATA) by Allen Hin Wing Lam Bachelor ofElectrical Engineering Carleton University 1996 PROJECT SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF ENGINEERING In the School ofEngineering Science © Allen Hin Wing Lam 2009 SIMON FRASER UNIVERSITY Fall 2009 All rights reserved. However, in accordance with the Copyright Act ofCanada, this work may be reproduced, without authorization, under the conditions for Fair Dealing. Therefore, limited reproduction ofthis work for the purposes ofprivate study, research, criticism, review and news reporting is likely to be in accordance with the law, particularly ifcited appropriately. Approval Name: Allen Hin Wing Lam Degree: Master ofEngineering Title ofProject: Comparing Fibre Channel, Serial Attached SCSI (SAS) and Serial ATA (SATA) Examining Committee: Chair: Dr. Daniel Lee Chair ofCommittee Associate Professor, School ofEngineering Science Simon Fraser University Dr. Stephen Hardy Senior Supervisor Professor, School ofEngineering Science Simon Fraser University Jim Younger Manager, Product Engineering PMC- Sierra, Inc. Date ofDefence/Approval r 11 SIMON FRASER UNIVERSITY LIBRARY Declaration of Partial Copyright Licence The author, whose copyright is declared on the title page of this work, has granted to Simon Fraser University the right to lend this thesis, project or extended essay to users of the Simon Fraser University Library, and to make partial or single copies only for such users or in response -
Nvme SSD Controller
EVERYTHING YOU WANTED TO KNOW ABOUT STORAGE BUT WERE TOO PROUD TO ASK Part Aqua Storage Controllers May 15, 2018 10:00 am PT Today’s Presenters J Metz Craig Carlson John Kim Peter Onufryk Chad Hintz Cisco Cavium Mellanox Microsemi Cisco © 2018 Storage Networking Industry Association. All Rights Reserved. 2 SNIA-At-A-Glance © 2018 Storage Networking Industry Association. All Rights Reserved. 3 SNIA Legal Notice The material contained in this presentation is copyrighted by the SNIA unless otherwise noted. Member companies and individual members may use this material in presentations and literature under the following conditions: Any slide or slides used must be reproduced in their entirety without modification The SNIA must be acknowledged as the source of any material used in the body of any document containing material from these presentations. This presentation is a project of the SNIA. Neither the author nor the presenter is an attorney and nothing in this presentation is intended to be, or should be construed as legal advice or an opinion of counsel. If you need legal advice or a legal opinion please contact your attorney. The information presented herein represents the author's personal opinion and current understanding of the relevant issues involved. The author, the presenter, and the SNIA do not assume any responsibility or liability for damages arising out of any reliance on or use of this information. NO WARRANTIES, EXPRESS OR IMPLIED. USE AT YOUR OWN RISK. © 2018 Storage Networking Industry Association. All Rights Reserved. 4 Controllers! So many things to Up, Up, Down, control, so little time! Down, Left, Right, Left, Right, B, A, storage Start! © 2018 Storage Networking Industry Association. -
Hypertransport Extending Technology Leadership
HyperTransport Extending Technology Leadership International HyperTransport Symposium 2009 February 11, 2009 Mario Cavalli General Manager HyperTransport Technology Consortium Copyright HyperTransport Consortium 2009 HyperTransport Extending Technology Leadership HyperTransport and Consortium Snapshot Industry Status and Trends HyperTransport Leadership Role February 11, 2009 Mario Cavalli General Manager HyperTransport Technology Consortium Copyright HyperTransport Consortium 2009 HyperTransport Snapshot Low Latency, High Bandwidth, High Efficiency Point-to-Point Interconnect Leadership CPU-to-I/O CPU-to-CPU CPU-to-Coprocessor Copyright HyperTransport Consortium 2009 Adopted by Industry Leaders in Widest Range of Applications than Any Other Interconnect Technology Copyright HyperTransport Consortium 2009 Snapshot Formed 2001 Controls, Licenses, Promotes HyperTransport as Royalty-Free Open Standard World Technology Leaders among Commercial and Academic Members Newly Elected President Mike Uhler VP Accelerated Computing Advanced Micro Devices Copyright HyperTransport Consortium 2009 Industry Status and Trends Copyright HyperTransport Consortium 2009 Global Economic Downturn Tough State of Affairs for All Industries Consumer Markets Crippled with Long-Term to Recovery Commercial Markets Strongly Impacted Copyright HyperTransport Consortium 2009 Consequent Business Focus Cost Effectiveness No Redundancy Frugality Copyright HyperTransport Consortium 2009 Downturn Breeds Opportunities Reinforced Need for More Optimized, Cost-Effective Computing -
The Benefits of Serial Attached SCSI (SAS) for External Subsystems
SERVER STORAGE SOLUTIONS WHITE PAPER The Benefits of Serial Attached SCSI (SAS) for External Subsystems Serial Attached SCSI (SAS), the follow-on to parallel The first SAS prototypes were announced in 2003 and SCSI, is designed for high-performance enterprise were a major step to achieving mass market requirements and offers both the benefits of backward availability. Those prototypes allowed development of compatibility with SCSI and interoperability with the first generation of technologies and products that Serial ATA (SATA), bringing enterprises a flexibility bring the benefits of SAS into the enterprise. These and cost savings previously not possible. SAS provides products have been developed and tested, and enable a significant benefits to external storage subsystems and wide variety of integrated solutions. offers users “one-stop-shopping” to satisfy their Interoperability testing was a key component of SAS, requirements for the following three main data types; because it increases the architecture’s flexibility by Throughput Data Transaction Data Reference Data supporting both SAS and SATA disk drives and components. Interoperability allows one vendor’s SAS • High MB/s and large • Maximum IOPs for OLTP, • Fixed content, archival data data-intensive files calculation intensive files for secondary/nearline products to be compatible with another’s, and it also • Large block, random • Small block, random storage ensures products developed today will work with all read/writes read/writes • Large block, sequential existing and next-generation -
A Unified Memory Network Architecture for In-Memory
A Unified Memory Network Architecture for In-Memory Computing in Commodity Servers Jia Zhan∗, Itir Akgun∗, Jishen Zhao†, Al Davis‡, Paolo Faraboschi‡, Yuangang Wang§, and Yuan Xie∗ ∗University of California, Santa Barbara †University of California, Santa Cruz ‡HP Labs §Huawei Abstract—In-memory computing is emerging as a promising largely residing in main memory, they also pose significant paradigm in commodity servers to accelerate data-intensive challenges in DRAM scaling, especially for memory capacity. processing by striving to keep the entire dataset in DRAM. To If the large dataset cannot fit entirely in memory, it has to address the tremendous pressure on the main memory system, discrete memory modules can be networked together to form a be spilled to disk, thus causing sub-optimal performance due memory pool, enabled by recent trends towards richer memory to disk I/O contention. Unfortunately, with the current DDRx interfaces (e.g. Hybrid Memory Cubes, or HMCs). Such an inter- based memory architecture, the scaling of DRAM capacity memory network provides a scalable fabric to expand memory falls far behind the growth of dataset size of in-memory capacity, but still suffers from long multi-hop latency, limited computing applications [12]. A straightforward approach to bandwidth, and high power consumption—problems that will continue to exacerbate as the gap between interconnect and increase memory capacity is to add more CPU sockets for transistor performance grows. Moreover, inside each memory additional memory channels. However, this will introduce module, an intra-memory network (NoC) is typically employed to significant hardware cost [13]. Moreover, in a multi-socket connect different memory partitions. -
Introduction to AGP-8X
W H I T E P A P E R Introduction to AGP-8X Allan Chen Jessie Johnson Angel Suhrstedt ADVANCED MICRO DEVICES, INC. One AMD Place Sunnyvale, CA 94088 Page 1 Introduction to AGP-8X May 10, 2002 W H I T E P A P E R Background Tremendous efforts have been made to improve computing system performance through increases in CPU processing power; however, I/O bottlenecks throughout the computing platform can limit the system performance. To eliminate system bottlenecks, AMD has been working with industry leaders to implement innovative technologies including AGP, DDR SDRAM, USB2.0, and HyperTransport™ technology. This white paper will provide an overview of the latest graphics subsystem innovation: AGP-8X. Introduction The Accelerated Graphics Port (AGP) was developed as a high-performance graphics interface. It alleviates the PCI graphics bottleneck by providing high bandwidth throughput and direct access to system memory. The new AGP3.0 specification adds an 8X mode definition, which doubles the maximum data transfer rate from the previous high reached with AGP-4X by doubling the amount of data transferred per AGP bus cycle. Figure 1 shows the graphic interface bandwidth performance evolution from PCI to AGP-8X. In this figure, AGP3.0 refers to the specific AGP interface specification. AGP-1X, AGP-2X, AGP-4X and AGP-8X represent the data transfer speed mode. Graphics Interface Peak Bandwidth 2500 2000 1500 1000 Bandwidth (MB/s) 500 0 PCI AGP1X AGP2X AGP4X AGP8X AGP 1.0 Specification AGP 2.0 Specification AGP 3.0 Specification Figure 1: Available bandwidth of different graphic interfaces. -
AMD Opteron™ 4000 Series Platform Quick Reference Guide
AMD Opteron™ 4000 Series Platform Quick Reference Guide The AMD Opteron™ 4100 Series processor, the world’s lowest power per core processor1, sets the foundation for cloud workloads and affordability for mainstream infrastructure servers with prices starting at $992. AMD Opteron™ 4100 Series Processor END USER BENEFITS Outstanding Performance-Per-Watt > Designed from the ground up to handle demanding server workloads at the lowest available energy draw, beating the competition by as much as 40% (per/core).1 Business Value > The world’s first 1P and 2P capable processor at sub $100 pricing.2 Easy to Purchase and Operate > Scalable solutions with feature, component and platform consistency. PRODUCT FEATURES New AMD-P 2.0 Power Savings Features: > Ultra-low power platforms provide power efficiency beyond just the processor, 3 SOUNDBITE for both 1P and 2P server configurations. THE WORLD’S LOWEST POWER PER CORE SERVER PROCESSOR1 > APML (Advanced Platform Management Link)4 provides an interface for processor and systems management monitoring and controlling of system resources such as platform power Quick Features consumption via p-state limits and CPU thermals to closely monitor power and cooling. AMD-P 2.0: > Link Width PowerCap which changes all 16-bit links to 8-bit links5 can help power conscious Ultra-low power platform > customers improve performance-per-watt. > Advanced Platform Management Link (APML)4 > AMD CoolSpeed Technology reduces p-states when a temperature limit is reached to allow a > Link Width PowerCap server to operate if the processor’s thermal environment exceeds safe operational limits. > AMD CoolSpeed Technology > When C1E5,6 is enabled, the cores, southbridge and memory controller enter a sleep state that > C1E6 can equate to significant power savings in the datacenter depending on system configuration.