A Reconfigurable Architecture Via Grain Perception Operator

International Conference on Intelligent Control and Computer Application (ICCA 2016) A Reconfigurable Architecture via Grain Perception Operator Fan Yang Laixin Shen Sheng Li Run Wang School of Information and School of Information and College of Science School of Information and Engineering Engineering Anhui University of Science Engineering Huangshan University Huangshan University & Technology Huangshan University Huangshan, Anhui, China Huangshan, Anhui, China Huainan, Anhui, China Huangshan, Anhui, China Abstract—Application tasks are complex and diverse, which intensive computing, stream intensive, data intensive need HPC (High Performance Computing) to solve them. The computing, I/O intensive tasks, internal mixed parallelism. The computing efficiency is hugely different when they run in same application running in different structures has operational different architectures, because different application tasks have performance differences. The time complexity of matrix different computing features. The PMC (Processor-Memory- multiplication on a serial processor is O(n3), and is O(3n) in a Communication) resource requirements of application tasks are parallel structure Mesh, and is O(n) in the Torus structure. The perceived to get PMC operating grain, and the best matched single architecture is unable to meet many complex application architecture is assigned to the application. Hypergraph is used to describe the application structure and the computing tasks. Reconfigurable computing has been applied in many architecture, and its isomorphic principle is utilized to build and HPC, and its architecture is used to design a variable structure demonstrate the super-mixed heterogeneous architecture. to adapt different application tasks [3]. Reconfigurable Experiments show that reconfigurable architecture based on computing makes HPC feasible and further improves the operator grain perception has characteristic high computing and computing power, low power consumption, low cost, and low low energy consumption. development cycle, which provides an effective way to solve the technical wall problems. Keywords—High performance; architecture; perception; PMC grain operator; Hypergraph In this paper, according to some basic algorithm research of commonly used, such as linear algebraic, combinatorial optimization, graph algorithms, and image processing, different I. INTRODUCTION computing characteristics need different complicated algorithm HPC (High Performance Computing) application problem and running structure. At the same time, according to the is becoming more and more complex and diverse, involving calculation characteristics of various types of processing many different calculating types, which include atmospheric components, the analysis and calculation of application tasks in science, molecular dynamic, material science, fluid mechanic, the algorithm of particle size of each sub-algorithm are quantum chemistry, signal processing, bioinformatics, and important, and the PMC of each sub-algorithm is particle other disciplines, such as linear algebra, Fourier transform, calculated and the current state of existing components are also search sorting [1]. HPC system is mainly divided into two computed by the perceptron algorithm. The sub-structure is categories: 1) In a MPP (Massive Parallel Processing) designed reasonably, and the sub-algorithm is assigned to the architecture based on homogeneous system, the energy sub-structure in order to suit the calculation characteristic to get consumption is very serious and the actual running rate is low. a computing model for different system structures according to 2) The advanced CPUs with accelerator processor, such as the the application of tasks. So the sub-algorithm can realize the Cell, GPU, FPGA, DSP are composed of heterogeneous special highest computing performance, and achieve sub-parts on a systems and their components can accelerate heterogeneous high utilization rate. architecture, which greatly raise the application performance and effectively reduce power consumption. The heterogeneous II. RELATED WORKS architecture becoming a HPC is one of the important developing trends. Different dedicated processors have Reconfigurable computing and HPC are hot research at significant differences in term of performance and application home and abroad. [2] pointed out that whether the integrated field, such as image and floating point operations in GPU, circuits develop, HPC or the Internet and memory, about in whose efficiency is 50~100 times than CPU, and the 2020, there will be encountering insurmountable information combination of general processor and dedicated processor is technology wall. The classification model of computer the key to high performance in heterogeneous system [2]. architecture was given in [3], which was proposed for heterogeneous system structure in chip level, node level and Different calculating tasks are with different characteristics system level according to the interconnection model of that need to compute their PMC by resource requirements architecture based on different hardware granularity. [4] varying. There are some resource model including the common proposed an flow model based on the service execution and © 2016. The authors - Published by Atlantis Press 16 system designing object. [5] presented a practical parallel the PMC grains of components or sub-structures are also computation models named the LogGP synchronization model, calculated. Perception algorithm is used to calculate grain which is based on non-exclusive heterogeneous and reflected characteristics of components and application. The matching the impact of heterogeneity and non-exclusive computing component or sub-structure is assigned to different applications environment for concurrent algorithm design and analysis from and reach the targets of high performance and low energy the system level. A reconfigurable architecture [6] was consumption. analyzed and gave the design method for general purpose and special purpose in energy consumption level multi-processor in A. The basic concept of grain calculating special applications with 500 times performance improvement, Grain calculating is applied to perceive the characteristics and 70% energy saving. [7] pointed out that a reconfigurable of tasks and obtain a pattern. Components and sub-structures architecture can make the hardware resources behavior to adapt are also need to calculate their grain features, including to the special computing requirements on hardware resources numerical algorithms, combinatorial optimization algorithm, level, which provides an interactive mechanism to maximize fast Fourier transform, image processing. The matrix the use of logic resources. multiplication can be regarded as a basic grain. [8] proposed the system level granularity architecture, Grain calculating has many characteristics, such as which put forward reconfigurable computing applications with independence, diversity, universality, and intensive features hybrid interconnected manner in static and dynamic science. [9] including computation intensive, data intensive, worked in a large-scale multiprocessor network, and used communication intensive, storage intensive. Granularity optical interconnection equipment to complete the characteristics involve instruction level fine-grained, process heterogeneous architecture design. [10] proposed that using function level granularity, program process coarse granularity, multi-FPGAs system structure, the fine-grained and coarse- operation service level granularity. Structure characteristics grained partition problem behavior, whose memory space was include a branch, loop, order, and pattern feature, which effectively used. [11] putted forward the calculation of the includes cell task pools, stream/serial, and task/data parallel. HPC necessity. The above thesis was presented respectively in Some algorithm grains are shown in Table 1. the level of hardware, operating system, scheduling algorithm, such as the interconnection of the reconfigurable architecture design, but only single architecture is used to solve different TABLE I. GRAIN CALCULATING DESCRIPTION OF COMMONLY USED application tasks with different complexities and diversities. ALGORITHM (PART) There is lack of viewing the application task angle, where Commonly used algorithm grain calculating system structure may be suitable for its computing features and the calculation of the performance and energy consumption Support vector machine dense matrix should be taken into account. [12] proposed the viewpoint of SuperLU/OSKI/SpMV Sparse matrix "Application deicide its structure, structure decide its FFT/DFT/SFT/IFFT Spectral matrix effectiveness". According to different applications, revealing Hash/CRC/RSA Combinational logic the application characteristics of the reality problems, the Bayesian Markov/HMM Graph model suitable different variable system structure model can be designed to make the structure suitable for the application. BP/ANN Dynamic program Thus, the optimal target including high computing performance Monte Carlo/similar Graphs and energy consumption can obtain. Fast multi-stage N-Body [13] determined the minimum number of hyper edges in a Video compression/group Finite automata hypergraph and characterized the hyper edges of a k-partition- connected hypergraph. [14] used hypergraph to assemble all local link structures, and employed HMETIS for hypergraph B. PMC grain calculating model of algorithms partitioning. [15] proposed

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