Organic Light-Emitting Diode (Oled) Display Panel, Oled Display Device and Method for Driving the Same

(19) TZZ¥__T

(11) EP 3 147 894 A1

(12) EUROPEAN PATENT APPLICATION

(43) Date of publication: (51) Int Cl.: 29.03.2017 Bulletin 2017/13 G09G 3/3225 (2016.01) G09G 3/3233 (2016.01)

(21) Application number: 16190336.4

(22) Date of filing: 23.09.2016

(84) Designated Contracting States: (72) Inventors: AL AT BE BG CH CY CZ DE DK EE ES FI FR GB • NA, Se-Hwan GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO 10895 Gyeonggi-do (KR) PL PT RO RS SE SI SK SM TR • LEE, Jae-Young Designated Extension States: 07350 Seoul (KR) BA ME • KIM, Mi-Jung Designated Validation States: 06923 Seoul (KR) MA MD (74) Representative: Viering, Jentschura & Partner (30) Priority: 25.09.2015 KR 20150136459 mbB Patent- und Rechtsanwälte (71) Applicant: LG Display Co., Ltd. Am Brauhaus 8 Yeongdeungpo-gu 01099 Dresden (DE) Seoul 07336 (KR)

(54) ORGANIC LIGHT-EMITTING DIODE (OLED) DISPLAY PANEL, OLED DISPLAY DEVICE AND METHOD FOR DRIVING THE SAME

(57) Disclosed herein are an OLED display panel (410) further including a switching transistor (T-SW) for controlling application of supply voltage (VDD_EL) in the initializing interval of a pixel (P), an OLED display device including the same, and a method for driving the same. The OLED display panel (410) avoids a short-circuit between supply voltage VDD_EL and reference voltage Vref to thereby reduce initialization voltage applied to the gate terminal of the driving transistor T_dr. The OLED display device can achieve various effects such as improved response characteristics of pixels by reducing deviation in the initial voltage used in sampling. EP 3 147 894 A1

Printed by Jouve, 75001 PARIS (FR) 1 EP 3 147 894 A1 2

Description the switching transistor T_sw is connected to a scan line, and the drain electrode of the switching transistor T_sw CROSS REFERENCE TO RELATED APPLICA- is connected to a terminal of the storage capacitor C. The TION(S) switching transistor T_sw is turned on when a scan signal 5 Scan is applied via the scan line to allow data voltage to [0001] This application claims priority from Republic of be applied to the storage capacitor C. Korea Patent Application No. 10-2015-0136459 filed on [0011] The source electrode of the first transistor T1 is September 25, 2015. connected to a reference voltage line Vref and the gate electrodeof the first transistorT1 is connectedto an emis- BACKGROUND 10 sion control line, and the drain electrode of the first transistor T1 is connected to the terminal of the storage ca- 1. Technical Field pacitor C. The first transistor T1 is turned on when an emission control signal EM is applied via the emission [0002] The present disclosure relates to an organic control line to allow reference voltage Vref to be applied light-emitting diode (OLED) display panel, an OLED dis- 15 to the terminal of the storage capacitor C. play device including the same, and a method for driving [0012] The source electrode of the second transistor the same. More specifically, the present disclosure re- T2 is connected to the other terminal of the storage ca- lates to an OLED display panel further including a switch- pacitor C, the gate electrode of the second transistor T2 ing transistor for controlling application of supply voltage is connected to the scan line, and the drain electrode of in the initializing interval of a pixel, an OLED display de- 20 the second transistor T2 is connected to the drain elec- vice including the same, and a method for driving the trode of the driving transistor T_dr. same. [0013] The source electrode of the third transistor T3 isconnected to the drainelectrode ofthe driving transistor 2. Description of the Related Art T_dr, the gate electrode of the third transistor T3 is con- 25 nected to the emission control line, and the drain elec- [0003] As the information-oriented society evolves, trode of the third transistor T3 is connected to the anode various demands for display devices are ever increasing. electrode of the OLED. Recently, a variety of flat display devices such as liquid- [0014] The source electrode of the fourth transistor T4 crystal display (LCD) devices, plasma display panel is connected to the anode electrode of the OLED, the (PDP) devices, and organic light-emitting diode (OLED) 30 gate electrode of the fourth transistor T4 is connected to display devices have been utilized. the scan line, and the drain electrode of the fourth tran- [0004] Among these, an OLED display device is ad- sistor T4 is connected to the reference voltage Vref line. vantageous over other flat display devices in that it can [0015] The source electrode of the driving transistor be driven with low voltage, can be made thinner, has T_dr is connected to the supply voltage VDD_EL termi- good viewing angle and fast response speed, and so on. 35 nal, the gate electrode of the driving transistor T_dr is Accordingly, OLED display devices find more and more connected to the other terminal of the storage capacitor applications. C, and the drain electrode of the driving transistor T_dr [0005] FIG. 1 is a circuit diagram of a pixel of an OLED is connected to the drain electrode of the second tran- display device in the related art, FIG. 2 is a timing chart sistor T2. While the driving transistor T_dr is turned on, for driving the pixel, and FIG. 3 is a graph showing re- 40 current flows to the OLED so that the OLED emits light. sponse time (R/T) characteristics according to different [0016] The intensity of the light emitted from the OLED initializing time intervals. is proportional to the amount of the current flowing in the [0006] FIG. 1 is an equivalent circuit diagram of a pixel OLED, and the amount of the current flowing in the OLED of an OLED display device in the related art, which has is proportional to the magnitude of the data voltage DATA the typical 6T1C (six transistors and one capacitor) struc- 45 applied to the gate electrode of the driving transistor T_dr. ture. [0017] In this manner, the OLED display device can [0007] Referring to FIG. 1, the pixel of the typical OLED display a variety of images by applying data voltages display device includes six transistors, one capacitor, an having different magnitudes to the pixel areas to display OLED, etc. different gradations. [0008] That is, in the pixel area, first to fourth transistors 50 [0018] The storage capacitor C holds data voltage DA- T1 to T4, a switching transistor T_sw, a driving transistor TA for a frame to regulate the amount of the current flow- T_dr, a storage capacitor C, and an OLED may be ing in the OLED and maintains the gradation displayed formed. by the OLED. [0009] The first to fourth transistors T1 to T4, the [0019] FIG. 2 is a timing chart for driving the OLED switching transistor T_sw and the driving transistor T_dr 55 display device of FIG. 1. may be p-type transistors. [0020] Referring to FIG. 2, it can be seen that the emis- [0010] The source electrode of the switching transistor sion control signal EM is deactivated immediately after T_sw is connected to a data line, the gate electrode of the scan signal Scan is applied. In doing so, data ad-

2 3 EP 3 147 894 A1 4 dressing and Vth (threshold voltage) compensation are vide an OLED display panel further including a switching carried out. In particular, the time period in which both of transistor for controlling application of supply voltage the emission control signal EM and the scan signal Scan VDD_EL in the initializing time interval of a pixel, an are in on-state is the initializing time interval I of the pixel. OLED display device including the same, and a method It is noted that since the transistors are P type transistors, 5 for driving the same. the emission control signal EM and scan signal Scan are [0029] It is another aspect of the present disclosure to active and in the on-state when they are logic low, and provide an OLED display panel with improved response they are deactivated and in the off-state when they are characteristics of pixels by way of avoiding a short-circuit logic high. between supply voltage VDD_EL and reference voltage [0021] For the pixel having the 6T1C structure de-10 Vref to thereby reduce initialization voltage applied to the scribed above with reference to FIG. 1, all of the transis- gate terminal of the driving transistor T_dr. tors are turned on during the initializing time interval I in [0030] It is yet another aspect of the present disclosure which both of the emission control signal EM and the to provide an OLED display panel with improved re- scan signal Scan are in on-state. sponse characteristics by increasing the initialization [0022] In other words, the gate electrodes of all of the 15 time interval of pixels, an OLED display device including transistors T_sw, T_dr and T1 to T4 disposed in the pixel the same, and a method for driving the same. receive the emission control signal EM or the scan signal [0031] As described above, the OLED display device Scan directly or indirectly, and thus all of the transistors having the typical 6T1C pixel structure has the problem remain turned on during the time interval I in which the that response time delay occurs due to deviation in the scan signal is applied on the scan line, and the signal on 20 initial voltage used in sampling, especially when the the emission control line EM is in an on-state. screen is changed from black to white. [0023] As a result, a short-circuit is created between [0032] In one embodiment, to overcome the problem, the supply voltage VDD_EL and the reference voltage an exemplary embodiment of the present disclosure pro- Vref during the initializing time interval I. That is, the ini- vides an OLED display panel further including an addi- tialization voltage applied at the gate terminal of the driv- 25 tional transistor T5 which is disposed between the supply ing transistor T_dr equals to: voltage VDD_EL terminal and the driving transistor T_dr and controls application of the supply voltage VDD_EL VDD_EL - Vref - a, to the driving transistor T_dr during the process of initial- where a denotes a voltage that varies depending on izing a pixel. data of a previous frame. 30 [0033] A control signal of the transistor T5 may be another emission control signal EM(n-1) of the immediately [0024] Due to the voltage a, the voltage at the gate previous stage of a circuit that generates the emission terminal of the driving transistor T_dr increases in black control signal EM(n), a processed signal using an emis- screen while it decreases in white screen, such that de- sion control signal EM(n-k) of a previous stage ahead of viation in the initial voltage used in sampling occurs, re- 35 the emission control signal EM(n) by k stages, or a control sulting in response time delay. signal supplied from a separate driving circuit. [0025] Such a problem can be somewhat improved by [0034] In the exemplary embodiment, a scan signal increasing the initializing time interval. However, there is may be continuously applied in an active state while the a problem in that the luminous efficiency at the first frame control signal is supplied in an active state and the emis- is still less than or equal to 50%. 40 sion control signal EM(n) is deactivated, and the time [0026] FIG. 3 is a graph showing response time char- period in which the control signal is supplied in the active acteristics of the OLED display device shown in FIG. 1 state may be used as the initializing time interval of the according to different initializing time intervals. That is, pixel. FIG. 3 is a graph showing changes in brightness accord- [0035] In addition, with the configuration, it is possible ing to initializing time intervals when the screen 45 is to avoid a short-circuit from being created between the changed from black to white. supply voltage VDD_EL and the reference voltage Vref [0027] FIG. 3 shows changes in brightness over time during the initializing time interval of a pixel, such that according to the initialization times of 0 ms (a), 1 ms (b) the initial voltage applied to the gate terminal of the driving and 2 ms (c). It can be seen that the longer initializing transistor T_dr can be reduced. As a result, there are time intervals exhibit better response characteristics.50 many advantages such as reduced deviation in the initial However, it can be seen that the brightness immediately voltage used in sampling, improved response character- after the screen is changed from black to white (after 0.01 istics of the pixel, and so on. second) is still 50% or less of the normal value in all of [0036] According to an exemplary embodiment of the the initialization times of (a), (b) and (c). present disclosure, it is possible to eliminate the possi- 55 bility that a short-circuit is created between the supply SUMMARY voltage VDD_EL and the reference voltage Vref during the initializing time interval of a pixel. [0028] It is an aspect of the present disclosure to pro- [0037] Accordingly, the initial voltage applied to the

3 5 EP 3 147 894 A1 6 gate terminal of the driving transistor T_dr can be re- after the scan signal is activated until the emission control duced, such that deviation in the initial voltage used in signal supplied via the emission control line is deactivat- sampling can be reduced. As a result, the response char- ed. acteristics of the pixel can be improved. [0045] In one or more embodiments, a control signal [0038] In addition, the initializing time interval of the 5 is applied via the control line to the fifth transistor, and pixel can be increased by using the control signal for the the scan signal is continuously applied in an active state supply voltage VDD_EL, thereby further improving re- while the control signal is supplied in an active state and sponse characteristics. the emission control signal EM(n) is deactivated (1H). [0039] Moreover, the initial sampling voltage can be [0046] In one or more embodiments, the switching uniformly applied to the pixels with the reference voltage 10 transistor, the capacitor, the driving transistor, the first Vref, such that defects such as afterimage or spots can transistor, the second transistor, the third transistor, the be suppressed. fourth transistor, and the fifth transistor are all included [0040] An organic light-emitting diode (OLED) display within a pixel of the OLED display panel. panel according to various embodiments may comprise: [0047] An organic light-emitting diode (OLED) display a scan line for transmitting a scan signal, and a data line 15 device according to various embodiments may comprise: for transmitting a data signal, the scan line intersecting an organic light-emitting diode display panel according thedata line; aswitching transistor toallow the data signal to one or more embodiments described herein and con- to be supplied to an output stage in response to the scan figured to display images; a gate driver configured to sup- signal; a capacitor to store a voltage corresponding to ply a scan signal to the display panel via the scan line of the data signal; a driving transistor to control a current 20 the display panel; a data driver configured to supply a applied to an OLED based on the voltage stored in the data signal to the display panel via the data line of the capacitor; a first transistor connected to an emission con- display panel; and a timing controller configured to control line, a reference voltage line and a terminal of the trol driving timings of the gate driver and the data driver. capacitor; a second transistor connected to the scan line, [0048] In one or more embodiments, said organic light- another terminal of the capacitor and a first node; a third 25 emitting diode display device further comprises a control transistor connected to the emission control line, the first signal generator that is separate from a circuit that gen- node and a second node; a fourth transistor connected erates the emission control signal, the control signal gen- to the scan line, the reference voltage line and the second erator configuredto generate thededicated control signal node; and a fifth transistor connected to a control line, a and supply the dedicated control signal to the fifth tran- supply voltage terminal, and the driving transistor. 30 sistor via the control line, wherein the fifth transistor uses [0041] In one or more embodiments, an emission con- the dedicated control signal supplied from the control sig- trol signal is applied via the emission control line, and nal generator via the control line to selectively block the another emission control signal is used as a control signal supply voltage from the supply voltage terminal. of the fifth transistor to selectively block a supply voltage [0049] An organic light-emitting diode (OLED) display signal from the supply voltage terminal, wherein the an- 35 device according to various embodiments may comprise: other emission control signal is from an immediately pre- a display panel to display images; a gate driver to supply vious stage of a circuit that generates the emission con- a scan signal via a scan line; a data driver to supply a trol signal. data signal to the display panel via a data line; and a [0042] In one or more embodiments, an emission con- timing controller to control driving timings of the gate driv- trol signal is applied via the emission control line, and 40 er and the data driver, wherein the display panel com- another emission control signal is used as a control signal prises: a switching transistor to allow the data signal to of the fifth transistor to selectively block a supply voltage be supplied to an output stage in response to the scan signal from the supply voltage terminal, wherein the an- signal; a capacitor configured to store a voltage corre- other emission control signal is from a kth previous stage sponding to the data signal; a driving transistor to control of a circuit that generates the emission control signal sup- 45 a current applied to an OLED based on the voltage stored plied via the emission control line, wherein k is a natural in the capacitor; a first transistor connected to an emis- number greater than 1. sion control line, a reference voltage line and a terminal [0043] In one or more embodiments, an emission con- of the capacitor; a second transistor connected to the trol signal is applied via the emission control line, and a scan line, another terminal of the capacitor and a first dedicated control signal is used as a control signal of the 50 node; a third transistor connected to the emission control fifth transistor to selectively block a supply voltage signal line, the first node and a second node; a fourth transistor from the supply voltage terminal, wherein the dedicated connected to the scan line, the reference voltage line and control signal is generated from a control signal generator the second node; and a fifth transistor connected to a that is separate from a circuit that generates the emission control line, a supply voltage terminal, and the driving control signal. 55 transistor. [0044] In one or more embodiments, a control signal [0050] In one or more embodiments of said OLED dis- is applied to the fifth transistor via the control line, and play device, an emission control signal is applied via the thecontrol signal is continuously applied in an active state emission control line,and another emissioncontrol signal

4 7 EP 3 147 894 A1 8 is used as a control signal of the fifth transistor to selec- them while the scan signal as well as the emission control tively block a supply voltage signal from the supply volt- signal are supplied, wherein the turned-off fifth transistor age terminal, wherein the another emission control signal blocks a supply voltage signal from being supplied to the is from an immediately previous stage of a circuit that driving transistor while the switching transistor, driving generates the emission control signal. 5 transistor, first transistor, second transistor, third transis- [0051] In one or more embodiments of said OLED dis- tor, and fourth transistor are initialized. play device, an emission control signal is applied via the [0057] In one or more embodiments, another emission emission control line, and another emission control signal control signal is used as the control signal, wherein the is used as a control signal of the fifth transistor to selec- another emission control signal is from an immediately tively block a supply voltage signal from the supply volt- 10 previous stage of a circuit that generates the emission age terminal, wherein the another emission control signal control signal. is from a kth previous stage of a circuit that generates [0058] In one or more embodiments, a processed sig- the emission control signal supplied via the emission con- nal of another emission control signal is used as a control trol line, wherein k is a natural number greater than 1. signal, and wherein the another emission control signal [0052] In one or more embodiments of said OLED dis- 15 is from a kth previous stage of a circuit that generates play device, an emission control signal is applied via the the emission control signal, wherein k is a natural number emission control line, and the OLED display device fur- greater than 1. thercomprises: a controlsignal generatorthat is separate [0059] In one or more embodiments, a dedicated con- from a circuit that generates the emission control signal, trol signal is used as the control signal of the fifth tran- thecontrol signal generator configured to generate a ded- 20 sistor, wherein the dedicated control signal is generated icated control signal and supply the dedicated control by a control signal generator that is separate from a circuit signal to the fifth transistor via the control line, wherein that generates the emission control signal. the fifth transistor uses the dedicated control signal sup- [0060] In one or more embodiments, the control signal plied from the control signal generator via the control line is continuously applied in an active state after the scan to selectively block a supply voltage signal from the sup- 25 signal is activated until the emission control signal is de- ply voltage terminal. activated. [0053] In one or more embodiments of said OLED dis- [0061] In one or more embodiments, the scan signal play device, the control line applies a control signal to is continuously applied in an active state while the control the fifth transistor, and the control signal is continuously signal is supplied in an active state and the emission applied in an active state after the scan signal is activated 30 control signal is deactivated. until the emission control signal EM(n) supplied via the emission control line is deactivated. BRIEF DESCRIPTION OF DRAWINGS [0054] In one or more embodiments of said OLED display device, the control line applies a control signal to [0062] the fifth transistor, and the scan signal is continuously 35 applied in an active state while the control signal is sup- FIG. 1 is an equivalent circuit diagram of a pixel of plied in an active state and the emission control signal is an OLED display device in the related art; deactivated. [0055] In one or more embodiments of said OLED dis- FIG. 2 is a timing chart for driving the OLED display play device, the switching transistor, the capacitor, the 40 device of FIG. 1; driving transistor, the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth FIG. 3 is a graph showing response time character- transistor are all included within a pixel of the display istics of the OLED display device shown in FIG. 1 panel. according to different initializing time intervals; [0056] Various embodiments provide a method for45 driving an organic light-emitting diode (OLED) display FIG. 4 is a block diagram of an OLED display device device comprising a switching transistor, a driving tran- according to an exemplary embodiment of the sistor, a first transistor, a second transistor, a third tran- present disclosure; sistor, a fourth transistor, a fifth transistor and a capacitor, the method comprising: supplying a scan signal as well 50 FIG. 5A is an equivalent circuit diagram of a pixel of as an emission control signal to turn on the switching an OLED display device according to an exemplary transistor, the driving transistor, the first transistor, the embodiment of the present disclosure; second transistor, the third transistor and the fourth transistor; supplying a control signal while the emission con- FIG. 5B is a timing chart for driving the OLED display trol signal is supplied to turn off the fifth transistor; and 55 device of FIG. 5A; supplying a reference voltage to the turned-on switching transistor, driving transistor, first transistor, second tran- FIG. 6A is an equivalent circuit diagram of a pixel of sistor, third transistor, and fourth transistor to initialize an OLED display device according to another exem-

5 9 EP 3 147 894 A1 10

plary embodiment of the present disclosure; signals for controlling the pixel areas P may be disposed in the display panel 410 in parallel with the plurality of FIG. 6B is a timing chart for driving the OLED display scan lines GL1 to GLn. device of FIG. 6A; [0068] All of the pixel areas P have the same configu- 5 ration and thus only one pixel will be described below. In FIG. 7A is an equivalent circuit diagram of a pixel of the following description, a scan line GL represents the an OLED display device according to yet another plurality of scan lines GL1 to GLn, a data line DL repre- exemplary embodiment of the present disclosure; sents the first to m th data lines DL1 to DLm, and an emission control line EL represents the plurality of emission FIG. 7B is a timing chart for driving the OLED display 10 control lines EL1 to ELn. device of FIG. 7A; and [0069] In each of the pixel areas P, first to fifth transistors T1 to T5, a switching transistor T_sw, a driving tran- FIG. 8 includes graphs comparing response charac- sistor T_dr, a storage capacitor C, and an OLED may be teristics of the OLED display device in the related art formed. The transistors may be p-type transistors as with those according to an exemplary embodiment 15 shown in the drawings. The configuration of each of the of the present disclosure. pixel areas P and elements thereof will be described in detail with reference to the drawings below. DETAILED DESCRIPTION [0070] The data driver 420 may include one or more ICs (not shown) supplying a data signal to the display [0063] The above objects, features and advantages 20 panel 410. The data driver 420 generates a data signal will become apparent from the detailed description with by using a converted image signal R/G/B received from reference to the accompanying drawings. Embodiments the timing controller 440 and a plurality of data control are described in sufficient detail to enable those skilled signals, and supplies the generated data signal to the in the art in the art to easily practice the technical idea of display panel 410 via the data line DL. the present disclosure. Detailed disclosures of well25 [0071] The timing controller 440 may receive a plurality known functions or configurations may be omitted in or- of image signals, a plurality of control signals such as a der not to unnecessarily obscure the gist of the present vertical synchronization signal VSY, a horizontal syn- disclosure. Hereinafter, embodiments of the present dis- chronization signal HSY and a data enable signal DE, closure will be described in detail with reference to the etc., from a system such as a graphic card via an inter- accompanying drawings. Throughout the drawings, like 30 face. In addition, the timing controller 440 may generate reference numerals refer to like elements. a plurality of data signals to supply them to the driver ICs [0064] FIG. 4 is a block diagram of an OLED display in the data driver 420. device according to an exemplary embodiment of the [0072] The gate driver 430 generates a scan signal by present disclosure. using a control signal received from the timing controller [0065] Referring to FIG. 4, the OLED display device 35 440 and supplies the generated scan signal to the display 400 according to the exemplary embodiment of the panel 410 via the scan line GL. present disclosure includes a display panel 410 for dis- [0073] That is, the OLED display device according to playing images, a data driver 420, a gate driver 430, and the exemplary embodiment shown in FIG. 4 provides the a timing controller 440 for controlling the timings of the pixel P having the 7T1C structure instead of the typical data driver 420 and the gate driver 430, etc. 40 6T1C structure. The additional fifth transistor T5 is [0066] The display panel 410 may include: a plurality switched on/off to control the supply voltage VDD_EL to of scan lines GL1 to GLn; a plurality of data lines DL1 to be applied to the driving transistor T_dr. Hereinafter, the DLm intersecting the scan lines to define a plurality of pixel structures of OLED display devices according to pixel areas P; and a plurality of emission control lines exemplary embodiments of the present disclosure will be EL1 to ELn. Each emission control line EL is connected 45 described with reference to the drawings. to a row of pixels P. In some embodiments, an emission [0074] FIG. 5A is an equivalent circuit diagram of a control line EL can be connected to two pixel rows and pixel of an OLED display device according to an exem- used for emission control for one row of pixels and used plary embodiment of the present disclosure. FIG. 5B is to control initialization time for another row of pixels. In a timing chart for driving the OLED display device of FIG. one embodiment, a shift register circuit (not shown) gen- 50 5. erates the emission control signals for the emission con- [0075] Referring to FIG. 5A, a pixel of an OLED display trol lines EL1 to ELn. The shift register circuit has multiple device according to an exemplary embodiment of the sequential register stages that shift one or more bits from present disclosure includes seven transistors, one ca- onestage tothe next in each clock cycle. The shift register pacitor, an OLED, etc. can generate the emission control signals such that one 55 [0076] That is, in the pixel area P, first to fifth transistors emission control signal is active at a time. T1 to T5, a switching transistor T_sw, a driving transistor [0067] Although not shown in FIG. 4, a plurality of ini- T_dr, a storage capacitor C, and an OLED may be tializationlines anda pluralityof control lines for supplying formed.

6 11 EP 3 147 894 A1 12

[0077] The source electrode of the switching transistor nals shifted by a shift register, the emission control signal T_swis connected to a data line DATA, thegate electrode EM(n-1) at the immediately previous stage of the shift of the switching transistor T_sw is connected to a scan register is used as the control signal of the fifth transistor line Scan, and the drain electrode of the switching tran- T5 in the n th pixel. Accordingly, during the initializing time sistor T_sw is connected to a terminal A of the storage 5 interval I’ of the pixel after the scan signal is activated capacitor C. until the emission control signal EM(n) is deactivated, the [0078] The switching transistor T_sw is turned on when fifth transistor T5 is turned off by the emission control a scan signal Scan is applied via the scan line to allow signal EM(n-1) of the immediately previous stage, such data voltage to be applied to the storage capacitor C, that the supply voltage VDD_EL is not applied to the driv- wherein the switching transistor T_sw is configured to 10 ing transistor T_dr. In one embodiment, each stage of allow the data signal to be supplied to an output stage in the shift register corresponds to a different emission line. response to the scan signal. Thus, the emission control signal of a previous stage may [0079] The source electrode of the first transistor T1 is also correspond to the emission control signal provided connected to a reference voltage Vref line, the gate elec- to a previous pixel row. trode of the first transistor T1 is connected to an emission 15 [0087] That is, the supply voltage VDD_EL is prevent- control line, and the drain electrode of the first transistor ed from being applied to the driving transistor T_DR dur- T1 is connected to the terminal A of the storage capacitor ing the initializing time interval I’, such that no short-circuit C. The first transistor T1 is turned on when an emission is created between the supply voltage VDD_EL and the control signal EM(n) is applied via the emission control reference voltage Vref, and thus voltage at the gate ter- line to allow the reference voltage Vref to be applied to 20 minal of the driving transistor T_dr and voltage at the the terminal A of the storage capacitor C. anode of the OLED can be initialized to equal voltages [0080] The source electrode of the second transistor only with the reference voltage Vref. In addition, it is pos- T2 is connected to the other terminal B of the storage sible to solve problems such as response time delay capacitor C, the gate electrode of the second transistor caused by the influence of previous frame data. T2 is connected to the scan line, and the drain electrode 25 [0088] According to the exemplary embodiment shown of thesecond transistor T2is connected toa firstnode N1. in FIG. 5A, the initializing time interval I’ of a pixel in which [0081] The source electrode of the third transistor T3 the emission control signal EM(n) as well as the scan is connected to the first node N1, the gate electrode of signal Scan are in on-state, coincides with the interval in the third transistorT3 isconnected to the emissioncontrol which the emission control signal EM(n-1) at the imme- line, and the drain electrode of the third transistor T3 is 30 diately previous stage is deactivated and in an off-state, connected to a second node N2. as shown in FIG. 5B. It is noted that since the transistors [0082] The source electrode of the fourth transistor T4 of the display are P type transistors, the emission control is connected to the second node N2, the gate electrode signals EM and scan signal Scan are active and in the of the fourth transistor T4 is connected to the scan line, on-state when they are logic low, and they are deactivat- and the drain electrode of the fourth transistor T4 is con- 35 ed and in the off-state when they are logic high. nected to the reference voltage line Vref. [0089] As a result, the time of 1H in which the emission [0083] The source electrode of the fifth transistor T5 is control signal EM(n-1) is deactivated can be fully used connected to a supply voltage VDD_EL, the gate elec- as the initializing time interval of the pixel, such that per- trode of the fifth transistor T5 is connected to an emission formance can be further improved. 1H may refer to a control line of a previous stage, and the drain electrode 40 single horizontal period. The relationship between the of the fifth transistor T5 is connected to the source elec- initializing time intervals and response characteristics trode of the driving transistor T_dr. has already been described above with reference to FIG. [0084] The source electrode of the driving transistor 3. T_dr is connected to the drain electrode of the fifth tran- [0090] In the exemplary embodiment shown in FIGS. sistor T5, the gate electrode of the driving transistor T_dr 45 5A and 5B, no additional element is required for gener- is connected to the other terminal B of the storage ca- ating the control signal of the fifth transistor T5. Accord- pacitor C, and the drain electrode of the driving transistor ingly, there is an advantage in that the OLED display T_dr is connected to the first node N1. While the driving device can become more compact. transistor T_dr is turned on, the driving transistor T_dr [0091] FIG. 6A is an equivalent circuit diagram of a controls the level of current flowing through the OLED so 50 pixel of an OLED display device according to another that the OLED emits light, as mentioned earlier. exemplary embodiment of the present disclosure. FIG. [0085] The pixel of the OLED display device according 6B is a timing chart for driving the OLED display device to the exemplary embodiment shown in FIG. 5 allows the of FIG. 6A. fifth transistor T5 to selectively apply the supply voltage [0092] Referring to FIG. 6A, the source electrode of VDD_EL to the driving transistor T_dr depending on a 55 the switching transistor T_sw is connected to a data line signal EM(n-1) applied from the emission control line of DATA, the gate electrode of the switching transistor T_sw a previous stage. is connected to a scan line, and the drain electrode of [0086] In other words, among the emission control sig- the switching transistor T_sw is connected to a terminal

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A of the storage capacitor C. 7B is a timing chart for driving the OLED display device [0093] The source electrode of the first transistor T1 is of FIG. 7A. connected to a reference voltage Vref line, the gate elec- [0103] FIG. 7A shows an exemplary embodiment in trode of the first transistor T1 is connected to an emission which a control signal CTR applied from a separate driv- control line, and the drain electrode of the first transistor 5 ing circuit is used as the control signal of the fifth transistor T1 is connected to the terminal A of the storage capacitor T5. Specifically, in the exemplary embodiment shown in C. FIG. 7A, the fifth transistor T5 is operated by the control [0094] The source electrode of the second transistor signal CTR applied from the separate driving circuit ded- T2 is connected to the other terminal B of the storage icated togenerating the controlsignal of the fifth transistor capacitor C, the gate electrode of the second transistor 10 T5, such that there is an advantage in that the control T2 is connected to the scan line, and the drain electrode signal CTR best suitable for the condition and configu- of thesecond transistor T2is connected toa firstnode N1. ration of the OLED display device can be provided. [0095] The source electrode of the third transistor T3 [0104] Accordingly, in the OLED display device ac- is connected to the first node N1, the gate electrode of cording to the exemplary embodiment shown in FIG. 7A, the third transistorT3 isconnected to the emissioncontrol 15 it is possible to apply a control signal CTR that achieves line, and the drain electrode of the third transistor T3 is the best efficiency/performance, and it is also possible connected to a second node N2. to set the initializing time interval I’ determined by the [0096] The source electrode of the fourth transistor T4 control signal CTR as desired. is connected to the second node N2, the gate electrode [0105] The driving circuit for generating the control sig- of the fourth transistor T4 is connected to the scan line, 20 nal CTR may be disposed in the gate driver 430 (see and the drain electrode of the fourth transistor T4 is con- FIG. 4), for example. It is to be understood that a control nected to the reference voltage line Vref. linefor supplying thecontrol signal CTR may be inparallel [0097] The source electrode of the fifth transistor T5 is with the scan line GL. In one embodiment, the driving connected to a supply voltage VDD_EL, the gate elec- circuit generating the control signal CTR is separate in trode of the fifth transistor T5 is connected to an emission 25 the sense that it is separate and distinct from the circuit control line of one of the previous stages, and the drain that generates the emission signals EM. The control sig- electrode of the fifth transistor T5 is connected to the nal CTR is also applied via a control line that is separate source electrode of the driving transistor T_dr. and distinct from the emission lines. As a result, the con- [0098] In the exemplary embodiment shown in FIG. 7, trol signal CTR does not serve as the emission control an emission control signal EM(n-k) at a previous stage 30 signal of any other pixels. of a shift register is applied as the control signal of the [0106] The other elements such as the transistors T1 fifth transistor T5, where k is a natural number satisfying to T5, T_sw and T_drive, the storage capacitor C and the relationship n > k > 1. the OLED are identical to those described above. [0099] Specifically, in the structure shown in FIGS. 6A, [0107] FIG. 8 includes two graphs comparing response the emission control signal EM(n-k) at a previous stage 35 characteristics of the OLED display device in the related ahead of the nth stage by k stages is received and is art with those according to an exemplary embodiment of provided as the control signal of the fifth transistor T5 the present disclosure. The top graph shows response after the scan signal Scan is activated until the emission characteristics of an OLED display device in the related control signal EM(n) is deactivated, such that the initial- art;and thebottom graph shows response characteristics izing time interval I’ can be increased. 40 of an OLED display device according to an exemplary [0100] In other words, according to the exemplary em- embodiment of the present disclosure. bodiment, the initializing time interval in which the control [0108] When the screen is changed from black to signal of the fifth transistor T5 is supplied equals to the white, the 6T1C pixel exhibits luminance efficiency of time of kH, and accordingly, the scan signal is supplied 31.1% at the first frame and luminous efficiency of 94.3% for the time of (k + 1)H in each of the pixels, as can be 45 atthe second frame. In contrast, the 7T1C pixel according seen from FIG. 6B. to the exemplary embodiment of the present disclosure [0101] It is to be understood that an additional signal exhibits almost complete luminous efficiency (99.9%) control process may be further included for supplying the even from the first frame. emission control signal EM(n - k) until the initialization of [0109] As set forth above, according to an exemplary the pixel is completed. In one embodiment, an emission 50 embodiment of the present disclosure, during the initial- control signal EM(n-k) from a previous stage of a shift izing time interval of each pixel in the OLED display de- registermay be input toa processing circuit.The process- vice, the initialization of the transistor in each pixel is car- ing circuit generates a processed signal from the emis- ried out only with the reference voltage Vref. In addition, sion control signal EM(n-k), which can then be provided response characteristics can be improved and defects to the fifth transistor T5. 55 such as afterimage effects or spots can be suppressed. [0102] FIG. 7A is an equivalent circuit diagram of a pixel of an OLED display device according to yet another exemplary embodiment of the present disclosure. FIG.

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Claims signal (EM(n)) via the emission control line, and to use a dedicated control signal (CTR) as a control 1. An organic light-emitting diode display panel (410) signal of the fifth transistor (T5) to selectively block comprising: a supply voltage (VDD_EL) from the supply voltage 5 terminal, wherein the dedicated control signal (CTR) a scan line for transmitting a scan signal (Scan), is generated by a control signal generator that is sep- and a data line for transmitting a data signal (Da- arate from a circuit that generates the emission con- ta), the scan line intersecting the data line; trol signal (EM(n)). a switching transistor (T-SW) to allow the data signal (Data) to be supplied to an output stage 10 5. The organic light-emitting diode display panel (410) in response to the scan signal (Scan); of any one of claims 1 to 4, configured to apply, via a capacitor (C) to store a voltage corresponding the control line, a control signal to the fifth transistor to the data signal (Data); (T5), and to apply the control signal continuously in a driving transistor (T_DR) to control a current an active state after the scan signal (Scan) is acti- applied to an organic light-emitting diode15 vated until the emission control signal (Em(N)) sup- (OLED) based on the voltage stored in the ca- plied via the emission control line is deactivated. pacitor (C); a first transistor (T1) connected to an emission 6. The organic light-emitting diode display panel (410) control line, a reference voltage line and a ter- of any one of claims 1 to 5, configured to apply, via minal of the capacitor (C); 20 the control line, a control signal to the fifth transistor a second transistor (T2) connected to the scan (T5), and to apply the scan signal (Scan) continu- line, another terminal of the capacitor (C) and a ously applied in an active state while the control sig- first node (N1); nal is supplied in an active state and the emission a third transistor (T3) connected to the emission control signal (EM(n)) is deactivated. control line, the first node (N1) and a second 25 node (N2); 7. The organic light-emitting diode display panel (410) a fourth transistor (T4) connected to the scan of any one of claims 1 to 6, wherein the switching line, the reference voltage line and the second transistor (T-SW), the capacitor (C), the driving tran- node (N2); and sistor (T_DR), the first transistor (T1), the second a fifth transistor (T5) connected to a control line, 30 transistor (T2), the third transistor (T3), the fourth a supply voltage terminal, and the driving tran- transistor (T4), and the fifth transistor (T5) are all sistor (T_DR). includedwithin a pixel(P) of the organic light-emitting diode display panel (410). 2. The organic light-emitting diode display panel (410) of claim 1, configured to apply an emission control 35 8. An organic light-emitting diode display device com- signal (Em(n)) via the emission control line, and to prising: use another emission control signal (Em(n-1)) as a control signal of the fifth transistor (T5) to selectively an organic light-emitting diode display panel block a supply voltage (VDD_EL) from the supply (410) according to any one of claims 1 to 7 con- voltage terminal, wherein the another emission con- 40 figured to display images; trol signal (EM(n-1)) is from an immediately previous a gate driver (430) configured to supply a scan stage of a circuit that generates the emission control signal (Scan) to the display panel (410) via the signal (EM(n)). scan line of the display panel (410); a data driver (420) configured to supply a data 3. The organic light-emitting diode display panel (410) 45 signal (Data) to the display panel (410) via the of claim 1, configured to apply an emission control data line of the display panel (410); and signal (Em(n)) via the emission control line, and to a timing controller (440) configured to control use another emission control signal (Em(n-k)) as a driving timings of the gate driver (430) and the control signal of the fifth transistor (T5) to selectively data driver (420). block a supply voltage (VDD_EL) from the supply 50 voltage terminal, wherein the another emission con- 9. The organic light-emitting diode display device of trol signal (EM(n-k)) is from a kth previous stage of claim 8, wherein the display panel (410) is a display a circuit that generates the emission control signal panel according to claim 4, and wherein the organic (EM(n)) supplied via the emission control line, light-emittingdiode display devicefurther comprises: wherein k is a natural number greater than 1. 55 a control signal generator that is separate from 4. The organic light-emitting diode display panel (410) a circuit that generates the emission control sig- of claim 1, configured to apply an emission control nal (Em(n)), the control signal generator config-

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ured to generate the dedicated control signal (CTR) is generated by a control signal generator that (CTR) and supply the dedicated control signal is separate from a circuit that generates the emission (CTR) to the fifth transistor (T5) via the control control signal (EM(n)). line, wherein the fifth transistor (T5) uses the dedi- 5 14. The method of any one of claims 11 to 13, wherein cated control signal (CTR) supplied from the the control signal is continuously applied in an active control signal generator via the control line to state after the scan signal (Scan) is activated until selectively block the supply voltage (VDD_EL) the emission control signal (EM(n)) is deactivated. from the supply voltage terminal. 10 15. The method of any one of claims 11 to 14, wherein 10. A method for driving an organic light-emitting diode the scan signal (Scan) is continuously applied in an display device comprising a switching transistor (T- active state while the control signal is supplied in an SW), a driving transistor (T_DR), a first transistor active state and the emission control signal (EM(n)) (T1), a second transistor (T2), a third transistor (T3), is deactivated. a fourth transistor (T4), a fifth transistor (T5) and a 15 capacitor (C), the method comprising:

supplying a scan signal (Scan) as well as an emission control signal (EM(n)) to turn on the switching transistor (T-SW), the driving transis- 20 tor (T_DR), the first transistor (T1), the second transistor (T2), the third transistor (T3) and the fourth transistor (T4); supplying a control signal while the emission control signal (EM(n)) is supplied to turn off the 25 fifth transistor (T5); and supplying a reference voltage (Vref) to the turned-on switching transistor (T-SW), driving transistor (T_DR), first transistor (T1), second transistor (T2), third transistor (T3), and fourth 30 transistor (T4) to initialize them while the scan signal (Scan) as well as the emission control signal (EM(n)) are supplied, wherein the turned-off fifth transistor (T5) blocks a supply voltage (VDD_EL) from being supplied 35 to the driving transistor (T_DR) while the switching transistor (T-SW), driving transistor (T_DR), first transistor (T1), second transistor (T2), third transistor (T3), and fourth transistor (T4) are initialized. 40

11. The method of claim 10, wherein another emission control signal (EM(n-1) is used as the control signal, wherein the another emission control (EM(n-1)) signal is from an immediately previous stage of a circuit 45 that generates the emission control signal (EM(n)).

12. The method of claim 10, wherein a processed signal of another emission control signal (EM(n-k)) is used as acontrol signal,and wherein theanother emission 50 control signal (EM(n-k)) is from a kth previous stage of a circuit that generates the emission control signal (EM(n)), wherein k is a natural number greater than 1. 55 13. The method of claim 10, wherein a dedicated control signal (CTR) is used as the control signal of the fifth transistor (T5), wherein the dedicated control signal

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REFERENCES CITED IN THE DESCRIPTION

This list of references cited by the applicant is for the reader’s convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

Patent documents cited in the description

• KR 1020150136459 [0001]