Technical

MOSFET power losses and how they affect power-supply effi ciency

by George Lakkas, Texas Instruments

Power-supply efficiency is a critical criterion for today’s cloud-infrastructure hardware. The efficiency of the chosen power solutions relates to system power loss and the thermal performance of integrated circuits (ICs), printed circuit boards (PCBs), and other components, which determine the power-usage effectiveness of a data centre.

This article revisits some of the basic principles zero losses, thus offering 100% efficiency. contributors in a buck converter: conduction of power supplies and then addresses how However, components are not ideal, as is losses, switching losses, and static (quiescent) – the power stage of any switching- illustrated in the following examples. losses. regulator – affect efficiency. For the An efficient switching regulator results in less MOSFETs have a finite switching time, shown in Fig. 1, power loss heat dissipation, which reduces system cost therefore, switching losses come from the and efficiency are defined by Eqs. 1 and 2. and size for elements such as heat sinks, dynamic and currents the MOSFETs fans and their assembly. In battery-operated must handle during the time it takes to turn (1) systems, less power loss means that these on or off. devices can use the same battery for a Switching losses in the inductor come from longer run time because the device pulls less (2) the core and core losses. Gate-drive losses current from the battery. are also switching losses because they In the ideal switching regulator shown in To consider the various factors that contribute are required to turn the FETs on and off. For Fig. 2, the current is zero when the switch is to efficiency, the focus of this article is on the the control circuit, the quiescent current step-down (buck) DC/DC converter topology, contributes to power loss; the faster the open and the power loss is zero, thus VIN is being chopped. When the switch is closed, which is the most popular switching-regulator comparator, the higher the bias current. For the voltage across it is zero and the power topology in today’s cloud infrastructure the feedback circuit, the , loss is also zero. An ideal switch implies systems. Fig. 3 shows the key power-loss error and comparator bias currents

Fig. 1: Typical linear regulator.

Fig. 3. Power-loss contributors in a buck switching regulator.

Fig. 2: Ideal switching regulator. Fig. 4: MOSFET conduction losses.

42 April 2016 – EngineerIT Fig. 5: MOSFET switching losses. Fig. 6: Switch MOSFET gate losses. Fig. 7: General gate losses.

Fig. 8: Total switch MOSFET losses. Fig. 9: MOSFET body- current.

contribute to power loss. Megaohm resistors Relationships for Fig. 5 to derive loss equation: frequency, QGS2 and QGD depend on the cannot be used to reduce power loss time the driver takes to charge the FET, and I E = (V × I /2) × t1, G because of the bias current into the feedback t1 DS D is the gate current. circuit. Fig. 4 shows a basic switching circuit E = (V /2 × I ) × t2, t2 DS D Switch-MOSFET gate losses can be caused and Eqn. 3 is used to calculate conduction P = 2 × (E + E ) × f , by the energy required to charge the MOSFET losses for Q1 or Q2. SW t1 t2 SW gate. That is, the Q at the gate voltage t1 = Q /I , G(TOT) GS2 G of the circuit. These are both turn-on and turn- (3) off gate losses. t2 = QGD/IG, V = Miller plateau, Most of the power is in the MOSFET gate PLAT driver. Gate-drive losses are frequency-

VTH = Gate-to-source threshold voltage, dependent and are also a function of the Note that R is the R of the selected gate capacitance of the MOSFETs. When DS(on) I = Cdv/dt, MOSFET, I is the root-mean-square (RMS) G turning the MOSFET on and off, the higher the current through the MOSFET, and that neither Q = C × V, switching frequency, the higher the gate-drive of these is a function of switching frequency. losses. This is another reason why efficiency dt = t1 or t2, and In general, a higher switching frequency and goes down as the switching frequency higher input voltage require a lower QG (gate goes up. VGS(actual) is the actual gate-to-source drive charge) to cut down the switching losses in voltage driving the MOSFET. Larger MOSFETs with lower R provide the switch MOSFET (Q1). DS(on) MOSFET switching losses are a function of lower conduction losses at the cost of higher gate capacitances, which results in For a rectifier MOSFET (Q2), low RDS(on) is most load current and the power supply’s switching higher gate-drive losses. These losses can important, but don’t ignore the gate power. frequency as shown by Eqn. 4. be significant for power-supply controllers Also, changing the MOSFET RDS(on) changes the duty cycle (D), which affects RMS currents (with external MOSFETs) at very high switching frequencies in the multiple-megahertz region. and losses elsewhere. The inductor current (4) There is no known method for calculating also affects MOSFET conduction loss. a “best” QG and RDS(on) in a given situation, The high-side MOSFET (Q1) switching losses although figure-of-merit (FOM) numbers

are evaluated first in Fig. 5 because they are where VIN = VDS (drain-to-source voltage), are typically mentioned in data sheets as I = I (drain current), f is the switching more complex. OUT D SW (FOM = RDS(on) × QG).

EngineerIT – April 2016 43 Fig. 10: Rectifier MOSFET gate driver and losses. Fig. 11: Total rectifier MOSFET losses.

For the switch MOSFET shown in losses (PCON), body-diode conduction losses Fig. 6, a lower gate charge (Q ) in (9b) G (PBD), and gate losses (PGATE). Eqn. 5 enables lower power loss and a faster There are no switching losses because of switching time; however, this contributes to the bodydiode. The body diode conducts (9c) more parasitic turn-on of the rectifier MOSFET. and the voltage across the FET is the A happy medium can be obtained in the diode voltage, which is zero. The body design to accommodate these trade-offs. diode ensures zero-voltage switching per (9d) Eqn. 7.

(5) (7)

Conduction losses are simple I2R losses There are also general gate losses as shown when the MOSFET channel conducts per in Fig. 7. The MOSFET effect on the gate- Eqn. 8. (9e) driver IC, or a pulse-width modulation (PWM) controller with an integrated gate driver, add to the power-dissipation losses. Eqn. 10 can be used to approximate the (8) body-diode power loss. As shown by Equation 6, gate-drive losses do not all occur on the MOSFET. where: (10)  R is the RDS(on) of the selected MOSFET,  I is the RMS current through the MOSFET, The final consideration in Fig. 10 is for the (6)  t is the delay between the upper DLYUpLo gate losses of the rectifier MOSFET (Q2). Gate MOSFET turning off and the lower MOSFET losses are calculated in the same manner turning on, and where: as with the switch MOSFET. Losses can be  t is the delay between the lower DLYLoUp significant because of a higher gate charge.  MOSFET turning off and the upper MOSFET PDRV is the total gate drive loss divided to calculate the driver loss, turning on. Fig. 11 shows the various contributors that affect total losses attributed to the rectifier  R is turn on of the driver, The rectifier MOSFET also has body-diode GHI MOSFET.  losses. The average body-diode current can RGLO is the turn off of the driver, be calculated during dead time.  Conclusion Replacing RGHI with RG is the loss in the gate resistor. The blue waveform in Fig. 9 shows the dead The efficiency of a synchronous step-down  Replacing RGHI with RGI is the switching FET time, which is the time between when the power converter with integrated or external loss, high-side FET turns off and the low-side FET MOSFETs can be optimised when the  (rectifier FET) turns on. We want the average Higher QG increases driver dissipation, and designer understands the parameters that current in the switching cycle. The output  affect efficiency and the specifications to Adding external RG reduces internal driver dissipation because it reduces the overall inductor (L) dictates the slope of the dotted look for in data sheets. line, I resistance path to the MOSFET gate. BD1, IBD2, IBD3. This slope is the average current through the body diode. In the absence of an ideal power converter, Fig. 8 shows the various contributors that the designer has to make trade-offs and affect total switch MOSFET losses. Eqns. 9a through 9e can be used to optimise the parameters that affect power- determine the body-diode current: supply efficiency. Now consider the rectifier (synchronous) MOSFET total and conduction losses. Power (9a) Contact Erich Nast, Avnet South Africa, loss in a rectifier MOSFET consists of conduction Tel 011 319-8600, [email protected]

44 April 2016 – EngineerIT