DOCSLIB.ORG

Hive: Fault Containment for Shared-Memory Multiprocessors

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Hive: Fault Containment for Shared-Memory Multiprocessors Hive: Fault Containment for Shared-Memory Multiprocessors John Chapin, Mendel Rosenblum, Scott Devine, Tirthankar Lahiri, Dan Teodosiu, and Anoop Gupta Computer Systems Laboratory Stanford University, Stanford CA 94305 htkp: //www-flash. skanforcl. edu Abstract In this paper we describe Hive, an operahng system designed for large-scale shared-memory multiprocessors. Hive is Reliability and scalability are major concerns when designing fundamentally different from previous monolithic and microkernel operating systems for large-scale shared-memory multiprocessors. SMP OS implementations: it IS structured as an internal distributed In this paper we describe Hive, an operating system with a novel system of independent kernels called ce/ls. This multicellular kernel architecture that addresses these issues Hive is structured kernel architecture has two main advantages: as an internal distributed system of independent kernels called ● Re[mbiltry: In SMP OS implementations, any significant cells. This improves reliabihty because a hardwme or software hardware or software fault causes the entire system to crash. fault damages only one cell rather than the whole system, and For large-scale machines this can result in an unacceptably low improves scalability because few kernel resources are shared by mean time to failure. In Hive, only the cell where the fault processes running on different cells. The Hive prototype is a occurred crashes, so only the processes using the resources of complete implementation of UNIX SVR4 and is targeted to run on that cell are affected. This is especially beneficial for compute the Stanford FLASH multiprocessor. server workloads where there are multiple independent This paper focuses on Hive’s solutlon to the following key processes. the predominant situation today. In addition, challenges: ( 1) fault containment, i.e. confining the effects of scheduled hardware maintenance and kernel software upgrades hardware or software faults to the cell where they occur, and (2) can proceed transparently to applications, one cell at a time. memory sharing among cells, which is requmed to achieve ● Scdabi/i@: SMP OS implementations are difficult to scale to application performance competitive with other multiprocessor large ma~hines because ;11 processors directly share all kernel operating systems. Fault containment in a shared-memory resources. Improving parallelism in a ‘<shared-everything” multiprocessor requmes defending each cell against erroneous architecture 1s an iterative trial-and-error process of identifying writes caused by faults in other cells. Hive prevents such damage and fixing bottlenecks. In contrast, Hive offers a systematic by using the FLASH jirewzdl, a write permission bit-vector approach to scalablhty. Few kernel resources are shared by associated with each page of memory, and by discarding processes running on different cells, so parallelism can be potentially corrupt pages when a fault is detected. Memory sharing Improved by increasing the number of cells. is provided through a unified file and virtual memory page cache However, the multicellular architecture of Hive also creates new across the cells, and through a umfied free page frame pool. implementation challenges. These include: We report early experience with the system, including the results of fault injection and performance experiments using ● Fault comirrrrwrr,’ The effects of faults must be confined to the SimOS, an accurate simulator of FLASH, The effects of faults cell in which they occur, This M difficult since a shared-memory were contained to the cell in which they occurred m all 49 tests multiprocessor allows a faulty cell to issue wild writes which where we injected fail-stop hardware faults, and in all 20 tests can corrupt the memory of other cells. where we injected kernel data corruption. The Hive prototype ● Resource sharing: Processors, memory, and other system executes test workloads on a four-processor four-cell system with resources must be shared flexibly across cell boundaries, to between 0’%. and 11YOslowdown as compared to SGI IRIX 5.2 (the preserve the execution efficiency that justifies investing in a version of UNIX on which it is based). shared-memory multiprocessor. ● Smg/e-sy.s tent image.. The cells must cooperate to present a 1 Introduction standard SMP OS interface to applications and users. In this paper, we focus on Hive’s solution to the fault containment Shared-memory multiprocessors are becoming an increasingly problem and on Its solution to a key resource sharing problem, common server platform because of their excellent performance sharing memory across cell boundaries, The solutions rely on under dynamic multlprogrammed workloads, However, the hardware as well as software mechamsms: we have designed Hive symmetric multiprocessor operating systems (SMP OS) in conjunction with the Stanford FLASH multiprocessor [ 10], commonly used for small-scale machines are difficult to scale to which has enabled us to add hardware support m a few critical the large shared-memory multiprocessors that can now be built areas. (Stanford DASH [11 ], MIT Alewife [3], Convex Exemplar [5]). Hive’s fault containment strategy has three mam components. Permission to make digitalrhard copy of part or all of this work for personal Each cell uses firewrll hardware rxovided by FLASH to defend or classroom use is granted without fee provided that copies are not made most of its memory pages against ;ild writes. Any pages writable or distributed for profit or commercial advantage, the copyright notic8, the by a failed cell are preemptively discarded when the failure is title of the publication and its date appear, and notice is given that copying is by permission of ACM, Inc. To oopy otherwise, to republish, to detected, which prevents any corrupt data from being read post on servers, or to redistribute to lists, requires prior specific permission subsequently by applications or written to disk. Finally, aggressive and/or a fee. fadure detection reduces the delay until preemptive discard occurs. Cell failures are detected initially using heuristic checks, then SIGOPS ’95 12/95 CO, USA 0 1995 ACM 0-89791 -715-419510012 ...$3.50 12 confirmed with a distributed agreement protocol that minimizes redefine fault containment to include this resource management the probability of concluding that a functioning cell has failed. requirement: Hive prowdes two types of memory sharing among cells. First, A system provides fcadtcontainment f the probability thut the file system and the virtual memory system cooperate so an application falls is proportional to the amount of processes on multiple cells can use the same memory page for resources used by that application. not to the total amount shared data. Second, the page allocation modules on different cells of resources in the system. cooperate so a free page belonging to one cell can be loaned to another cell that is under memory pressure. Either type of sharing One important consequence of choosing this as the reliability goal would cause fault containment problems on current is that large applications which use resources from the whole multiprocessors, since a hardware fault in memory or in a system receive no reliability benefits. For example, some compute processor caching the data could halt some other processor that server workloads contain parallel applications that run with as tries to access that memory FLASH makes memory sharing safe many threads as there are processors in the system. However, these by providing timeouts and checks on memory accesses. large applications have previously used checkpointing to provide The current prototype of Hive is based on and remains binary their own reliability, so we assume they can continue to do so. compatible with IRIX 5.2 (a version of UNIX SVR4 from Silicon The fault containment strategy can be used in both distributed Graphics, Inc. ). Because FLASH is not available yet, we used the systems and multiprocessors. However, the problems that arise in SlmOS hardware simulator [ 18] to develop and test Hive. Our implementing fault containment are different in the two early experiments using SimOS demonstrate that: environments. In addition to all the problems that arise in distributed systems, the shared-memory hardware of Hive can survive the halt of a processor or the failure of a range multiprocessors increases vulnerability to both hardware faults and of memory. In all of 49 experiments where we injected a fail- software faults. We describe the problems caused by each of these stop hardware fault, the effects were confined to the cell where in turn. the fault occurred. Hardware faults: Consider the architecture of the Stanford Hive can surwve kernel software faults. In all of 20 FLASH, which is a typical large-scale shared-memory experiments where we randomly corrupted internal operating multiprocessor (Figure 2.1 ). FLASH consists of multiple nodes, system data structures, the effects were confined to the cell each with a processor and its caches, a local portion of main where the fault occurred. memory, and local 1/0 devices. The nodes commumcate through a Hive can offer reasonable performance while providing fault high-speed low-latency mesh network. Cache coherence is containment. A four-cell Hive executed three test workloads provided by a coherence controller on each node. A machine like with between 0% and 1170 slowdown as compared to IRIX 5.2 this M called a CC-NUMA multiprocessor (cache-coherent with on a four-processor machine. non-uniform memory access time) since accesses to local memory These results indicate that a multicellular kernel architecture can are faster than accesses to the memory of other nodes. provide fault containment in a shared-memory multiprocessor. The In a CC-NUMA machine, an important unit of failure is the performance results are also promising, but significant further node, A node failure halts a processor and has two direct effects on work is required on resource sharing and the single-system image the memory of the machine: the portion of main memory assigned before we can make definitive conclusions about performance.
Load more

Recommended publications
  • 3Dfx Oral History Panel Gordon Campbell, Scott Sellers, Ross Q. Smith, and Gary M. Tarolli
    3dfx Oral History Panel Gordon Campbell, Scott Sellers, Ross Q. Smith, and Gary M. Tarolli Interviewed by: Shayne Hodge Recorded: July 29, 2013 Mountain View, California CHM Reference number: X6887.2013 © 2013 Computer History Museum 3dfx Oral History Panel Shayne Hodge: OK. My name is Shayne Hodge. This is July 29, 2013 at the afternoon in the Computer History Museum. We have with us today the founders of 3dfx, a graphics company from the 1990s of considerable influence. From left to right on the camera-- I'll let you guys introduce yourselves. Gary Tarolli: I'm Gary Tarolli. Scott Sellers: I'm Scott Sellers. Ross Smith: Ross Smith. Gordon Campbell: And Gordon Campbell. Hodge: And so why don't each of you take about a minute or two and describe your lives roughly up to the point where you need to say 3dfx to continue describing them. Tarolli: All right. Where do you want us to start? Hodge: Birth. Tarolli: Birth. Oh, born in New York, grew up in rural New York. Had a pretty uneventful childhood, but excelled at math and science. So I went to school for math at RPI [Rensselaer Polytechnic Institute] in Troy, New York. And there is where I met my first computer, a good old IBM mainframe that we were just talking about before [this taping], with punch cards. So I wrote my first computer program there and sort of fell in love with computer. So I became a computer scientist really. So I took all their computer science courses, went on to Caltech for VLSI engineering, which is where I met some people that influenced my career life afterwards.
    [Show full text]
  • PACKET 7 BOOKSTORE 433 Lecture 5 Dr W IBM OVERVIEW
    “PROCESSORS” and multi-processors Excerpt from Hennessey Computer Architecture book; edits by JT Wunderlich PhD Plus Dr W’s IBM Research & Development: JT Wunderlich PhD “PROCESSORS” Excerpt from Hennessey Computer Architecture book; edits by JT Wunderlich PhD Historical Perspective and Further 7.14 Reading There is a tremendous amount of history in multiprocessors; in this section we divide our discussion by both time period and architecture. We start with the SIMD SIMD=SinGle approach and the Illiac IV. We then turn to a short discussion of some other early experimental multiprocessors and progress to a discussion of some of the great Instruction, debates in parallel processing. Next we discuss the historical roots of the present multiprocessors and conclude by discussing recent advances. Multiple Data SIMD Computers: Attractive Idea, Many Attempts, No Lasting Successes The cost of a general multiprocessor is, however, very high and further design options were considered which would decrease the cost without seriously degrading the power or efficiency of the system. The options consist of recentralizing one of the three major components. Centralizing the [control unit] gives rise to the basic organization of [an] . array processor such as the Illiac IV. Bouknight, et al.[1972] The SIMD model was one of the earliest models of parallel computing, dating back to the first large-scale multiprocessor, the Illiac IV. The key idea in that multiprocessor, as in more recent SIMD multiprocessors, is to have a single instruc- tion that operates on many data items at once, using many functional units (see Figure 7.14.1). Although successful in pushing several technologies that proved useful in later projects, it failed as a computer.
    [Show full text]
  • Online Sec 6.15.Indd
    6.155.9 Historical Perspective and Further Reading Th ere is a tremendous amount of history in multiprocessors; in this section we divide our discussion by both time period and architecture. We start with the SIMD approach and the Illiac IV. We then turn to a short discussion of some other early experimental multiprocessors and progress to a discussion of some of the great debates in parallel processing. Next we discuss the historical roots of the present multiprocessors and conclude by discussing recent advances. SIMD Computers: Attractive Idea, Many Attempts, No Lasting Successes Th e cost of a general multiprocessor is, however, very high and further design options were considered which would decrease the cost without seriously degrading the power or effi ciency of the system. Th e options consist of recentralizing one of the three major components. Centralizing the [control unit] gives rise to the basic organization of [an] . array processor such as the Illiac IV. Bouknight et al. [1972] Th e SIMD model was one of the earliest models of parallel computing, dating back to the fi rst large-scale multiprocessor, the Illiac IV. Th e key idea in that multiprocessor, as in more recent SIMD multiprocessors, is to have a single instruction that operates on many data items at once, using many functional units (see Figure 6.15.1). Although successful in pushing several technologies that proved useful in later projects, it failed as a computer. Costs escalated from the $8 million estimate in 1966 to $31 million by 1972, despite construction of only a quarter of the planned multiprocessor.
    [Show full text]
  • Kingston Memory in Your System Contents
    KINGSTON MEMORY IN YOUR SYSTEM CONTENTS page Introduction 2 1 System Specific Memory 2 1.1 Kingston Technology memory and your system’s warranty 2 1.1.1 Using Kingston Technology memory means your system warranty remains valid 2 1.1.2 Letter of confirmation from the Vice President, European Sales and Marketing 3 2 Kingston Technology Memory in Specific Manufacturers’ Systems 4 2.1 Kingston Technology memory in Compaq systems 4 2.1.1 Compaq recognition 5 2.1.2 Kingston Technology memory and Compaq’s Insight Manager® 5 2.2 Kingston Technology and Hewlett Packard 5 2.2.1 Hewlett Packard’s system warranty remains valid when using Kingston memory 5 2.2.2 Kingston’s partnership with Hewlett Packard 6 2.3 Kingston Technology and Sun Systems 6 2.3.1 Sun’s system warranty remains valid when using Kingston memory 6 2.3.2 Kingston Technology is a member of the Sun Developer Connection 6 2.3.2 Kingston Technology is part of the Cobalt Developer Network 6 3 Service Partnerships 7 3.1 Kingston Technology & SGI 7 3.1.1 Licensing Agreement 7 3.1.2 Kingston Technology’s European Service Agreement with SGI 7 4 Kingston Technology Strategic Relationships 8 4.1 Kingston Technology and Toshiba 8 4.2 Kingston Technology and Dell 9 4.3 Kingston Technology and Apple 9 4.4 Kingston Technology and JEDEC 9 4.5 Kingston Technology and Intel 9 4.6 Kingston Technology and Rambus 10 4.7 Kingston Technology and Microsoft 10 5 OEM Manufacturing 11 5.1 Some details of Kingston Technology’s OEM manufacturing 11 6 Why Kingston Technology Europe Ltd? 12 1 INTRODUCTION Kingston Technology is the world’s leading manufacturer of memory products, supplying more than 2000 products for over 4000 systems.
    [Show full text]
  • Performance of Various Computers Using Standard Linear Equations Software
    ———————— CS - 89 - 85 ———————— Performance of Various Computers Using Standard Linear Equations Software Jack J. Dongarra* Electrical Engineering and Computer Science Department University of Tennessee Knoxville, TN 37996-1301 Computer Science and Mathematics Division Oak Ridge National Laboratory Oak Ridge, TN 37831 University of Manchester CS - 89 - 85 June 15, 2014 * Electronic mail address: [email protected]. An up-to-date version of this report can be found at http://www.netlib.org/benchmark/performance.ps This work was supported in part by the Applied Mathematical Sciences subprogram of the Office of Energy Research, U.S. Department of Energy, under Contract DE-AC05-96OR22464, and in part by the Science Alliance a state supported program at the University of Tennessee. 6/15/2014 2 Performance of Various Computers Using Standard Linear Equations Software Jack J. Dongarra Electrical Engineering and Computer Science Department University of Tennessee Knoxville, TN 37996-1301 Computer Science and Mathematics Division Oak Ridge National Laboratory Oak Ridge, TN 37831 University of Manchester June 15, 2014 Abstract This report compares the performance of different computer systems in solving dense systems of linear equations. The comparison involves approximately a hundred computers, ranging from the Earth Simulator to personal computers. 1. Introduction and Objectives The timing information presented here should in no way be used to judge the overall performance of a computer system. The results reflect only one problem area: solving dense systems of equations. This report provides performance information on a wide assortment of computers ranging from the home-used PC up to the most powerful supercomputers. The information has been collected over a period of time and will undergo change as new machines are added and as hardware and software systems improve.
    [Show full text]
  • Lmbench: Portable Tools for Performance Analysis
    The following paper was originally published in the Proceedings of the USENIX 1996 Annual Technical Conference San Diego, California, January 1996 lmbench: Portable Tools for Performance Analysis Larry McVoy, Silicon Graphics Carl Staelin, Hewlett-Packard Laboratories For more information about USENIX Association contact: 1. Phone: 510 528-8649 2. FAX: 510 548-5738 3. Email: [email protected] 4. WWW URL: http://www.usenix.org lmbench: Portable tools for performance analysis Larry McVoy Silicon Graphics, Inc. Carl Staelin Hewlett-Packard Laboratories Abstract of this benchmark suite obsolete or irrelevant. lmbench is a micro-benchmark suite designed to lmbench is already in widespread use at many focus attention on the basic building blocks of many sites by both end users and system designers. In some common system applications, such as databases, simu- cases, lmbench has provided the data necessary to lations, software development, and networking. In discover and correct critical performance problems almost all cases, the individual tests are the result of that might have gone unnoticed. lmbench uncovered analysis and isolation of a customer’s actual perfor- a problem in Sun’s memory management software that mance problem. These tools can be, and currently are, made all pages map to the same location in the cache, used to compare different system implementations effectively turning a 512 kilobyte (K) cache into a 4K from different vendors. In several cases, the bench- cache. marks have uncovered previously unknown bugs and lmbench measures only a system’s ability to design flaws. The results have shown a strong correla- transfer data between processor, cache, memory, net- tion between memory system performance and overall work, and disk.
    [Show full text]
  • Performance of Various Computers Using Standard Linear Equations Software
    ———————— CS - 89 - 85 ———————— Performance of Various Computers Using Standard Linear Equations Software Jack J. Dongarra* Electrical Engineering and Computer Science Department University of Tennessee Knoxville, TN 37996-1301 Computer Science and Mathematics Division Oak Ridge National Laboratory Oak Ridge, TN 37831 University of Manchester CS - 89 - 85 September 30, 2009 * Electronic mail address: [email protected]. An up-to-date version of this report can be found at http://WWW.netlib.org/benchmark/performance.ps This Work Was supported in part by the Applied Mathematical Sciences subprogram of the Office of Energy Research, U.S. Department of Energy, under Contract DE-AC05-96OR22464, and in part by the Science Alliance a state supported program at the University of Tennessee. 9/30/2009 2 Performance of Various Computers Using Standard Linear Equations Software Jack J. Dongarra Electrical Engineering and Computer Science Department University of Tennessee Knoxville, TN 37996-1301 Computer Science and MatHematics Division Oak Ridge National Laboratory Oak Ridge, TN 37831 University of Manchester September 30, 2009 Abstract This report compares the performance of different computer systems in solving dense systems of linear equations. The comparison involves approximately a hundred computers, ranging from the Earth Simulator to personal computers. 1. Introduction and Objectives The timing information presented here should in no way be used to judge the overall performance of a computer system. The results reflect only one problem area: solving dense systems of equations. This report provides performance information on a wide assortment of computers ranging from the home-used PC up to the most powerful supercomputers. The information has been collected over a period of time and will undergo change as new machines are added and as hardware and software systems improve.
    [Show full text]
  • Performance of Various Computers Using Standard Linear Equations
    CS Performance of Various Computers Using Standard Linear Equations Software Jack J Dongarra Computer Science Department UniversityofTennessee Knoxville TN and Mathematical Sciences Section Oak Ridge National Lab oratory Oak Ridge TN CS Novemb er Electronic mail address dongarracsutkedu An uptodate version of this rep ort can b e found at httpwwwnetliborgb enchmarkp erformanceps This work was supp orted in part by the Applied Mathematical Sciences subprogram of the Oce of Energy Research US Department of Energy under Contract DEACOR and in part by the Science Alliance a state supp orted program at the UniversityofTennessee Performance of Various Computers Using Standard Linear Equations Software Jack J Dongarra Computer Science Department UniversityofTennessee Knoxville TN and Mathematical Sciences Section Oak Ridge National Lab oratory Oak Ridge TN Novemb er Abstract This rep ort compares the p erformance of dierent computer systems in solving dense systems of linear equations The comparison involves approximately a hundred computers ranging from aCray YMP to scientic workstations such as the Ap ollo and Sun to IBM PCs Intro duction and Ob jectives The timing information presented here should in no way b e used to judge the overall p erformance of a computer system The results reect only one problem area solving dense systems of equations This rep ort provides p erformance information on a wide assortment of computers ranging from the homeused PC up to the most powerful sup ercomputers The information has been
    [Show full text]
  • Interconnect-Aware Coherence Protocols for Chip Multiprocessors
    Interconnect-Aware Coherence Protocols for Chip Multiprocessors Liqun Cheng, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, John B. Carter School of Computing, University of Utah flegion,naveen,karthikr,rajeev,[email protected] ∗ Abstract However, with communication emerging as a larger power and performance constraint than computation, it may be- Improvements in semiconductor technology have made come necessary to understand and leverage the properties it possible to include multiple processor cores on a single of the interconnect at a higher level. Exposing wire prop- die. Chip Multi-Processors (CMP) are an attractive choice erties to architects enables them to find creative ways to for future billion transistor architectures due to their low exploit these properties. This paper presents a number of design complexity, high clock frequency, and high through- techniques by which coherence traffic within a CMP can put. In a typical CMP architecture, the L2 cache is shared be mapped intelligently to different wire implementations by multiple cores and data coherence is maintained among with minor increases in complexity. Such an approach can private L1s. Coherence operations entail frequent commu- not only improve performance, but also reduce power dissi- nication over global on-chip wires. In future technologies, pation. communication between different L1s will have a significant In a typical CMP, the L2 cache and lower levels of the impact on overall processor performance and power con- memory hierarchy are shared by multiple cores [24, 41]. sumption. On-chip wires can be designed to have different Sharing the L2 cache allows high cache utilization and latency, bandwidth, and energy properties.
    [Show full text]
  • An Overview of Scientific Computing
    An Overview of Scienti c Computing Lloyd Fosdick Elizab eth Jessup Septemb er 28, 1995 High Performance Scienti c Computing University of Colorado at Boulder c Copyright 1995 by the HPSC Group of the University of Colorado The following are memb ers of the HPSC Group of the Department of Computer Science at the University of Colorado at Boulder: Lloyd D. Fosdick Elizab eth R. Jessup Carolyn J. C. Schauble Gitta O. Domik Overview i Contents 1 Intro duction 1 2 Large-scale scienti c problems 2 2.1.1 Computer simulation of the greenhouse e ect ::: :: 6 3 The scienti c computing environment 8 4 Workstations 14 4.1 RISC architecture : :: :: :: :: ::: :: :: :: :: ::: :: 15 4.2 The DEC 5000 workstation : :: ::: :: :: :: :: ::: :: 17 4.2.1 The MIPS R3000 and R3010 pro cessors. : :: ::: :: 18 5 Sup ercomputers 19 5.1 Parallel architectures : :: :: :: ::: :: :: :: :: ::: :: 19 5.1.1 Evaluation of an integral : ::: :: :: :: :: ::: :: 20 5.1.2 Molecular dynamics :: :: ::: :: :: :: :: ::: :: 21 5.1.3 Typ es of parallel computers :: :: :: :: :: ::: :: 22 5.2 A virtual parallel computer : :: ::: :: :: :: :: ::: :: 26 6 Further reading 27 References 28 CUBoulder : HPSC Course Notes ii Overview Trademark Notice Convex, Convex Exemplar, are trademarks of Convex Computer Corp ora- tion. Cray, Cray-1, Cray Y-MP, Cray C90, are trademarks of Cray Research, Inc. DEC, DECstation, DECstation 5000, DEC 5000/240, DEC 10000-660 AXP, DEC PXG 3D Accelerator, DEC VAX 11/780, PXG, PXGTurb o+, VAX are trademarks of Digital Equipment Corp oration. HP 9000/735 is a trademark of Hewlett-Packard Company. Intel i860, Intel iPSC/2, Intel iPSC/860, Intel Delta, Intel Paragon are trade- marks of Intel Corp oration.
    [Show full text]
  • No Slide Title
    Cap 1 Introduction Introduction What is Parallel Architecture? Why Parallel Architecture? Evolution and Convergence of Parallel Architectures IC/Unicamp Fundamental Design Issues – Adaptado dos slides da editora por Mario Côrtes Mario por editorada slides dos Adaptado pag 1 2 What is Parallel Architecture? A parallel computer is a collection of processing elements that cooperate to solve large problems fast Some broad issues: • IC/Unicamp Resource Allocation: – – how large a collection? – how powerful are the elements? – how much memory? • Data access, Communication and Synchronization – how do the elements cooperate and communicate? – how are data transmitted between processors? – what are the abstractions and primitives for cooperation? • Performance and Scalability – how does it all translate into performance? – how does it scale? (satura o crescimento ou não) Adaptado dos slides da editora por Mario Côrtes Mario por editorada slides dos Adaptado 3 1.1 Why Study Parallel Architecture? Role of a computer architect: To design and engineer the various levels of a computer system to maximize performance and programmability within limits of technology cost IC/Unicamp and . – Parallelism: • Provides alternative to faster clock for performance (limitações de tecnologia) • Applies at all levels of system design (ênfase do livro: pipeline, cache, comunicação, sincronização) • Is a fascinating perspective from which to view architecture • Is increasingly central in information processing Côrtes Mario por editorada slides dos Adaptado pag 4 4
    [Show full text]
  • High-Quality Volume Rendering Using Texture Mapping Hardware
    High-Quality Volume Rendering Using Texture Mapping Hardware Frank Dachille, Kevin Kreeger, Baoquan Chen, Ingmar Bitter and Arie Kaufman+ Center for Visual Computing (CVC)t and Department of Computer Science State University of New York at Stony Brook Stony Brook, NY 11794-4400, USA Abstract store the volume as a solid texture on the graphics hardware, then to sample the texture using planes parallel to the image Wt present a method Jor volume rendering of regular grids plane and composite them into the frame buffer using the cclhic~h takes advantage of <?D texture mapping hardware cur- blending hardware. This approach considers only ambient, rc,rhlly available on graphics workstations. Our method pro- light and quickly produces unshaded images. The images ducts accurate shadang for arbitrary and dynamically chang- could be improved by volumetric shading, which implements ing directionul lights, viewing parameters, and transfer func- a full lighting equation for each volume sample. lior~. TIlis is achieved by hardware interpolating the data Cabral et al. [3] rendered 512x512~64 volumes into a values and gradients before software classification and shad- 512 x512 window (presumably with 64 sampling planes) in rng. The method works equally well for parallel and perspec- 0.1 seconds on a four Raster Manager SGJ RealityEnginrb tive projections. We present two approaches for OUT method: Onyx with one 150MHz CPU. Cullip and Neumann [4] one which takes advantage of software ray casting optimita- also produced 512x512 images on the SGI RealityEngine Irons nnd another which takes advantage of hardware blend- (again presumably 64 sampling planes since the volume is ing (Acceleration.
    [Show full text]