Evaluating Performance of the SGI Altix 4700 Via Scientific Benchmark and Micro-Benchmarks
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3Dfx Oral History Panel Gordon Campbell, Scott Sellers, Ross Q. Smith, and Gary M. Tarolli
3dfx Oral History Panel Gordon Campbell, Scott Sellers, Ross Q. Smith, and Gary M. Tarolli Interviewed by: Shayne Hodge Recorded: July 29, 2013 Mountain View, California CHM Reference number: X6887.2013 © 2013 Computer History Museum 3dfx Oral History Panel Shayne Hodge: OK. My name is Shayne Hodge. This is July 29, 2013 at the afternoon in the Computer History Museum. We have with us today the founders of 3dfx, a graphics company from the 1990s of considerable influence. From left to right on the camera-- I'll let you guys introduce yourselves. Gary Tarolli: I'm Gary Tarolli. Scott Sellers: I'm Scott Sellers. Ross Smith: Ross Smith. Gordon Campbell: And Gordon Campbell. Hodge: And so why don't each of you take about a minute or two and describe your lives roughly up to the point where you need to say 3dfx to continue describing them. Tarolli: All right. Where do you want us to start? Hodge: Birth. Tarolli: Birth. Oh, born in New York, grew up in rural New York. Had a pretty uneventful childhood, but excelled at math and science. So I went to school for math at RPI [Rensselaer Polytechnic Institute] in Troy, New York. And there is where I met my first computer, a good old IBM mainframe that we were just talking about before [this taping], with punch cards. So I wrote my first computer program there and sort of fell in love with computer. So I became a computer scientist really. So I took all their computer science courses, went on to Caltech for VLSI engineering, which is where I met some people that influenced my career life afterwards. -
PACKET 7 BOOKSTORE 433 Lecture 5 Dr W IBM OVERVIEW
“PROCESSORS” and multi-processors Excerpt from Hennessey Computer Architecture book; edits by JT Wunderlich PhD Plus Dr W’s IBM Research & Development: JT Wunderlich PhD “PROCESSORS” Excerpt from Hennessey Computer Architecture book; edits by JT Wunderlich PhD Historical Perspective and Further 7.14 Reading There is a tremendous amount of history in multiprocessors; in this section we divide our discussion by both time period and architecture. We start with the SIMD SIMD=SinGle approach and the Illiac IV. We then turn to a short discussion of some other early experimental multiprocessors and progress to a discussion of some of the great Instruction, debates in parallel processing. Next we discuss the historical roots of the present multiprocessors and conclude by discussing recent advances. Multiple Data SIMD Computers: Attractive Idea, Many Attempts, No Lasting Successes The cost of a general multiprocessor is, however, very high and further design options were considered which would decrease the cost without seriously degrading the power or efficiency of the system. The options consist of recentralizing one of the three major components. Centralizing the [control unit] gives rise to the basic organization of [an] . array processor such as the Illiac IV. Bouknight, et al.[1972] The SIMD model was one of the earliest models of parallel computing, dating back to the first large-scale multiprocessor, the Illiac IV. The key idea in that multiprocessor, as in more recent SIMD multiprocessors, is to have a single instruc- tion that operates on many data items at once, using many functional units (see Figure 7.14.1). Although successful in pushing several technologies that proved useful in later projects, it failed as a computer. -
Documento Tecnico Sobre Sgi Altix 3000 Para Universidad Politecnica De Valencia
DOCUMENTO TECNICO SOBRE SGI ALTIX 3000 PARA UNIVERSIDAD POLITECNICA DE VALENCIA Mayo 2003 SGI Pza. Descubridor Diego de Ordás 3 Edificio Santa Engracia 120 28003 MADRID 1 de 83 INDICE Capítulo/Sección Página 1 ANEXO TÉCNICO A: DESCRIPCIÓN DE LA ARQUITECTURA EMPLEADA EN LA FAMILIA SGI ALTIX 3000....................................................4 1.1 ARQUITECTURA SGI ALTIX 3000...............................................................5 1.1.1 DISTRIBUCIÓN DE MEMORIA.............................................................5 1.1.2 LATENCIA DE ACCESO A MEMORIA..................................................5 1.1.3 COHERENCIA DE CACHÉ....................................................................5 1.1.4 TIPO DE PARALELISMO.......................................................................5 1.1.5 TOPOLOGIA...........................................................................................5 1.1.5.1 RED DE INTERCONEXIÓN ........................................................................5 2 ANEXO TÉCNICO B: EL SUPERCLUSTER SGI ALTIX 3000 ....................5 2.1 INTRODUCCIÓN ............................................................................................5 2.2 MÓDULOS O BRICKS.....................................................................................5 2.2.1 CPU BRICK ITANIUM 2 (C-BRICK) .....................................................5 2.2.1.1 PROCESADOR INTEL® ITANIUM® 2 MCKINLEY..................................5 2.2.1.2 PROCESADOR INTEL® ITANIUM® 2 MADISON. ....................................5 -
Online Sec 6.15.Indd
6.155.9 Historical Perspective and Further Reading Th ere is a tremendous amount of history in multiprocessors; in this section we divide our discussion by both time period and architecture. We start with the SIMD approach and the Illiac IV. We then turn to a short discussion of some other early experimental multiprocessors and progress to a discussion of some of the great debates in parallel processing. Next we discuss the historical roots of the present multiprocessors and conclude by discussing recent advances. SIMD Computers: Attractive Idea, Many Attempts, No Lasting Successes Th e cost of a general multiprocessor is, however, very high and further design options were considered which would decrease the cost without seriously degrading the power or effi ciency of the system. Th e options consist of recentralizing one of the three major components. Centralizing the [control unit] gives rise to the basic organization of [an] . array processor such as the Illiac IV. Bouknight et al. [1972] Th e SIMD model was one of the earliest models of parallel computing, dating back to the fi rst large-scale multiprocessor, the Illiac IV. Th e key idea in that multiprocessor, as in more recent SIMD multiprocessors, is to have a single instruction that operates on many data items at once, using many functional units (see Figure 6.15.1). Although successful in pushing several technologies that proved useful in later projects, it failed as a computer. Costs escalated from the $8 million estimate in 1966 to $31 million by 1972, despite construction of only a quarter of the planned multiprocessor. -
AVS on UNIX WORKSTATIONS INSTALLATION/ RELEASE NOTES
_________ ____ AVS on UNIX WORKSTATIONS INSTALLATION/ RELEASE NOTES ____________ Release 5.5 Final (50.86 / 50.88) November, 1999 Advanced Visual Systems Inc.________ Part Number: 330-0120-02 Rev L NOTICE This document, and the software and other products described or referenced in it, are con®dential and proprietary products of Advanced Visual Systems Inc. or its licensors. They are provided under, and are subject to, the terms and conditions of a written license agreement between Advanced Visual Systems and its customer, and may not be transferred, disclosed or otherwise provided to third parties, unless oth- erwise permitted by that agreement. NO REPRESENTATION OR OTHER AFFIRMATION OF FACT CONTAINED IN THIS DOCUMENT, INCLUDING WITHOUT LIMITATION STATEMENTS REGARDING CAPACITY, PERFORMANCE, OR SUI- TABILITY FOR USE OF SOFTWARE DESCRIBED HEREIN, SHALL BE DEEMED TO BE A WARRANTY BY ADVANCED VISUAL SYSTEMS FOR ANY PURPOSE OR GIVE RISE TO ANY LIABILITY OF ADVANCED VISUAL SYSTEMS WHATSOEVER. ADVANCED VISUAL SYSTEMS MAKES NO WAR- RANTY OF ANY KIND IN OR WITH REGARD TO THIS DOCUMENT, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PUR- POSE. ADVANCED VISUAL SYSTEMS SHALL NOT BE RESPONSIBLE FOR ANY ERRORS THAT MAY APPEAR IN THIS DOCUMENT AND SHALL NOT BE LIABLE FOR ANY DAMAGES, INCLUDING WITHOUT LIMI- TATION INCIDENTAL, INDIRECT, SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF OR RELATED TO THIS DOCUMENT OR THE INFORMATION CONTAINED IN IT, EVEN IF ADVANCED VISUAL SYSTEMS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. The speci®cations and other information contained in this document for some purposes may not be com- plete, current or correct, and are subject to change without notice. -
Hive: Fault Containment for Shared-Memory Multiprocessors
Hive: Fault Containment for Shared-Memory Multiprocessors John Chapin, Mendel Rosenblum, Scott Devine, Tirthankar Lahiri, Dan Teodosiu, and Anoop Gupta Computer Systems Laboratory Stanford University, Stanford CA 94305 htkp: //www-flash. skanforcl. edu Abstract In this paper we describe Hive, an operahng system designed for large-scale shared-memory multiprocessors. Hive is Reliability and scalability are major concerns when designing fundamentally different from previous monolithic and microkernel operating systems for large-scale shared-memory multiprocessors. SMP OS implementations: it IS structured as an internal distributed In this paper we describe Hive, an operating system with a novel system of independent kernels called ce/ls. This multicellular kernel architecture that addresses these issues Hive is structured kernel architecture has two main advantages: as an internal distributed system of independent kernels called ● Re[mbiltry: In SMP OS implementations, any significant cells. This improves reliabihty because a hardwme or software hardware or software fault causes the entire system to crash. fault damages only one cell rather than the whole system, and For large-scale machines this can result in an unacceptably low improves scalability because few kernel resources are shared by mean time to failure. In Hive, only the cell where the fault processes running on different cells. The Hive prototype is a occurred crashes, so only the processes using the resources of complete implementation of UNIX SVR4 and is targeted to run on that cell are affected. This is especially beneficial for compute the Stanford FLASH multiprocessor. server workloads where there are multiple independent This paper focuses on Hive’s solutlon to the following key processes. -
IRIX® Admin System Configuration and Operation
IRIX® Admin System Configuration and Operation 007-2859-017 COPYRIGHT © 1992-2001 Silicon Graphics, Inc. All rights reserved; provided portions may be copyright in third parties, as indicated elsewhere herein. No permission is granted to copy, distribute, or create derivative works from the contents of this electronic documentation in any manner, in whole or in part, without the prior written permission of Silicon Graphics, Inc. LIMITED RIGHTS LEGEND The electronic (software) version of this document was developed at private expense; if acquired under an agreement with the USA government or any contractor thereto, it is acquired as "commercial computer software" subject to the provisions of its applicable license agreement, as specified in (a) 48 CFR 12.212 of the FAR; or, if acquired for Department of Defense units, (b) 48 CFR 227-7202 of the DoD FAR Supplement; or sections succeeding thereto. Contractor/manufacturer is Silicon Graphics, Inc., 1600 Amphitheatre Pkwy 2E, Mountain View, CA 94043-1351. TRADEMARKS AND ATTRIBUTIONS Challenge, Indigo, IRIS, IRIX, Octane, and Onyx are registered trademarks and SGI, Crimson, Indigo2, IRIS FailSafe, IRIS InSight, IRIS WorkSpace, IRIX Networker, NUMAlink, Origin, Performance Co-Pilot, Power Challenge, Power Indigo2, Power Onyx, the SGI logo, and XFS are trademarks of Silicon Graphics, Inc. Indy is a registered trademark, used under license in the United States and owned by Silicon Graphics, Inc., in other countries worldwide. Centronics is a trademark of Centronics Data Computer Corporation. Cray is a registered trademark of Cray, Inc. Documenter’s Workbench is a trademark of Novell, Inc. FrameMaker, Illustrator, and PostScript are trademarks of Adobe Systems, Incorporated. -
MANUAL Polyrate 2016-2A
MANUAL Polyrate 2016-2A Jingjing Zheng, Junwei Lucas Bao, Rubén Meana-Pañeda, Shuxia Zhang, Benjamin J. Lynch, José C. Corchado, Yao-Yuan Chuang, Patton L. Fast, Wei-Ping Hu, Yi-Ping Liu, Gillian C. Lynch, Kiet A. Nguyen, Charles F. Jackels, Antonio Fernandez Ramos, Benjamin A. Ellingson, Vasilios S. Melissas, Jordi Villà, Ivan Rossi, Elena. L. Coitiño, Jingzhi Pu, Titus V. Albu Department of Chemistry Chemical Theory Center, and Supercomputing Institute University of Minnesota, Minneapolis, Minnesota 55455 Artur Ratkiewicz Institute of Chemistry University of Bialystok, Poland Rozeanne Steckler Northwest Alliance for Computational Science & Engineering Oregon State University, Corvallis, Oregon 97331 Bruce C. Garrett Environmental Molecular Sciences Laboratory Pacific Northwest National Laboratory, Richland, Washington 99352 Alan D. Isaacson Department of Chemistry and Biochemistry Miami University, Oxford, Ohio 45056 and Donald G. Truhlar Department of Chemistry, Chemical Theory Center, and Supercomputing Institute University of Minnesota, Minneapolis, Minnesota 55455 Program version: 2016-2A Program version date: Nov. 29, 2016 Manual version date: Nov. 29, 2016 Copyright 1989 – 2016 Executive summary: Polyrate is a computer program for the calculation of chemical reaction rates of polyatomic species (and also atoms and diatoms as special cases) by variational transition state theory (VTST); conventional transition state theory is also supported. Bimolecular and unimolecular reactions and gas-phase, solid-state, and gas-solid-interface reactions are all included. Polyrate can perform variational transition state theory (VTST) calculations on reactions with both tight and loose transition states. For tight transition states it uses reaction-path (RP) variational transition state theory of Garret and Truhlar, and for loose transition states it uses variable-reaction-coordinate (VRC) variational transition state theory of Georgievskii and Klippenstein. -
Kingston Memory in Your System Contents
KINGSTON MEMORY IN YOUR SYSTEM CONTENTS page Introduction 2 1 System Specific Memory 2 1.1 Kingston Technology memory and your system’s warranty 2 1.1.1 Using Kingston Technology memory means your system warranty remains valid 2 1.1.2 Letter of confirmation from the Vice President, European Sales and Marketing 3 2 Kingston Technology Memory in Specific Manufacturers’ Systems 4 2.1 Kingston Technology memory in Compaq systems 4 2.1.1 Compaq recognition 5 2.1.2 Kingston Technology memory and Compaq’s Insight Manager® 5 2.2 Kingston Technology and Hewlett Packard 5 2.2.1 Hewlett Packard’s system warranty remains valid when using Kingston memory 5 2.2.2 Kingston’s partnership with Hewlett Packard 6 2.3 Kingston Technology and Sun Systems 6 2.3.1 Sun’s system warranty remains valid when using Kingston memory 6 2.3.2 Kingston Technology is a member of the Sun Developer Connection 6 2.3.2 Kingston Technology is part of the Cobalt Developer Network 6 3 Service Partnerships 7 3.1 Kingston Technology & SGI 7 3.1.1 Licensing Agreement 7 3.1.2 Kingston Technology’s European Service Agreement with SGI 7 4 Kingston Technology Strategic Relationships 8 4.1 Kingston Technology and Toshiba 8 4.2 Kingston Technology and Dell 9 4.3 Kingston Technology and Apple 9 4.4 Kingston Technology and JEDEC 9 4.5 Kingston Technology and Intel 9 4.6 Kingston Technology and Rambus 10 4.7 Kingston Technology and Microsoft 10 5 OEM Manufacturing 11 5.1 Some details of Kingston Technology’s OEM manufacturing 11 6 Why Kingston Technology Europe Ltd? 12 1 INTRODUCTION Kingston Technology is the world’s leading manufacturer of memory products, supplying more than 2000 products for over 4000 systems. -
IRIX® Admin: System Configuration and Operation
IRIX® Admin: System Configuration and Operation 007-2859-021 COPYRIGHT © 1992-2003 Silicon Graphics, Inc. All rights reserved; provided portions may be copyright in third parties, as indicated elsewhere herein. No permission is granted to copy, distribute, or create derivative works from the contents of this electronic documentation in any manner, in whole or in part, without the prior written permission of Silicon Graphics, Inc. LIMITED RIGHTS LEGEND The electronic (software) version of this document was developed at private expense; if acquired under an agreement with the USA government or any contractor thereto, it is acquired as "commercial computer software" subject to the provisions of its applicable license agreement, as specified in (a) 48 CFR 12.212 of the FAR; or, if acquired for Department of Defense units, (b) 48 CFR 227-7202 of the DoD FAR Supplement; or sections succeeding thereto. Contractor/manufacturer is Silicon Graphics, Inc., 1600 Amphitheatre Pkwy 2E, Mountain View, CA 94043-1351. TRADEMARKS AND ATTRIBUTIONS Silicon Graphics, SGI, the SGI logo, Challenge, Indigo, IRIS, IRIX, Octane, Onyx, and Origin are registered trademarks and Crimson, Indigo2, IRIS FailSafe, IRIS InSight, IRIS WorkSpace, IRIX Networker, NUMAlink, Performance Co-Pilot, Power Challenge, Power Indigo2, Power Onyx, and XFS are trademarks of Silicon Graphics, Inc., in the United States and/or other countries worldwide. Indy is a registered trademark, used under license in the United States and owned by Silicon Graphics, Inc., in other countries worldwide. Centronics is a trademark of GENICOM, L.L. C. Cray is a registered trademark of Cray, Inc. Documenter’s Workbench is a trademark of Novell, Inc. -
Chapter 2 - Graphics Programming with JOGL
Chapter 2 - Graphics Programming with JOGL • Graphics Software: Classification and History • JOGL Hello World Program • 2D Coordinate Systems in JOGL • Dealing with Window Reshaping • 3D Coordinate Systems in JOGL LMU München – Medieninformatik – Heinrich Hussmann – Computergrafik 1 – SS2012 – Kapitel 2 1 Software Using Graphics • Graphics is always finally rendered by hardware: – Monitor, projector, head-mounted display, (2D/3D) printer, plotter, vehicle … • Special-purpose software packages: – Dedicated to a special application area – Based on general graphics software as lower layers – User may need high geometrical skills in some cases, but principles of graphics programming are hidden from user – Examples: CAD software, architectural software, medical software • General-purpose graphics software: – Typically libraries or frameworks to be used for construction of other software – Defines a “computer graphics application programming interface” (CG API) – Exist on various abstraction levels – Can be bound to various programming languages (mostly used: C++) LMU München – Medieninformatik – Heinrich Hussmann – Computergrafik 1 – SS2012 – Kapitel 2 2 Low-Level and High-Level CG APIs • Low-Level APIs – Provide functionality for constructing and rendering (3D) graphical views – Abstracts away from concrete graphics hardware (existence and size of buffers, hardware support for certain functionality) – Targets at hardware-supported execution – Dominant examples: OpenGL (open standard), Direct3D (Microsoft) • High-Level APIs – Provide further -
Performance of Various Computers Using Standard Linear Equations Software
———————— CS - 89 - 85 ———————— Performance of Various Computers Using Standard Linear Equations Software Jack J. Dongarra* Electrical Engineering and Computer Science Department University of Tennessee Knoxville, TN 37996-1301 Computer Science and Mathematics Division Oak Ridge National Laboratory Oak Ridge, TN 37831 University of Manchester CS - 89 - 85 June 15, 2014 * Electronic mail address: [email protected]. An up-to-date version of this report can be found at http://www.netlib.org/benchmark/performance.ps This work was supported in part by the Applied Mathematical Sciences subprogram of the Office of Energy Research, U.S. Department of Energy, under Contract DE-AC05-96OR22464, and in part by the Science Alliance a state supported program at the University of Tennessee. 6/15/2014 2 Performance of Various Computers Using Standard Linear Equations Software Jack J. Dongarra Electrical Engineering and Computer Science Department University of Tennessee Knoxville, TN 37996-1301 Computer Science and Mathematics Division Oak Ridge National Laboratory Oak Ridge, TN 37831 University of Manchester June 15, 2014 Abstract This report compares the performance of different computer systems in solving dense systems of linear equations. The comparison involves approximately a hundred computers, ranging from the Earth Simulator to personal computers. 1. Introduction and Objectives The timing information presented here should in no way be used to judge the overall performance of a computer system. The results reflect only one problem area: solving dense systems of equations. This report provides performance information on a wide assortment of computers ranging from the home-used PC up to the most powerful supercomputers. The information has been collected over a period of time and will undergo change as new machines are added and as hardware and software systems improve.