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TPS65094 PMIC for Intel™ Apollo Lake Platform

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TPS65094 PMIC for Intel™ Apollo Lake Platform Product Order Technical Tools & Support & Folder Now Documents Software Community TPS65094 SWCS133D –SEPTEMBER 2015–REVISED MAY 2019 TPS65094 PMIC for Intel™ Apollo Lake Platform 1 Device Overview 1.1 Features 1 • Wide VIN range from 5.6 V to 21 V BUCK5 (V1P24A) for typical applications • Three variable-output voltage synchronous • Three LDO regulators with adjustable output Step-down controllers With D-CAP2™ Topology voltage – 5 A for BUCK1 (VNN), 7 A for BUCK6 (VDDQ), – LDOA1: I2C-Selectable output voltage from 1.35 and 21 A for BUCK2 (VCCGI) using external V to 3.3 V for up to 200 mA of output current FETs for typical applications – LDOA2 and LDOA3: I2C-Selectable output – I2C Dynamic Voltage Scaling (DVS) control voltage from 0.7 V to 1.5 V for up to 600 mA of (0.5 V to 1.45 V in 10-mV Steps) for BUCK1 and Output Current BUCK2 • VTT LDO for DDR memory termination – OTP-Programmable default output voltage for • Three load switches with slew rate control BUCK6 (VDDQ) – Up to 400 mA of output current with voltage • Three variable-output voltage synchronous drop less than 1.5% of nominal input voltage Step-down converters with dcs-control topology – R < 96 mΩ at input voltage of 1.8 V 2 DSON and I C DVS capabilities • I2C Interface (device address 0x5E) supports: – VIN range from 4.5 V to 5.5 V – Standard mode (100 kHz) – 3 A of output current for BUCK3 (VCCRAM) – Fast mode (400 kHz) – 2 A of output current for BUCK4 (V1P8A) and – Fast mode plus (1 MHz) 1.2 Applications • 2-, 3-, or 4-Series cell li-ion battery-powered • Tablets, Ultrabook™, and notebook computers products (NVDC or Non-NVDC) • Mobile PCs and mobile internet devices • Wall-powered designs, particularly from 12-V supply 1.3 Description The TPS65094 device is a single-chip solution, power-management integrated chip (PMIC) designed specifically for the latest Intel™ processors targeted for tablets, ultrabooks, notebooks, industrial PCs, and Internet-of-Things (IOT) applications using 2S, 3S, or 4S Li-Ion battery packs (NVDC or non-NVDC power architectures), as well as wall-powered applications. The TPS65094 device is used for essential systems with low-voltage rails merged for the smallest footprint and lowest-cost system-power solution. The TPS65094 device provides the complete power solution based on the Intel Reference Designs. Six highly efficient step-down voltage regulators (VRs), a sink or source LDO (VTT), and a load switch are controlled by power-up sequence logic to provide the proper power rails, sequencing, and protection—including DDR3 and DDR4 memory power. The two regulators (BUCK1 and BUCK2) support dynamic voltage scaling (DVS) for maximum efficiency—including support for Connected Standby. The high-frequency VRs use small inductors and capacitors to achieve a small solution size. An I2C interface allows simple control by an embedded controller (EC) or by a system on chip (SoC). The PMIC comes in an 8-mm × 8-mm single-row VQFN package with a thermal pad for good thermal dissipation and ease of board routing. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TPS65094 VQFN (64) 8.00 mm × 8.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS65094 SWCS133D –SEPTEMBER 2015–REVISED MAY 2019 www.ti.com 1.4 Functional Block Diagram Optional(a) Required(b) LDO5V VSYS EC BOOT1 LDOA1 LDOA1 DRVH1 PMICEN 1.35 V to 3.3 V BUCK1 (b) DRV5V_2_A1 1.8 V DRV5V_1_6 Default: 1V SLP_S3B SW1 200 mA VSET VNN Typical SLP_S4B DRVL1 EN Application EN SLP_S0B Usage: FBVOUT1 Control 0.5 V to 1.45 V (a) LDOLS_EN Inputs (DVS) (b) PGNDSNS1 SWA1_EN 5 A ILIM1 THERMTRIPB V1P8A VSYS BOOT2 CLK DRVH2 2 I C CTRL BUCK2 SoC DATA SW2 Default: 0V VCCGI VSET V1P8A DRVL2 EN Typical Control Application FBVOUT2 Outputs Usage: IRQB 0.5 V to 1.45 V PGNDSNS2 (DVS) PCH_PWROK 21 A FBGND2 Internal RSMRSTB Interrupt ILIM2 Events PROCHOT BUCK5V PVIN3 GPO TEST CTRL VSET LX3 INTERRUPT_CNTL BUCK3 VCCRAM OTP EN Default: 1.05 V FB3 3 A REGISTERS <PGND_BUCK3> BUCK5V PVIN4 VSYS VSYS Digital Core VSET BUCK4 LX4 V5ANA Default: 1.8 V V1P8A EN BUCK5V 2 A FB4 LDO5 LDO5V <PGND_BUCK4> nPUC LDO3P3 REFSYS BUCK5V VREF PVIN5 VSET BUCK5 LX5 V1P24A Default: 1.24 V EN FB5 2 A <PGND_BUCK5> AGND VSYS Thermal monitoring BOOT6 Thermal shutdown DRVH6 SW6 BUCK6 VSET VDDQ Default: OTP DRVL6 EN Dependent 7 A FBVOUT6 PGNDSNS6 ILIM6 PVINVTT VTT_LDO VTT EN VTT ½ × VDDQ VTTFB ILIM set by OTP EN EN EN EN EN VSET VSET LDOA2 LDOA3 LOAD SWA1 LOAD SWB1 LOAD SWB2 0.7 V to 1.5 V 0.7 V to 1.5 V 300 mA 400 mA 400 mA 600 mA 600 mA LDOA2 LDOA3 PVINSWA1 SWA1 SWB1 SWB2 PVINLDOA2_A3 PVINSWB1_B2 V1P8A(1) (2) Dashed connections optional. 0.5 V to 3.3 V 0.5 V to 3.3 V Refer to Pin Attributes for connection if unused. (2) (1) LPDDR3 and LPDDR4 (1) (2) DDR3L SWA1 V1P8U (a) LDOA1 1ot —Always 2n“ SWB1_2 (b) LDOA1 —Always 2n“ 0.5 V to 3.3 V Copyright © 2016, Texas Instruments Incorporated Figure 1-1. PMIC Functional Block Diagram 2 Device Overview Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65094 TPS65094 www.ti.com SWCS133D –SEPTEMBER 2015–REVISED MAY 2019 Table of Contents 1 Device Overview ......................................... 1 5.14 Timing Requirements ............................... 25 1.1 Features .............................................. 1 5.15 Switching Characteristics ........................... 26 1.2 Applications........................................... 1 5.16 Typical Characteristics .............................. 27 1.3 Description............................................ 1 6 Detailed Description ................................... 28 1.4 Functional Block Diagram ............................ 2 6.1 Overview ............................................ 28 2 Revision History ......................................... 3 6.2 Functional Block Diagram........................... 29 3 Device Options ........................................... 5 6.3 Feature Description ................................. 31 3.1 OTP Comparison ..................................... 5 6.4 Device Functional Modes ........................... 48 4 Pin Configuration and Functions..................... 6 6.5 Programming ........................................ 48 5 Specifications ........................................... 10 6.6 Register Maps ....................................... 52 5.1 Absolute Maximum Ratings ......................... 10 7 Application and Implementation .................... 72 5.2 ESD Ratings ........................................ 10 7.1 Application Information.............................. 72 5.3 Recommended Operating Conditions............... 11 7.2 Typical Application .................................. 72 5.4 Thermal Information................................. 11 7.3 Specific Application for TPS650944 ................ 81 5.5 Electrical Characteristics: Total Current 7.4 Do's and Don'ts ..................................... 82 Consumption ........................................ 11 8 Power Supply Recommendations .................. 82 5.6 Electrical Characteristics: Reference and Monitoring 9 Layout .................................................... 83 System .............................................. 12 9.1 Layout Guidelines ................................... 83 5.7 Electrical Characteristics: Buck Controllers ......... 13 9.2 Layout Example 83 5.8 Electrical Characteristics: Synchronous Buck ..................................... Converters........................................... 17 10 Device and Documentation Support ............... 84 5.9 Electrical Characteristics: LDOs .................... 20 10.1 Device Support ..................................... 84 5.10 Electrical Characteristics: Load Switches ........... 24 10.2 Documentation Support ............................. 84 5.11 Digital Signals: I2C Interface ........................ 25 10.3 Receiving Notification of Documentation Updates .. 84 5.12 Digital Input Signals (LDOLS_EN, SWA1_EN, 10.4 Community Resources .............................. 84 THERMTRIPB, PMICEN, SLP_S3B, SLP_S4B, 10.5 Trademarks.......................................... 84 SLP_S0B) ........................................... 25 10.6 Electrostatic Discharge Caution..................... 84 5.13 Digital Output Signals (IRQB, RSMRSTB, 10.7 Glossary 84 PCH_PWROK, PROCHOT)......................... 25 ............................................. 2 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (May 2019) to Revision D Page • Added "TPS650947" column to Summary of TPS65094x OTP Differences table ........................................... 5 • Changed TPS650945 DEVICEID register to "Dh" and TPS650944 DEVICEID register to "Ch" in Summary of TPS65094x OTP Differences table................................................................................................. 5 • Added TPS650947 settings to Section 6.6 ...................................................................................... 52 Changes from Revision B (February 2017) to Revision C Page • Changed TPS65094x to TPS65094 in title ........................................................................................ 1 • Deleted variants from top of each page ..........................................................................................
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