Pll Based Frequency Synthesizer Implemented

Vol.97(3) September 2006 SOUTH AFRICAN INSTITUTE OF ELECTRICAL ENGINEERS 237

PLL BASED FREQUENCY SYNTHESIZER PLLIMPLEMENTED BASED FREQUENCY WITH SYNTHESIZERAN ACTIVE INDUCTOR IMPLEMENTED WITH ANOSCILLATOR ACTIVE INDUCTOR OSCILLATOR.

S. Sinha and M. du Plessis

Department of Electrical, Electronic & Computer Engineering, Carl and Emily Fuchs Institute for Microelectronics (CEFIM), University of Pretoria, Pretoria, South Africa, 0002

Abstract: High costs, bulkiness, and larger power consumption makes transceiver integration and miniaturization a desired option to discretely implemented transceivers. Furthermore, a frequency synthesizer forms an important part of high-frequency transceivers. In this paper, the design of a fully-integrated dual loop frequency synthesizer is detailed. Previously, frequency synthesizers have already been implemented using CMOS technology. The synthesizer discussed in this paper deploys a dual loop architecture with a high-frequency LC voltage controlled oscillator (VCO) forming part of one of the loops. As opposed to previous architectures, the synthesizer discussed in this paper utilises an active-inductor LC VCO as opposed to a passive-inductor LC VCO deployed in earlier synthesizer implementations. Amongst others, an important advantage of this implementation is the higher quality, Q-factor of the active inductor at the trade-off of increased noise and power dissipation.

The synthesizer generates signals in the microwave frequency (2.4-2.5 GHz) range with a 1 MHz resolution. Using the 0.35 µm BiCMOS process, simulations showed a phase noise of –117 dBc/Hz at an offset of 1 MHz and reference sidebands at -80 dBc, both these parameters with respect to a 2.45 GHz carrier.

Key words: Phase locked loop (PLL), voltage controlled oscillator (VCO), single sideband (SSB) mixer, active inductor VCO.

1. INTRODUCTION achieving the design with an active inductor implementation. To meet the growing demand for wireless communication, 2. DESIGN SPECIFICATIONS it is worthy to implement some transceivers monolithically with the help of improving large-scale integration (LSI) In RF transceivers, a frequency synthesizer generates the technology. CMOS technology is normally preferred periodic signals required for both up- and down- because of the prospect to offer the cheapest solution. The conversion. Some of the main design specifications and synthesizer discussed in this paper is designed for the considerations [3] are as follows. BiCMOS process: widely regarded as a key enabler for smaller, higher-performance, power-efficient 2.1 Output frequency range and resolution communications products. This enabled the deign to deploy double and even quadruple circuit-switching speeds while The frequency synthesizer generates signals with still retaining the cost and integration benefits of frequencies in the 2.4-2.5 GHz range. Due to the close conventional silicon technology. separation between channels in developing wireless communication systems as well as tight PLL architectural One of the major engineering challenges for a single-chip trade-offs, a frequency resolution of at least 1 MHz was transceiver is the design of an on-chip low-noise frequency chosen. synthesizer. Due to close separation between the channels in wireless communication systems, RF synthesizers 2.2 Phase noise employed in wireless transceivers have rigorous frequency specifications and have restrictive phase noise prerequisites For an ideal oscillating source, a sharp impulse is to reduce the effect of other blocking signals as discussed in anticipated in the frequency domain. However, due to [1]. However, for this paper, while the specification of random waverings in the oscillator, (expressed as phase phase noise was considered, an important aim was also on noise), the spectrum demonstrates “skirts” around the

carrier. As discussed in [1], [3], finite phase noise corrupts 3.1 Simplest topology: Single loop Integer-N PLL both the up- and down-converted signals. Furthermore, there may also be large interferers in nearby channels, This topology consists of a simple PLL with an integer-N which may be near the coveted signal. Mixing of the programmable divider in feedback. desired signal and the interferer with non-ideal LO output, the tail of the interferer corrupts the down-converted signal 3.2 Improvment: the fractional-N topology band of concern and deteriorates the signal-to-noise ratio (SNR) (the effect is termed “reciprocal mixing”). On the In fractional-N synthesizers, the divider architecture is transmitter side, large-power signals with significant phase changed to obtain frequency change by a fraction of the noise can taint weak nearby signals. reference frequency. Hence, the tradeoff in the PLL synthesizer with an integer divider does not apply to As shown in [4], smaller Q obtained from on-chip passive fractional-N synthesis. The change allows a larger loop inductors is one of the main reasons that degenerates phase bandwidth compared to that in the integer-N topology under noise. The implementation of this paper with an active similar channel spacing [1]. Thus, increasing the locking inductor results in a higher Q with a voltage tuning range of speed of the synthesizer and providing more suppression of more than 15 % relative to the frequency of operation. the VCO output phase noise near the carrier. The drawback is the existence of large fractional spurs at the output and 2.3 Spurious frequencies location of spurs vary with the division ratio. Methods such as noise shaping by S-' modulation for spur reduction have Furthermore, spurious frequencies, which are non-ideal been proposed [1], however these somewhat complicates constituents in the output spectrum, are also returned. These the design. have a particularly troublesome effect [3] in the receive path, this is as the down-converted interferer may possibly 3.3 Improvment: the dual-loop topology fall in the wanted channel. Typical systems require that all sidebands be approximately 70 to 80 dB below the main Utilizing two or more loops can change the relationship carrier, bringing in an additional trade-off between between the channel spacing and reference frequency of sideband suppression and the switching speed in PLL integer-N synthesizers as discussed in [4]. Just like any two topologies. elements, two loops, may be combined in either series or parallel. The loops are combined by means of a SSB mixer. 2.4 Switching time SSB mixers are usually nonlinear and exhibit large spurs on its output. As proposed in [1], if the SSB mixer is placed The output frequency may be ascertained via a look-up channel table set by a pseudorandom number generator as within one of the loops rather than on the output of the two in an application using a scheme such as frequency hopping loops, the desired synthesized signal quality can be spread spectrum (FHSS). A finite time is needed to set up substantially improved. The synthesizer focused in this the output frequency; this should be such that the other paper uses the earlier proposal, despite that the loop needs a transceiver subsystems need not have to “wait” for the longer settling time, as spurs reduction on the mixer is of a synthesized signal. The switching time varies from one greater advantage. configuration to another, the dual PLL topology selected (§ 3), shows improvement in switching time when likened to Further, as in [1], placing a prescaler (÷ X) (like in fig. 1), traditional single loop integer-N PLL topology. Initial helps to reduce the spurs resulting from the reference design switching time of less than 1 ms was aimed. source of the lower PLL. Each divide-by-2 counter can provide 6 dB reduction of phase noise of its output carrier 3. CONCEPT DESIGNS comparing to its input, and thus the selected value of X = 4, provides approximately 12 dB reduction of phase noise to Previously synthesizers were implemented using direct the lower loop output signal. Fig. 1 also shows a complete techniques such as the direct digital synthesizer (DDS) or frequency planning of the system with certain important the direct analog synthesizer (DAS). However, these subsystem (detailed in § 4) specifications indicated. designs often require numerous components and therefore not suitable for integrated transceivers. This is one the main The resulting synthesized frequency can be calculated as in reasons why the PLL (indirect synthesizer) became the (1). This is simply derived by using the result from the preferred architecture for frequency synthesis. Within this simple integer-N synthesizer topology. architecture several topologies have been developed. Vol.97(3) September 2006 SOUTH AFRICAN INSTITUTE OF ELECTRICAL ENGINEERS 239

ffref22 ref ffout offset M NfM ref 1 1 4.1 Phase frequency detector (PFD) X X PLL performance characteristics may vary depending on the type of phase detector (PD) used. As discussed in [4], To verify the mathematical feasibility of the design, several types exist, for high-speed performance dual D flip- MATLAB was used. The complete modelling was done on flop PD is preferred. The PFD contains a charge pump as SIMULINK for simplicity. Fig. 2 shows the frequency an integral part of the device. domain output obtained for a set value on the programmable divider. 4.2 Fixed frequency dividers (÷ N and ÷ X)

PFD 1 VCO1 Based on the frequency and the amplitude of the input fo fref1 LPF signals, different types of single-ended or differential I Q [144 MHz] structures for frequency dividers can be chosen. The divide- by-4 X-prescaler is implemented using the same ÷ N [100, 200] MHz configuration as the y4 block within the divide-by-16 N = 16 I Q N-prescaler. ÷ X X = 4 The Master-slave configuration is a basic Johnson counter. PFD2 I Q fref2 It is implemented as the first stage of the divider as it can VCO2 LPF operate with much higher frequencies than source coupled [1 MHz] logic (SCL) dividers. A full speed SCL latch is used to ÷ M implement the y2 stage. M [400, 800] 4.3 Programmable counter Modulus selection The counter employs the conventional design [3], which Figure 1. Concept design and frequency planning of the consists of a dual-modulus prescaler (DMP), a pulse (P) synthesizer and a swallow (S) counter. At initial reset state, the 30 prescaler divides by (N + 1) until the swallow counter overflows, changing the modulus control signal. The 25 prescaler then divides by N until the pulse counter reaches P counts. The total counting number M is given by (2). 20 M PNS. 2 15

10 4.4 SSB mixer

5 In the upper-loop, a SSB mixer is needed to obtain the desired sideband for the high frequency prescaler output. Several methods are proposed to design a mixer [4]. The simplest method of achieving SSB is to implement a double 0 2 4 6 side band (DSB) mixer using a Gilbert cell implementation. Frequency (GHz) Thereafter, one of the bands can be filtered to obtain the Figure 2. Spectrum obtained from simulation of the desired frequency component. However, the DSB-filter mathematical (SIMULINK) model configuration is not always practical as the frequency components in this design, viz. (f1 - f2) and (f1 + f2) are way 4. SUBSYSTEMS too close, thence a very sharp filter would be required, which would mean many more resistor and capacitor The synthesizer was designed by realizing each subsystem components. For the synthesizer discussed in this paper, an at a time. Appropriate input and output loading is used to alternative implementation was done. An I/Q modulator account for possible loading effects anticipated in the configuration, shown in fig. 3, was used to achieve the subsystem integration stage of the design. In the next few required sideband. The I/Q modulator requires both in- and sections each of the subsystems is discussed. quadrature- phases at its inputs, this poses additional design challenges on the two VCOs, which will be required to 240 SOUTH AFRICAN INSTITUTE OF ELECTRICAL ENGINEERS Vol.97(3) September 2006

generate these phases. The DSB units are still implemented Another advantage of using this topology is that feed- using Gilbert cells. Depending on whether the output of the forward paths through the gate-drain capacitances of the DSB units is being summed or differenced, either the upper input differential pairs cancel each other out (i.e. CGD = 0) side band (USB) or lower side band (LSB) may be thus eliminating the effect of high-frequency phase shifts obtained. caused by the RHP (Right Hand Plane) zeros, [13]. The resonant frequency is obtained from equation (4). I v o(t) SSB Q 1 DSB f0 (4) 2S LC I Q

Figure 3. Block diagram of the SSB mixer The active inductor topology of figure 5 which uses the gyrator configuration of figure 4 is implemented to achieve 4.5 VCO : Active inductor (LC) oscillator higher frequencies of operation with multi-band 1 capabilities. This is possible due to the fact that the In order to achieve the phase noise specification for the inductance can be tuned using the tail currents Iga and Igb, a relation directly related to equations (3) and (4) synthesizer, the high frequency oscillator should have a very good phase noise performance. As indicated in fig. 1, VDD the tuning range is not too wide; hence a good quality LC P1a P2a P1b P2b oscillator suffices. The quality factor, Q , of the LC 0 oscillator is basically dictated by the type of inductor used [3]. For comparison, [11] shows the implementation of the N3a N4a N3b N4b LC oscillator using a passive inductor. Ina Inb Vout1 Vout2 N1a N2a N1b N2b

The active inductor has been developed using a differential Iga Igb gyrator topology. 0 0 2 gm(V1V )2 C s V2 V1 L

+ Figure 5. A fully balanced floating active inductor with - + - - + + - gm gm gm gm negative-resistance loads, [12] - + + + + - 0 - -

-V1 To complete the tank, a variable capacitor is also required. g2 (V1V )2 -V2 m Several methods exist to implement a varactor [3], the PN CLs junction varactor was used in this synthesizer for simplicity. It consists of a P+ and N+ region residing in an N-well. The Figure 4. The figure shows a fully differential floating + gyrator, [12] depletion region is formed between the P region and the N-well. The tuning range provided by a PN junction varactor varies with the doping profile. The PN junction Assuming that the configuration is symmetrical, g = g = m1 m2 varactor provides a r10% tuning range. Figure 6 provides g , it is shown in [12] that a resultant inductance is obtained m some typical simulation results with the proposed active as given below: inductor above.

V CC Coupled LC oscillators provide good performance in terms L LL (3) of phase noise, signal amplitude, power consumption, and 2 Iggmm12u gm quadrature output signals [7]. However, IQ amplitude and phase mismatches in these oscillators can be quite large due to the serious mismatch problem of large area inductors and The motivation behind the use of the differential gyrator varactors. A simple design modification (by tying the topology of figure 4 is that it transforms the intrinsic source nodes of the coupling transistors of the two capacitances to inductive behaviours as is shown in oscillators together) of the coupled LC oscillators shows a equation (3) and it offers common mode operation and even significant improvement on the amplitude and phase harmonic rejection (which will be shown later on in the mismatches [8]. obtained simulations). Vol.97(3) September 2006 SOUTH AFRICAN INSTITUTE OF ELECTRICAL ENGINEERS 241

(1.20G, 1.97) (100.00M, -26.48) dx=1.10G dy=28.44 v(vid1,vid2) 10 Fundamental frequency (1.20 GHz, 1.97 dBVrms) ° ° 0 45 45 Vin2+ Vin2+

-10 Vin1+ Vin1+ out1 Vo-

-20 45° Vb cont 45° ° -30 180 out2 Vo+ Vin1- Vin1-

-40 Vin2- Vin2-

-50 Voltage (dBVrms)

-60 Figure 7. Block diagram of a conventional four-stage ring -70 oscillator

0 5 10 15 20 25 30 35 40 45 50

Frequency (GHz)

Figure 6. Simulated frequency response of the VCO implemented with an ideal inductor

4.6 VCO2: Ring oscillator

The requirements of the lower-loop oscillator are having the centre frequency of 600 MHz and a tuning range around 400 MHz with tuning voltage ranging from 0 to 3.3 V. The phase noise should be smaller than –110 dBc/Hz at 1 MHz offset from the carrier. In order to obtain such a large tuning range, a ring oscillator is used instead of a LC tank oscillator, which has a typical frequency-tuning range limited to around 10-20 % [1]. The feasibility of low noise Frequency (Hz) CMOS ring oscillator that can be comparable with the performance of monolithic LC oscillators has been proven Figure 8. Simulation result obtained by doing a dc voltage [9]. In this section, the design of a ring oscillator using parametric sweep on the ring oscillator circuit negative delay path with normal delay path to achieve low phase noise performance is accomplished [10]. The delay 4.7 Loop filter cell is designed to have large tuning ability and to achieve constant phase noise as well as constant output signal A passive implementation is used as it suffices the basic amplitude throughout the tuning range. filtering purpose and also saves power.

The oscillator is similar to the conventional four-stage ring 5. SIMULATION oscillator (shown in fig. 7) with the exception of a negative delay path. Negative skewed delay path is employed with Simulation results of the complete synthesizer are shown in the normal delay path to obtain higher frequency operation Table II.. and enhance the tuning range [1]. TABLE II In a conventional differential ring oscillator, the oscillation SYNTHESIZER SIMULATION RESULTS frequency is bounded by the number of delay cells and the Specification Theory/aim Achieved unit delay time of a delay cell. The oscillation frequency Freq. range 2.4 – 2.5 GHz 2.4 – 2.5 GHz can be approximated as 1/(2NW) [1], where N is the number Resolution at least 1 MHz 1 MHz of stages and Wis the delay of the unit delay cell. To Phase noise increase the operation frequency, the negative skewed delay (offset of 1 MHz) < -80 dBc/Hz # -117 dBc/Hz path is used. With the negative skewed delay path, Sidebands about -60 dBc -60 dBc according to [10], the operation frequency of the oscillator # Switching time < 1ms 30 µs is almost double the value of 1/(2NW). Simulation results, as # shown in fig. 8 confirm this result. Power supply 3.3 V, < 60 mA 3.3 V, # 30 mA Technology Austria Microsystems (AMS) 0.35 µm 242 SOUTH AFRICAN INSTITUTE OF ELECTRICAL ENGINEERS Vol.97(3) September 2006

6. CONCLUSION [6] Craninckx, J. and Steyaert, M.S.J., “A fully integrated CMOS DCS-1800 Frequency synthesizer,” IEEE A fully differential ﬂ oating active inductor was used to Journal of Solid-State circuits, vol. 33, pp. 2054 - design a dual loop synthesizer. At a tuning voltage of 2065, 1988. 2.8 V, 4.9 mA of dc current is drawn from a 3.3 V power [7] Rofougaran, A., Rael, J., Rofougaran, M. and Abidi A., supply, resulting in a phase noise of -117 dBc/Hz at 1000 “A 900 MHz CMOS LC Oscillator with Quadrature kHz offset from the carrier while dissipating 13.72 mW of Outputs,” in 1996 ISSCC Digest of technical papers, power. At 2.8 V tuning voltage, a VCO quality factor Q pp. 392 - 393. of 36.75 at a frequency of 2.4 GHz is achieved. The dual [8] Luong, H.C. and Lo, C.W., “2-V 900-MHz Quadrature (series) loop architecture was used to obtain more optimal Coupled LC Oscillators with Improved Amplitude trade-off among phase noise, channel spacing, reference and Phase Matchings,” in Proc. 1999 ISCAS Conf., frequency and settling time compared to the conventional pp. 585 - 588. integer-N PLL architectures. [9] Park, C. H. and Kim, B., “A Low-Noise 900 MHz VCO in 0.6 µm CMOS,” 1999 IEEE Journal of Solid 7. REFERENCES State Circuits, pp. 586 - 591. [1] Kan, K.K., “A 2-V 1.8-GHz fully-integrated CMOS [10] Lee, S.J., Kim, B. and Lee, K., “A Novel High-Speed frequency synthesizer for DCS-1800 wireless Ring Oscillator for Multiphase Clock Generation systems,” thesis for the Degree of Master of Using Negative Skewed Delay Scheme,” 1997 IEEE Philosophy, Department of Electrical and Electronic Journal of Solid State Circuits, pp. 289 - 291. Engineering, The Hong Kong University of Science [11] Sinha, S. and du Plessis, M., “Design of a dual loop and Technology (HKUST), Hong Kong, 1999. frequency synthesizer,” in Proc. Africon 2004, pp. [2] Fogler, H.S. and LeBlanc, S.E., Strategies for creative 525-529. problem solving, 1st ed., New Jersey: Prentice-Hall, [12] Henri, M., 2003. Design of an integrated high- 1995, pp. 18 - 30. frequency active inductor VCO. (Final report for [3] Razavi, B., “Challenges in the design of frequency Project EPR 400). Pretoria: Department of Electrical, synthesizers for wireless applications,” in Proc. 1997 Electronic and Computer Engineering, University of IEEE Custom Integrated Circuit Conference (CICC), Pretoria. pp. 395 - 402. [13] Khorramabadi, H. and Grey, P., 1984. High-frequency [4] Smith, J.R., “Modern communication circuits,” 2nd CMOS continuous-time ﬁ lters. IEEE journal of solid- ed., New York: McGraw-Hill, 1998, pp. 436 - 442. state Circuits, vol. 19, no. 6, pp.939-948. [5] Kythakyapuzha, S.R., “Modeling of spiral inductors and transformers,” thesis for the Degree of Master of Science, Department of Electrical and Computer Engineering, Kansas State University, Kansas, 2001.