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Pll Based Frequency Synthesizer Implemented Vol.97(3) September 2006 SOUTH AFRICAN INSTITUTE OF ELECTRICAL ENGINEERS 237 PLL BASED FREQUENCY SYNTHESIZER PLLIMPLEMENTED BASED FREQUENCY WITH SYNTHESIZERAN ACTIVE INDUCTORIMPLEMENTED WITH ANOSCILLATOR ACTIVE INDUCTOR OSCILLATOR. S. Sinha and M. du Plessis Department of Electrical, Electronic & Computer Engineering, Carl and Emily Fuchs Institute for Microelectronics (CEFIM), University of Pretoria, Pretoria, South Africa, 0002 Abstract: High costs, bulkiness, and larger power consumption makes transceiver integration and miniaturization a desired option to discretely implemented transceivers. Furthermore, a frequency synthesizer forms an important part of high-frequency transceivers. In this paper, the design of a fully-integrated dual loop frequency synthesizer is detailed. Previously, frequency synthesizers have already been implemented using CMOS technology. The synthesizer discussed in this paper deploys a dual loop architecture with a high-frequency LC voltage controlled oscillator (VCO) forming part of one of the loops. As opposed to previous architectures, the synthesizer discussed in this paper utilises an active-inductor LC VCO as opposed to a passive-inductor LC VCO deployed in earlier synthesizer implementations. Amongst others, an important advantage of this implementation is the higher quality, Q-factor of the active inductor at the trade-off of increased noise and power dissipation. The synthesizer generates signals in the microwave frequency (2.4-2.5 GHz) range with a 1 MHz resolution. Using the 0.35 µm BiCMOS process, simulations showed a phase noise of –117 dBc/Hz at an offset of 1 MHz and reference sidebands at -80 dBc, both these parameters with respect to a 2.45 GHz carrier. Key words: Phase locked loop (PLL), voltage controlled oscillator (VCO), single sideband (SSB) mixer, active inductor VCO. 1. INTRODUCTION achieving the design with an active inductor implementation. To meet the growing demand for wireless communication, 2. DESIGN SPECIFICATIONS it is worthy to implement some transceivers monolithically with the help of improving large-scale integration (LSI) In RF transceivers, a frequency synthesizer generates the technology. CMOS technology is normally preferred periodic signals required for both up- and down- because of the prospect to offer the cheapest solution. The conversion. Some of the main design specifications and synthesizer discussed in this paper is designed for the considerations [3] are as follows. BiCMOS process: widely regarded as a key enabler for smaller, higher-performance, power-efficient 2.1 Output frequency range and resolution communications products. This enabled the deign to deploy double and even quadruple circuit-switching speeds while The frequency synthesizer generates signals with still retaining the cost and integration benefits of frequencies in the 2.4-2.5 GHz range. Due to the close conventional silicon technology. separation between channels in developing wireless communication systems as well as tight PLL architectural One of the major engineering challenges for a single-chip trade-offs, a frequency resolution of at least 1 MHz was transceiver is the design of an on-chip low-noise frequency chosen. synthesizer. Due to close separation between the channels in wireless communication systems, RF synthesizers 2.2 Phase noise employed in wireless transceivers have rigorous frequency specifications and have restrictive phase noise prerequisites For an ideal oscillating source, a sharp impulse is to reduce the effect of other blocking signals as discussed in anticipated in the frequency domain. However, due to [1]. However, for this paper, while the specification of random waverings in the oscillator, (expressed as phase phase noise was considered, an important aim was also on noise), the spectrum demonstrates “skirts” around the “Copyright © 2004 IEEE”:“This paper was rst published in AFRICON ’04, 15-17 September 2004, Gabarone, Botswana.” 238 SOUTH AFRICAN INSTITUTE OF ELECTRICAL ENGINEERS Vol.97(3) September 2006 carrier. As discussed in [1], [3], finite phase noise corrupts 3.1 Simplest topology: Single loop Integer-N PLL both the up- and down-converted signals. Furthermore, there may also be large interferers in nearby channels, This topology consists of a simple PLL with an integer-N which may be near the coveted signal. Mixing of the programmable divider in feedback. desired signal and the interferer with non-ideal LO output, the tail of the interferer corrupts the down-converted signal 3.2 Improvment: the fractional-N topology band of concern and deteriorates the signal-to-noise ratio (SNR) (the effect is termed “reciprocal mixing”). On the In fractional-N synthesizers, the divider architecture is transmitter side, large-power signals with significant phase changed to obtain frequency change by a fraction of the noise can taint weak nearby signals. reference frequency. Hence, the tradeoff in the PLL synthesizer with an integer divider does not apply to As shown in [4], smaller Q obtained from on-chip passive fractional-N synthesis. The change allows a larger loop inductors is one of the main reasons that degenerates phase bandwidth compared to that in the integer-N topology under noise. The implementation of this paper with an active similar channel spacing [1]. Thus, increasing the locking inductor results in a higher Q with a voltage tuning range of speed of the synthesizer and providing more suppression of more than 15 % relative to the frequency of operation. the VCO output phase noise near the carrier. The drawback is the existence of large fractional spurs at the output and 2.3 Spurious frequencies location of spurs vary with the division ratio. Methods such as noise shaping by S-' modulation for spur reduction have Furthermore, spurious frequencies, which are non-ideal been proposed [1], however these somewhat complicates constituents in the output spectrum, are also returned. These the design. have a particularly troublesome effect [3] in the receive path, this is as the down-converted interferer may possibly 3.3 Improvment: the dual-loop topology fall in the wanted channel. Typical systems require that all sidebands be approximately 70 to 80 dB below the main Utilizing two or more loops can change the relationship carrier, bringing in an additional trade-off between between the channel spacing and reference frequency of sideband suppression and the switching speed in PLL integer-N synthesizers as discussed in [4]. Just like any two topologies. elements, two loops, may be combined in either series or parallel. The loops are combined by means of a SSB mixer. 2.4 Switching time SSB mixers are usually nonlinear and exhibit large spurs on its output. As proposed in [1], if the SSB mixer is placed The output frequency may be ascertained via a look-up channel table set by a pseudorandom number generator as within one of the loops rather than on the output of the two in an application using a scheme such as frequency hopping loops, the desired synthesized signal quality can be spread spectrum (FHSS). A finite time is needed to set up substantially improved. The synthesizer focused in this the output frequency; this should be such that the other paper uses the earlier proposal, despite that the loop needs a transceiver subsystems need not have to “wait” for the longer settling time, as spurs reduction on the mixer is of a synthesized signal. The switching time varies from one greater advantage. configuration to another, the dual PLL topology selected (§ 3), shows improvement in switching time when likened to Further, as in [1], placing a prescaler (÷ X) (like in fig. 1), traditional single loop integer-N PLL topology. Initial helps to reduce the spurs resulting from the reference design switching time of less than 1 ms was aimed. source of the lower PLL. Each divide-by-2 counter can provide 6 dB reduction of phase noise of its output carrier 3. CONCEPT DESIGNS comparing to its input, and thus the selected value of X = 4, provides approximately 12 dB reduction of phase noise to Previously synthesizers were implemented using direct the lower loop output signal. Fig. 1 also shows a complete techniques such as the direct digital synthesizer (DDS) or frequency planning of the system with certain important the direct analog synthesizer (DAS). However, these subsystem (detailed in § 4) specifications indicated. designs often require numerous components and therefore not suitable for integrated transceivers. This is one the main The resulting synthesized frequency can be calculated as in reasons why the PLL (indirect synthesizer) became the (1). This is simply derived by using the result from the preferred architecture for frequency synthesis. Within this simple integer-N synthesizer topology. architecture several topologies have been developed. Vol.97(3) September 2006 SOUTH AFRICAN INSTITUTE OF ELECTRICAL ENGINEERS 239 ffref22 ref ffout offset M NfM ref 1 1 4.1 Phase frequency detector (PFD) X X PLL performance characteristics may vary depending on the type of phase detector (PD) used. As discussed in [4], To verify the mathematical feasibility of the design, several types exist, for high-speed performance dual D flip- MATLAB was used. The complete modelling was done on flop PD is preferred. The PFD contains a charge pump as SIMULINK for simplicity. Fig. 2 shows the frequency an integral part of the device. domain output obtained for a set value on the programmable divider. 4.2 Fixed frequency dividers (÷ N and ÷ X) PFD 1 VCO1 Based on the frequency and the amplitude of the input fo fref1 LPF signals, different types of single-ended or differential I Q [144 MHz] structures for frequency dividers can be chosen. The divide- by-4 X-prescaler is implemented using the same ÷ N [100, 200] MHz configuration as the y4 block within the divide-by-16 N = 16 I Q N-prescaler. ÷ X X = 4 The Master-slave configuration is a basic Johnson counter. PFD2 I Q fref2 It is implemented as the first stage of the divider as it can VCO2 LPF operate with much higher frequencies than source coupled [1 MHz] logic (SCL) dividers.
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