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A Multi-Band Phase-Locked Loop Frequency Synthesizer

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A Multi-Band Phase-Locked Loop Frequency Synthesizer A MULTI-BAND PHASE-LOCKED LOOP FREQUENCY SYNTHESIZER A Thesis by SAMUEL MICHAEL PALERMO Submitted to the Office of Graduate Studies of Texas A&M University in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE August 1999 Major Subject: Electrical Engineering A MULTI-BAND PHASE-LOCKED LOOP FREQUENCY SYNTHESIZER A Thesis by SAMUEL MICHAEL PALERMO Submitted to Texas A&M University in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE Approved as to style and content by: _____________________________ _____________________________ José Pineda de Gyvez Edgar Sánchez-Sinencio (Chair of Committee) (Member) _____________________________ _____________________________ Sherif H. K. Embabi Duncan M. H. Walker (Member) (Member) _________________________ Chanan Singh (Head of Department) August 1999 Major Subject: Electrical Engineering iii ABSTRACT A Multi-Band Phase-Locked Loop Frequency Synthesizer. (August 1999) Samuel Michael Palermo, B.S., Texas A&M University Chair of Advisory Committee: Dr. José Pineda de Gyvez A phase-locked loop (PLL) frequency synthesizer suitable for multi-band transceivers is proposed. The multi-band PLL frequency synthesizer uses a switched tuning voltage- controlled oscillator (VCO) that covers a frequency range of 111 to 297MHz with a low average conversion gain of 41.71MHz/V. A key design feature of the multi-band PLL frequency synthesizer is that the VCO tuning switches are controlled only by the normal loop dynamics. No external control is needed for the synthesizer to switch to different bands of operation. The multi-band PLL frequency synthesizer is implemented in a standard 1.2µm CMOS technology using a 2.7V supply. The frequency synthesizer has a measured frequency range of 111 to 290MHz with phase noise up to –96dBc/Hz at a 50kHz carrier offset. Experimental comparisons of the multi-band PLL frequency synthesizer with a similar classic digital PLL frequency synthesizer show the multi-band synthesizer to have a 20% greater frequency range, an average 7.3dB superior phase noise performance, and similar acquisition time. iv DEDICATION This work is dedicated to my wife, Shawn. Her gracious support and countless sacrifices have allowed me to complete this great task. v ACKNOWLEDGMENTS I would like to thank my family for the support they have given over the years. Especially my wife for providing me the gift of her infinite love. My mother deserves special thanks for the endless encouragement. The support from my father is also greatly appreciated. I am extremely grateful for the contributions of all my committee members to my research. They have provided me with the tools necessary for the research through their courses and technical discussions. My advisor, Dr. José Pineda de Gyvez, deserves special acknowledgment for the support and guidance he has provided me throughout the years. I thank all of the students in the Analog and Mixed Signal Group for their friendship and technical support. I am extremely indebted to Antonio Mondragon for the CADENCE support, Fikret Dülger for the high frequency design and testing suggestions, and Ajay Kanji for the printed circuit board help. vi TABLE OF CONTENTS Page ABSTRACT................................................................................................................. iii DEDICATION ............................................................................................................. iv ACKNOWLEDGMENTS ............................................................................................. v TABLE OF CONTENTS.............................................................................................. vi LIST OF FIGURES...................................................................................................... ix LIST OF TABLES ......................................................................................................xvi INTRODUCTION......................................................................................................... 1 Phase-Locked Loops.................................................................................................1 Phase-Locked Loop Frequency Synthesizers.............................................................3 Research Objectives..................................................................................................8 PLL DESIGN THEORY ............................................................................................. 12 PLL Operation ........................................................................................................12 Frequency Synthesizer Architectures ......................................................................15 Frequency Synthesizers with Prescalers ............................................................16 Frequency Synthesizers with Dual-Modulus Prescalers .....................................17 Frequency Synthesizers with Four-Modulus Prescalers .....................................19 Fractional N-Loop Frequency Synthesis............................................................21 Linear PLL Analysis...............................................................................................23 PLL Noise Analysis ................................................................................................36 Input Phase Noise .............................................................................................37 VCO Phase Noise .............................................................................................39 Phase Detector Dead Zone ................................................................................41 Charge Pump PLLs.................................................................................................42 Charge Pump PLL Linear Analysis ...................................................................44 Stability Analysis ..............................................................................................45 Charge Pump PLL Building Blocks ........................................................................47 Phase/Frequency Detector.................................................................................47 Charge Pump ....................................................................................................50 Loop Filter........................................................................................................52 Voltage-Controlled Oscillator ...........................................................................53 Loop Divider Circuitry......................................................................................56 A General Fully Integrated PLL Design Procedure .................................................56 vii Page A MULTI-BAND PHASE-LOCKED LOOP FREQUENCY SYNTHESIZER............ 61 The Multi-Band PLL System ..................................................................................61 Multi-Band PLL Switch Control Mechanism.....................................................62 Multi-Band PLL Channel Design ......................................................................65 The Multi-Band PLL System Design Methodology.................................................74 Mathematical Design and Modeling........................................................................77 Mathematical Design Procedure........................................................................77 Mathematical Model .........................................................................................80 Behavioral Model ...................................................................................................83 Transistor Level Block Design................................................................................88 Phase/Frequency Detector.................................................................................88 Charge Pump ....................................................................................................94 Loop Filter........................................................................................................97 Switched Tuning VCO....................................................................................100 VCO Switch Control System...........................................................................113 Loop Divider...................................................................................................122 Multi-Band PLL System Simulation Results .........................................................129 Case A ............................................................................................................130 Case B ............................................................................................................132 Case C ............................................................................................................133 Case D ............................................................................................................135 Case E.............................................................................................................137 Classic Digital PLL Design and Simulation Results ..............................................138 Case A ............................................................................................................140 Case B ............................................................................................................142 Case C ............................................................................................................144
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