T1D.005 HIGH PRECISION SYNTHESIZER BASED ON MEMS PIEZORESISTIVE RESONATOR

K.L. Phan1, T. van Ansem1, C. van der Avoort1, J.T.M. van Beek1, M.J. Goossens1, S. Jose2, R.J.P. Lander3, S. Menten1, T. Naass1, J. Sistermans2, E. Stikvoort1, F. Swartjes2, K. Wortel1, and M.A.A. in 't Zandt1 1Research & Development - NXP Semiconductors, Eindhoven, the NETHERLANDS 2Operations, NXP Semiconductors, Nijmegen, the NETHERLANDS 3Research & Development - NXP Semiconductors, Leuven, BELGIUM

ABSTRACT middle of the structure. The heads of the dog-bone face In this paper, we present a detailed description of a two electrodes called the gate, over small gaps (g) of MEMS frequency synthesizer product, including the 200nm. The resonator is actuated electrostatically by a principle, processing, system architecture, and reliability combination of a DC voltage (VDC) and an AC voltage and characterization results. The synthesizer is based on a (vin) applied on the gate (Figure 1, right), which drives the MEMS piezoresistive dog-bone shaped resonator, having resonator into the extensional symmetrical a resonant frequency of 56MHz, and a Q-factor of mode shape. To sense the vibration, a DC bias current >40,000. Using a specific temperature compensation (Id) is sent though the beams via the anchors, which are algorithm, the output frequency can be kept stable within also called the source and drain terminals. Thanks to the ±20ppm over an operating temperature from -20°C to piezoresistance effect, resistance of the beams is +85°C. Jitter over a bandwidth from 12kHz to 20MHz is modulated by their strain, which results in an AC signal typically 2.96ps. The product has been proven to be voltage at the drain. manufacturable using standard industrial processes, and to input (gate) Id output be reliable against various stress and life-time tests. gap v+Vin dc e (drain) d o tr anchor c gap L le KEYWORDS e MEMS, piezoresistive resonator, frequency b e synthesizer, thin-film capping, reliability, fractional-N d o anchor tr PLL, temperature compensation, phase noise c le μ e g 10 m source (b) INTRODUCTION Figure 1: Left: SEM image of a dog-bone resonator, MEMS oscillators are considered a disruptive taken before the thin-film cap was created. During technology with the potential to replace quartz crystal resonance, the two heads of the dog-bone structure oscillators (XOs) for electronics. So far, MEMS-based vibrate laterally as shown by the arrows. Right: resonant frequency synthesizers have met all the requirements with mode-shape and electrical connections of the resonator. respect to phase noise, jitter, temperature stability, power The color map shows lateral strain during vibration. consumption, and reliability for the mainstream of 1 to 125 MHz XO segment, which covers high-volume Electrically, the resonator can be modeled as a field- applications including consumer electronics and effect transistor in the linear region (small signal model), computing [1, 2]. Unlike its peers [3, 4], NXP which has a frequency selection property [5-7]. The Semiconductors has been working on a unique oscillator transconductance gm of the resonator can be written as: concept based on piezoresistive MEMS resonators [5-7]. g g (ω) = m0 (1) This type of resonators overcomes the classical issue of m −ω 2 ω 2 + ω ω weak electro-mechanical coupling at high resonance 1 / 0 j /(Q 0 ) frequency, which is encountered in conventional ε hbKβ g = 0 I V (2) capacitive MEMS resonators. In this paper, a detailed m0 g 2 Lk d g description of NXP’s mature MEMS frequency ε synthesizer product, including the principle, processing, in which, 0 is the permittivity of vacuum, h is the system architecture, and reliability and characterization thickness of the resonator, b is the width of the heads, L is results, is presented. The product has been proven to be the length of the beams, K is the piezoresistive gauge manufacturable using standard industrial processes. factor of silicon, β is the ratio of strain in the beams to the total strain in the entire length of the resonator during PIEZORESISTIVE MEMS RESONATOR vibration, k is the stiffness of the resonator, Vg is the DC ω ω The heart of our frequency synthesizer is a MEMS bias voltage across the gaps, and 0 are the frequency dog-bone shaped resonator, having a resonant frequency of the signal and of the resonant frequency, respectively, of 55.8MHz, made in a 1.5μm-thick SOI layer (see Figure Q is the quality factor. The numerator of Eq. (1), gm0, 1, left). The dog-bone resonator consists of two describes the transconductance of the resonator symmetrical heads, connected together by four beams, irrespective of frequency, and the denominator describes which are attached to the substrate at two anchors at the the frequency selection of the resonator, which is similar

978-1-4673-5983-2/13/$31.00 ©2013 IEEE 802 Transducers 2013, Barcelona, SPAIN, 16-20 June 2013 to a RLC resonant circuit. At resonance (ω=ω0), the The complete synthesizer product contains a MEMS transconductance becomes –jgm0Q, which implies that it resonator die, stacked on an ASIC die (CMOS circuitry of has the maximum amplitude, and the resonator behaves the frequency synthesizer), overmolded inside a standard 3 like an . There is a 90° phase shift between the 4-pin SMD plastic package measuring 5×3.2×0.85mm AC output current and input voltage. Unlike its (see Figure 4), using all standard packaging processes at capacitive rival, the transconductance of the piezoresistive NXP’s back-end fabs. resonator can be “boosted” by increasing not only the bias Q-factor change voltage V , but also the bias current I , see Eq. (2), which g d -4000 -2000 0 2000 4000 results in a large output current at resonance and hence can easily be combined with an amplifier in an oscillation 99 loop. Furthermore, the output current does not depend on resonator size and makes this concept suitable for 90 realizing high frequency oscillators. 70 FABRICATION 50 The MEMS resonator is capped in vacuum using 30 NXP’s proprietary thin-film capping technology, which is a low-temperature (<400°C) and low-cost CMOS- 10 Freq. change, UHAST

Cumulative percentage Q change, UHAST compatible process. Figure 2 shows a schematic cross- Freq. change, HTSL section of a capped resonator. The process starts with 1 Q change, HTSL patterning and release etch of the MEMS resonator in a -4 -2 0 2 4 SOI wafer. Next, a sacrificial layer is deposited and Frequency change (ppm) patterned to form the vacuum cavity shape. A PECVD silicon nitride capping layer is subsequently deposited, Figure 3: Cumulative distribution of resonant frequency followed by contact and release hole etching. In the next change (in ppm) and Q-factor change of dog-bone step, the sacrificial layer is etched through the release resonators after 96hrs of UHAST (at 130°C/85%RH) and holes to form the cavity, and after that, the cavity is sealed 168hrs of HTSL (at 200°C). by depositing and patterning a plug layer at low pressure. The cap is subsequently reinforced by an extra oxide/nitride double layer. Finally contact holes are etched and metallization is made to make contact pads. The cavity under the cap can sustain <40mbar of pressure, which is enough to enable resonance of a quality factor of >40,000.

Reinforcement Plug Resonator Figure 4: Complete frequency synthesizer assembled in a layer Cap Actuation leadless 4-pin plastic package. Left: picture of a gaps Vacuum cavity decapped product, showing a stack of a MEMS resonator die glued on top of an ASIC die. Middle (and right): SOI bottom (and top) view of the product. Buried oxide Handle wafer FREQUENCY SYNTHESIZER

Figure 2: Schematic cross-section of a thin-film capped Figure 5 shows the top-level system architecture of resonator. our frequency synthesizer. Basically, the system consists of an oscillator core connected to the resonator, a charge- The thin-film cap has been proven to yield excellent pump to generate a DC voltage bias for the resonator, a robustness against various standard accelerated stress fractional-N Phase-Lock-Loop (frac-N PLL), a dedicated tests, such as Unbiased Highly Accelerated Steam Test block for temperature compensation, an output buffer, a (UHAST), High Temperature Storage Life (HTSL), digital block with an embedded memory, and a number of Temperature Cycling (TMCL), as well as the standard high-performance low-dropout regulators (LDOs). grinding, dicing and overmolding packaging process with The resonance of the MEMS resonator is maintained a peak pressure of 80bar. As examples, Figure 3 shows by the oscillator core consisting of a two-stage amplifier, results of a UHAST test (at 130°C and 85% relative which amplifies the AC voltage swing at the drain of the resonator and feeds back the amplified signal to its gate. humidity, for 96hrs) and HTSL test (at 200°C for 168hrs), ° performed on full 8-inch wafers. The resonant frequency The phase of the feed-back signal shifted by +100 , in ° change after the tests has been found to be below 2ppm, which +90 is needed for compensating the phase shift of which is within the accuracy of the measurement setup. the piezoresistive resonator and +10° is for compensating After the tests, majority (99%) of devices show parasitic capacitance coming from the resonator structure insignificant change (<7%) in the Q factor, which and bond-wires. The resonator is biased at VDC= -5V indicates that the cavity remains hermetic and outgassing (supplied by the charge pump) at the gate, and Id= 1.5mA within the cavity is not significant. from the drain to the source.

803 MEMS die ASIC die change of the resonator resistance can be included in the MEMS Charge power dissipation Pres = Id Vd. resonator LDOs pump Knowing temperature at the resonator, Tres, frequency Δ f/f from a calibration point (at which temperature of output the resonator beams is Tres0) can be calculated: (25 - 200MHz) Oscillator Frac-N Output Δf core 56 PLL buffer = C ()T −T + C ()()T 2 −T 2 + C T 3 −T 3 MHz f 1 res res0 2 res res0 3 res res0 where C are the temperature coefficients of frequency Temperature x compen- Digital Memory (TCFs) of the doped silicon used in the MEMS resonator. sation From Δf/f, the fractional divider number can be Control determined and fed to the frac-N PLL for temperature interface compensation. The compensation coefficients Axx and Cx Figure 5: System architecture of the MEMS frequency were extracted experimentally from measurements of synthesizer. averaged behaviors of many devices at different ambient temperatures and drain current values. These coefficients The output of the oscillator core is fed into the frac-N are subsequently stored in the memory of the synthesizer PLL. The frac-N PLL is a circuit that contains a Voltage and used in all parts. In this way we only need calibration Controlled Oscillator (VCO) whose frequency, after some at a single temperature, thus significantly reducing the divisions, can be locked to a reference frequency [8], final-test cost. The part-to-part variation of the frequency which is the MEMS frequency in this case. Via a number stability against temperature depends on variations of all of integer and fractional dividers, a frequency in the range components in the (thermal) system, such as temperature from 25MHz to 200MHz can be programmed and sensor accuracy, accuracy in the drain current value, generated at the output of the circuit. accuracy in the drain voltage measurement, variation in By nature, the resonant frequency of our doped the glue layer thickness (the glue between the MEMS and silicon-based resonator is temperature dependent with a ASIC dies), etc. By using the static thermal model and rate of approximately -24ppm/K at room temperature. the error propagation method with best known Without correction, the output of the frac-N PPL, being uncertainties and variations of all components, we have locked to the MEMS frequency, will also drift with estimated that the overall frequency stability would be temperature at the same rate. In our synthesizer, by ±28ppm (3-sigma), over the temperature range from - continuously adjusting the fractional divider number 20°C to +85°C. according to temperature change, temperature dependence Using a transient thermal model and experiments, it of frequency of the VCO can be electronically has been shown that only 2ms after power-on, the compensated. dynamic temperature difference between the resonator The MEMS resonator is continuously heated by a few beams and the sensor reaches the static ΔT predicted by K with respect to temperature of the ASIC die due to the algorithm. Therefore, the compensation algorithm dissipation of the drain current I . In order to provide a d should work correctly upon start-up of the complete compensation signal to the fraction-N PLL, temperature at synthesizer, which is by design at 8ms after power-on. the resonator beams (T ) is precisely calculated from the res resonator power dissipation (Pres) and temperature at the ASIC die, using a specific algorithm based on a static ELECTRICAL PERFORMANCE thermal model: Semi-automatic lab-scale tests have been performed = + Δ on over 150 parts, which revealed that 98% of the parts Tres Tsen T (3) have met functional specifications. Various quantities of in which Tsen is the temperature at the ASIC die, which is the specifications were measured at different temperature measured by an on-chip temperature sensor, ΔT is the from -20°C to +85°C, and different power supply values temperature difference between the resonator beams and (VDD) from 2.37V to 3.6V. The current consumption was the temperature sensor. Due to nonlinear temperature found to be typically 16mA at VDD=2.5V in the active dependence of thermal resistivity of the materials mode (no load condition), and <50μA in the standby Δ involved in the system, T can be expressed by a mode. Typical startup time was 8ms, regardless of VDD polynomial function of power dissipation and and temperature. temperature: A single set of optimized compensation coefficients 2 ΔT = A P + A P (4) was used in all parts, which yielded ±20ppm of frequency 1 res 2 res stability over an operating temperature range from -20°C = + + 2 + 3 ° A1 A10 A11Tsen A12Tsen A13Tsen to +85 C (see Figure 6). The worst part-to-part variation (5) ° = + + 2 + 3 of frequency deviation occurred at +85 C, which was A2 A20 A21Tsen A22Tsen A23Tsen ±8.7ppm (1-sigma), or ±26ppm (3-sigma). This result is in which Axx are functions of temperature coefficients of very close to the prediction from the thermal model thermal resistivities of the materials. The power (±28ppm 3-sigma, see the previous section). dissipation of the resonator is derived from the known A number of parts were soldered on printed circuit fixed drain current Id, and an on-chip measurement of the boards to study the effect of soldering on the frequency drain voltage Vd. In this way, any variation and life-time accuracy. Measurements before and after soldering

804 showed that soldering has no significant effect on the has been produced with high yield and proven to meet all frequency. Typically the standard deviation of frequency functional specifications. With the high frequency change is 2ppm, centered around 0ppm. stability over temperature and life-time, and low RMS 50 jitter, NXP’s frequency synthesizer has been shown to be 40 an excellent component for many clocking applications 30 such as for HDDs, Gigabit Ethernet, USB, PCI-Express 20 and S-ATA, microcontroller, CPU timing, memory, and various consumer electronics devices. 10 20 0 15 -10 10 -20 5 -30 0

Frequency deviation (ppm) -40 -5 -10 -50 -15

-20-100 1020304050607080 (ppm) drift Frequency -20 Temperature (°C) 0 200 400 600 800 1000 Figure 6: Frequency stability (in ppm, with respect to the targeted output frequency) against ambient temperature Time (hour) Figure 8: Ageing test on 30 samples at 85°C, for >1000 and VDD, measured on 110 samples, programmed at various output from 25MHz to 200MHz. hours, showing a frequency stability of <±5ppm.

Phase noise has been measured on all tested parts at REFERENCES different VDD values and temperatures. From the phase [1] A.K. Poddar and U.L. Rohde, “Latest technology, noise data, RMS jitter was calculated by integrating over technological challenges, and market trends for the frequency bandwidth of interest. An example of a frequency generating and timing devices”, IEEE phase noise plot of a product programmed to output Microwave Magazine, vol. 13 , pp. 120-134, 2012. 100MHz is shown in Figure 7. RMS jitter over an [2] J.T.M. van Beek and R. Puers, “A review of MEMS integration bandwidth from 12kHz to 20MHz and from oscillators for frequency reference and timing 1.875MHz to 20MHz is typically 2.96ps and 0.44ps, applications” J. Micromech. Microeng., vol.22, no.1 respectively. Generally RMS jitter slightly increases with 013001, (35pp), 2012. increasing temperature (typically about 14% per 100K [3] H. Lee, A. Partridge, and F. Assaderaghi, “Low jitter increase, for RMS jitter in the band 1.875MHz - 20MHz). and temperature stable MEMS oscillators”, in Proc. -60 IEEE Int. Freq. Control. Symp. 2012, pp. 266-270. [4] H. Bhugra, W. Pan, D. Lei, S. Lee, “Introducing high -80 performance crystalfree™ pMEMS oscillators”, in Proc. IEEE Int. Freq. Control. Symp. 2012, pp. 256- -100 259. [5] J.J.M. Bontemps, A. Murroni, J.T.M. van Beek, 12kHz -120 J.A.T.M. van den Homberg, J.J. Koning, G.E.J. Koops, G.J.A.M. Verheijden, J. van Wingerden, K.L. -140 1.875MHz 20MHz Phan, P. Vermeeren, C. van der Avoort, H.C.W.

Phase noise (dBc/Hz) Phase Jitter = Beijerinck, P.G.M. Baltus, “56 MHz Piezoresistive -160 0.44ps Micromechanical Oscillator”, in Digest Tech. Papers Jitter = 2.96ps Transducers‘09 Conference, Denver, June 21-25, -180 2009, pp. 1433-1436. 102 103 104 105 106 107 108 [6] J.T.M van Beek, G.J.A.M. Verheijden, G.E.J. Koops, Frequency offset (Hz) K. L. Phan, C. van der Avoort, J. van Wingerden, D. Figure 7: A typical phase-noise plot of a frequency Badaroglu Ernur, and J.J.M. Bontemps, “Scalable 1.1 synthesizer programmed to output 100MHz. GHz fundamental mode piezo-resistive silicon MEMS resonator”, IEEE Int. Electron Devices ° A standard ageing test at 85 C has been performed on Meeting, IEDM, Washington DC, December 10–12, 30 parts. In the course of over 1000h (42 days), the 2007, pp. 411-414. output frequency of the devices was observed to be stable [7] K.L. Phan; J.T.M van Beek, G.E.J Koops, within ±5ppm (Figure 8). “Piezoresistive ring-shaped MEMS resonator”, in Proc. Int. Solid-State Sensors, Actuators and CONCLUSIONS Microsystems Conf, (TRANSDUCERS) 2009, pp. NXP’s frequency synthesizer based on a MEMS 1413 – 1416. piezoresistive resonator has been described in detail. The [8] C. Barrett, “Fractional/Integer-N PLL Basics”, Texas MEMS resonator has been proven to be manufacturable Instruments Technical brief SWRA029. Available: using low-cost, low-temperature standard industrial http://www.ti.com/lit/an/swra029/swra029.pdf, Aug. processes. The complete frequency synthesizer product 1999.

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