Intel Desktop CPU Roadmap

Total Page:16

File Type:pdf, Size:1020Kb

Intel Desktop CPU Roadmap Intel Desktop CPU Roadmap 2004 2005 2008 2009 2010 System Price 2006 2007 TDP Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 1H Q2 3.73GHz Core2 Extreme Kentsfield Core2 Extreme Kentsfield QX9775 (3.2GHz/ Northwood Presler QX6850 (3GHz/ 12MB/FSB1600) QX Prescott 2M 3.2GHz(840) QX6700 (2.66GHz/ Core2 Extreme 6 cores/12MB L3 3.46GHz(955) 3.73GHz(965) 8MB/FSB1333) QX9770 (3.2GHz/ Bloomfield Extreme ≧ Extreme 3.46GHz 8MB/FSB1066) 965 (3.2GHz/8MB/ Smithfield-XE QX6800 (2.93GHz/ 12MB/FSB1600) (XE) 130W Pentium 2.93GHz(X6800) 8MB/FSB1066) Yorkfield QPI6.4/DDR3 1066) Pentium 4 3.8GHz(670) Extreme Edition QX9650 (3GHz/ Extreme Edition Conroe XE 12MB/FSB1333) Core i7 Bloomfield $900 Prescott Presler Core2 Quad Yorkfield 940 (2.93GHz/8MB/ 3.8GHz(571) 3.8GHz(672) 3.4GHz(950) 3.6GHz(960) Kentsfield Q9550 (2.83GHz/ QPI4.8/DDR3 1066) 3.8GHz(570) Lynnfield 4cores/PCIe x16 Conroe Q6600 (2.4GHz/ 12MB/FSB1333) Westmere Performance Performance 3.8GHz(670) 8MB/FSB1066) Q6700 (2.66GHz/ 2.xxGHz/8MB/ Prescott 3.6GHz(660) PCIe/DDR3 1066 6 cores (P1) Prescott 2M 3.2GHz(940) Pentium D 2.66GHz(E6700) 8MB/FSB1066) Prescott 2M Q9650 (3GHz/ 3.2GHz(840) 9xx 12MB/FSB1333) Core2 Duo Nehalem/Core 2 $4xx Smithfield Pentium D Boundary 8xx Cedar Mill Core2 Quad Q9550 (2.83GHz/ 3.6GHz(662) Conroe Yorkfield 12MB/FSB1333) 3.6GHz(560) 3.6GHz(561) 3.6GHz(661) 2.40GHz(E6600) 2.66GHz(E6700) 920 (2.66GHz/8MB/ 3.6GHz(660) Q9450 (2.66GHz/ QPI4.8/DDR3 1066) $300 Q Mainstream 3 12MB/FSB1333) Bloomfield 2.xxGHz/8MB/ Lynnfield 3.4GHz(650) Core i7 95W 3GHz(930) 3.4GHz(950) PCIe/DDR3 1066 Smithfield 3.6GHz(960) Kentsfield Mainstream3 3GHz(830) Presler Q9300 (2.5GHz/ Q9400 (2.66GHz/ (MS3) 6MB/FSB1333) 6MB/FSB1333) Prescott 2M Q6600 (2.4GHz/ Q6700 (2.66GHz/ 3.4GHz(650) 8MB/FSB1066) 8MB/FSB1066) 3.4GHz(550) 3.4GHz(551) 3.4GHz(651) 2.13GHz(E6400) 2.40GHz(E6600) E6850 (3GHz/ Dual-core/PCIe x16 Cedar Mill 3.2GHz(940) 4MB/FSB1333) E8600 (3.33GHz/ /Graphics core E8500 (3.16GHz/ 6MB/FSB1333) Mainstream 2 3.2GHz(640) 3.4GHz(950) Conroe1333MHz 6MB/FSB1333) 2.8GHz(820) Kentsfield Lynnfield Prescott 2.xxGHz/8MB/ 2.8GHz(920) 3GHz(930) Core2 Duo Q6600 (2.4GHz/ Q8300 (2.5GHz/ 3.2GHz(540) 3.2GHz(541) Wolfdale 8MB/FSB1066) 4MB/FSB1333) PCIe/DDR3 1066 3.2GHz(641) $200 3GHz(630) Conroe1333MHz E8400 (3GHz/ Pentium 4 Conroe-2M Conroe 6MB/FSB1333) Q8200 (2.33GHz/ Yorkfield Pentium 4 4MB/FSB1333) Mainstream2 5xx 1.86GHz(E6300) 2.13GHz(E6420) E6850 (3GHz/ Delayed from Q3'09. to Q1'10 (MS2) Pentium 4 6xx 2.8GHz(820) 1.86GHz(E6300) 1.86GHz(E6300) 4MB/FSB1333) 6xx 3.4GHz(945) 3.4GHz(945) E6750 (2.66GHz/ E8500 (3.16GHz/ 3GHz(531) 4MB/FSB1333) 6MB/FSB1333) 3GHz(631) Mainstream 1 Conroe-2M 3GHz(530) E8200 (2.66GHz/ E8300 (2.83GHz/ Core2 Duo 4 cores/2 cores 3.4GHz(651) 1.8GHz(E4300) 1.86GHz(E6320) 6MB/FSB1333) 6MB/FSB1333) Boundary 3GHz(630) Havendale Mainstream1 Wolfdale E8400 (3GHz/ (MS1) 3.4GHz(945) E6550 (2.33GHz/ 6MB/FSB1333) 2.8GHz(520) 2.8GHz(521) 4MB/FSB1333) Wolfdale $160 Core2 Duo Wolfdale 2.8GHz(521) Pentium D E7200 (2.53GHz/ E7500 (2.93GHz/ 3.06GHz(345) 3GHz(925) 3MB/FSB1066) 3MB/FSB1066) Essential2 3.33GHz(355) 2GHz(E4400) E4700 (2.6GHz/ (E2) Prescott-V 2MB/FSB800) Essential 3.2GHz(351) 3.06GHz(524) 2.8GHz(915) Conroe-2M E7400 (2.8GHz/ 2.4GHz(E4600) 3MB/FSB1066) 2.93GHz(340) 2.8GHz(820) 1.8GHz(E4300) Essential1 3.06GHz(346) 2.66GHz(805) E7300 (2.66GHz/ Core2 Duo (E1) Celeron D 2.2GHz(E4500) 3MB/FSB1066) Wolfdale $90 3xx Delayed from Q3'09. to Q1'10 E Cedar Mill Conroe-1M 65W 2.8GHz(335) 3.06GHz(346) 3.2GHz(541) 2.8GHz(820) 1.8GHz(E2160) E2220 (2.4GHz/ 1MB/FSB800) 2.93GHz(341) 3.33GHz(355) 2GHz(E2180) Value3 Value 3 3.46GHz(360) Wolfdale E5300 (2.6GHz/ 3GHz(531) 3.2GHz(935) (V3) 3.4GHz(65x) E2200 (2.2GHz/ E5200 (2.5GHz/ 2MB/FSB800) 2.66GHz(330) 3.33GHz(356) 1MB/FSB800) 2.8GHz(336) 3.4GHz(651) Pentium Dual-core 2MB/FSB800) Prescott-V 3.2GHz(352) Pentium 4 Pentium Dual-core $75 3.2GHz(64x) E5200 (2.5GHz/ 2.53GHz(325) 2.8GHz(336) 1.8GHz(E2160) 2MB/FSB800) 3.06GHz(524) 3.2GHz(541) 3GHz(925) Conroe-1M Wolfdale 3.2GHz(641) E2220 (2.4GHz/ Value2 Value 2 2.66GHz(331) Conroe-1M 1MB/FSB800) 3GHz(63x) E2200 (2.2GHz/ (V2) 2.4GHz(320) 3GHz(631) 3GHz(531) E2180 (2GHz/ 1MB/FSB800) 2.53GHz(326) 1.6GHz(E2140) 1MB/FSB800) $6x Celeron D Celeron Dual-core E1500 (2.2GHz/ Conroe-L Conroe-L Conroe 512KB/FSB800) 2GHz(440) E1400 (2GHz/ 3.06GHz(346) 3.2GHz(351) Cedar Mill 3.46GHz(360) Celeron 512KB/FSB800) 2 cores/1 core E1200 (1.6GHz/ 3.33GHz(356) Boundary Value1 Value 1 512KB/FSB800) (V1) 3.33GHz(355) 2.8GHz(336) 3.06GHz(346) 1.8GHz(430) 430 (1.8GHz/ 512KB/FSB800) 4xx 3.2GHz(352) Conroe-L 440? (2GHz/ Atom/Core 2 35W 512KB/FSB800) 3.2GHz(351) 1.6GHz(420) Boundary $30 NetBurst/Core 2 Integrated Board Atom Diamondville SC/DC Pineview SC/DC 2xx Boundary 330 (1.6GHz/ Integrated Board 1.33GHz(215) 1.2GHz(220) 1MB/FSB533) ? Basic 4W- 27W Yonah SC Conroe-L 230 (1.6GHz/ 512KB/FSB533) ? Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 1H Q2 System Price 2004 2005 2006 2007 2008 2009 2010 Hexa(6) Core Pentium 4 6xx (Prescott 2M) Pentium D 9xx(Presler) Core 2 Duo(Conroe) Core 2 Extreme/Quad (Kentsfield) Bloomfield Diamondville DC Quad Core Pentium 4 5xx (Prescott) Pentium D 8xx(Smithfield) Core 2 Duo(Conroe 1333) Core 2 Extreme/Quad (Yorkfield) Lynnfield Diamondville SC Dual Core Celeron D (Prescott-V) Pentium 4 (Cedar Mill) Pentium Dual-core (Conroe) Core 2 Duo(Wolfdale) Havendale Pineview DC Single Core Celeron D (Cedar Mill) Celeron (Conroe-L) Celeron Dual-core (Conroe) Pineview SC Copyright (c) 2008 Hiroshige Goto All rights reserved..
Recommended publications
  • Fujitsu Siemens Computers
    SPEC CINT2006 Result spec Copyright 2006-2014 Standard Performance Evaluation Corporation Fujitsu Siemens Computers SPECint_rate2006 = 21.4 PRIMERGY TX150 S5, Intel Pentium D processor 945, 3.40 GHz SPECint_rate_base2006 = 20.5 CPU2006 license: 22 Test date: May-2007 Test sponsor: Fujitsu Siemens Computers Hardware Availability: Sep-2006 Tested by: Fujitsu Siemens Computers Software Availability: Mar-2007 Copies 0 2.00 4.00 6.00 8.00 10.0 12.0 14.0 16.0 18.0 20.0 22.0 24.0 26.0 28.0 30.0 32.0 34.0 36.0 38.0 40.0 25.5 400.perlbench 2 2 24.1 17.8 401.bzip2 2 2 16.7 22.4 403.gcc 2 22.5 429.mcf 2 2 23.2 19.8 445.gobmk 2 2 18.7 19.5 456.hmmer 2 2 17.1 18.5 458.sjeng 2 2 17.4 19.4 462.libquantum 2 2 18.8 39.9 464.h264ref 2 2 38.3 16.7 471.omnetpp 2 2 15.7 15.5 473.astar 2 2 14.9 28.2 483.xalancbmk 2 SPECint_rate_base2006 = 20.5 SPECint_rate2006 = 21.4 Hardware Software CPU Name: Intel Pentium D 945 Operating System: 64-Bit SUSE LINUX Enterprise Server 10, Kernel CPU Characteristics: 800 MHz system bus 2.6.16.21-0.8-smp on an x86_64 CPU MHz: 3400 Compiler: Intel C++ Compiler for IA32/EM64T application, Version 9.1 - Build 20070215, Package-ID: FPU: Integrated l_cc_p_9.1.047 CPU(s) enabled: 2 cores, 1 chip, 2 cores/chip Auto Parallel: No CPU(s) orderable: 1 chip File System: ReiserFS Primary Cache: 12 K micro-ops I + 16 KB D on chip per core System State: Multiuser, Runlevel 3 Secondary Cache: 2 MB I+D on chip per core Base Pointers: 32-bit L3 Cache: None Peak Pointers: 32/64-bit Other Cache: None Other Software: Smart Heap Library, Version
    [Show full text]
  • Microcode Revision Guidance August 31, 2019 MCU Recommendations
    microcode revision guidance August 31, 2019 MCU Recommendations Section 1 – Planned microcode updates • Provides details on Intel microcode updates currently planned or available and corresponding to Intel-SA-00233 published June 18, 2019. • Changes from prior revision(s) will be highlighted in yellow. Section 2 – No planned microcode updates • Products for which Intel does not plan to release microcode updates. This includes products previously identified as such. LEGEND: Production Status: • Planned – Intel is planning on releasing a MCU at a future date. • Beta – Intel has released this production signed MCU under NDA for all customers to validate. • Production – Intel has completed all validation and is authorizing customers to use this MCU in a production environment.
    [Show full text]
  • MBP4ASG41M-VS3.Pdf
    ASRock > G41M-VS3 Página 1 de 2 Home | Global / English [Change] About ASRock Products News Support Forum Download Awards Dealer Zone Where to Buy Products G41M-VS3 Motherboard Series »G41M-VS3 Translate »Overview & Specifications ■ Supports FSB1333/1066/800/533 MHz CPUs »Download ■ Supports Dual Channel DDR3 1333(OC) ■ Intel® Graphics Media Accelerator X4500, Pixel Shader 4.0, DirectX 10, Max. shared »Manual memory 1759MB »FAQ ■ EuP Ready »CPU Support List ■ Supports ASRock XFast RAM, XFast LAN, XFast USB Technologies ■ Supports Instant Boot, Instant Flash, OC DNA, ASRock OC Tuner (Up to 158% CPU »Memory QVL frequency increase) »Beta Zone ■ Supports Intelligent Energy Saver (Up to 20% CPU Power Saving) ■ Free Bundle : CyberLink DVD Suite - OEM and Trial; Creative Sound Blaster X-Fi MB - Trial This model may not be sold worldwide. Please contact your local dealer for the availability of this model in your region. Product Specifications General - LGA 775 for Intel® Core™ 2 Extreme / Core™ 2 Quad / Core™ 2 Duo / Pentium® Dual Core / Celeron® Dual Core / Celeron, supporting Penryn Quad Core Yorkfield and Dual Core Wolfdale processors - Supports FSB1333/1066/800/533 MHz CPU - Supports Hyper-Threading Technology - Supports Untied Overclocking Technology - Supports EM64T CPU - Northbridge: Intel® G41 Chipset - Southbridge: Intel® ICH7 - Dual Channel DDR3 memory technology - 2 x DDR3 DIMM slots - Supports DDR3 1333(OC)/1066/800 non-ECC, un-buffered memory Memory - Max. capacity of system memory: 8GB* *Due to the operating system limitation, the actual memory size may be less than 4GB for the reservation for system usage under Windows® 32-bit OS. For Windows® 64-bit OS with 64-bit CPU, there is no such limitation.
    [Show full text]
  • Class-Action Lawsuit
    Case 3:20-cv-00863-SI Document 1 Filed 05/29/20 Page 1 of 279 Steve D. Larson, OSB No. 863540 Email: [email protected] Jennifer S. Wagner, OSB No. 024470 Email: [email protected] STOLL STOLL BERNE LOKTING & SHLACHTER P.C. 209 SW Oak Street, Suite 500 Portland, Oregon 97204 Telephone: (503) 227-1600 Attorneys for Plaintiffs [Additional Counsel Listed on Signature Page.] UNITED STATES DISTRICT COURT DISTRICT OF OREGON PORTLAND DIVISION BLUE PEAK HOSTING, LLC, PAMELA Case No. GREEN, TITI RICAFORT, MARGARITE SIMPSON, and MICHAEL NELSON, on behalf of CLASS ACTION ALLEGATION themselves and all others similarly situated, COMPLAINT Plaintiffs, DEMAND FOR JURY TRIAL v. INTEL CORPORATION, a Delaware corporation, Defendant. CLASS ACTION ALLEGATION COMPLAINT Case 3:20-cv-00863-SI Document 1 Filed 05/29/20 Page 2 of 279 Plaintiffs Blue Peak Hosting, LLC, Pamela Green, Titi Ricafort, Margarite Sampson, and Michael Nelson, individually and on behalf of the members of the Class defined below, allege the following against Defendant Intel Corporation (“Intel” or “the Company”), based upon personal knowledge with respect to themselves and on information and belief derived from, among other things, the investigation of counsel and review of public documents as to all other matters. INTRODUCTION 1. Despite Intel’s intentional concealment of specific design choices that it long knew rendered its central processing units (“CPUs” or “processors”) unsecure, it was only in January 2018 that it was first revealed to the public that Intel’s CPUs have significant security vulnerabilities that gave unauthorized program instructions access to protected data. 2. A CPU is the “brain” in every computer and mobile device and processes all of the essential applications, including the handling of confidential information such as passwords and encryption keys.
    [Show full text]
  • Professor Won Woo Ro, School of Electrical and Electronic Engineering Yonsei University the Intel® 4004 Microprocessor, Introdu
    Professor Won Woo Ro, School of Electrical and Electronic Engineering Yonsei University The 1st Microprocessor The Intel® 4004 microprocessor, introduced in November 1971 An electronics revolution that changed our world. There were no customer‐ programmable microprocessors on the market before the 4004. It propelled software into the limelight as a key player in the world of digital electronics design. 4004 Microprocessor Display at New Intel Museum A Japanese calculator maker (Busicom) asked to design: A set of 12 custom logic chips for a line of programmable calculators. Marcian E. "Ted" Hoff Recognized the integrated circuit technology (of the day) had advanced enough to build a single chip, general purpose computer. Federico Faggin to turn Hoff's vision into a silicon reality. (In less than one year, Faggin and his team delivered the 4004, which was introduced in November, 1971.) The world's first microprocessor application was this Busicom calculator. (sold about 100,000 calculators.) Measuring 1/8 inch wide by 1/6 inch long, consisting of 2,300 transistors, Intel’s 4004 microprocessor had as much computing power as the first electronic computer, ENIAC. 2 inch 4004 and 12 inch Core™2 Duo wafer ENIAC, built in 1946, filled 3000‐cubic‐ feet of space and contained 18,000 vacuum tubes. The 4004 microprocessor could execute 60,000 operations per second Running frequency: 108 KHz Founders wanted to name their new company Moore Noyce. However the name sounds very much similar to “more noise”. "Only the paranoid survive". Moore received a B.S. degree in Chemistry from the University of California, Berkeley in 1950 and a Ph.D.
    [Show full text]
  • Evolution of Microprocessor Performance
    EvolutionEvolution ofof MicroprocessorMicroprocessor PerformancePerformance So far we examined static & dynamic techniques to improve the performance of single-issue (scalar) pipelined CPU designs including: static & dynamic scheduling, static & dynamic branch predication. Even with these improvements, the restriction of issuing a single instruction per cycle still limits the ideal CPI = 1 Multiple Issue (CPI <1) Multi-cycle Pipelined T = I x CPI x C (single issue) Superscalar/VLIW/SMT Original (2002) Intel Predictions 1 GHz ? 15 GHz to ???? GHz IPC CPI > 10 1.1-10 0.5 - 1.1 .35 - .5 (?) Source: John P. Chen, Intel Labs We next examine the two approaches to achieve a CPI < 1 by issuing multiple instructions per cycle: 4th Edition: Chapter 2.6-2.8 (3rd Edition: Chapter 3.6, 3.7, 4.3 • Superscalar CPUs • Very Long Instruction Word (VLIW) CPUs. Single-issue Processor = Scalar Processor EECC551 - Shaaban Instructions Per Cycle (IPC) = 1/CPI EECC551 - Shaaban #1 lec # 6 Fall 2007 10-2-2007 ParallelismParallelism inin MicroprocessorMicroprocessor VLSIVLSI GenerationsGenerations Bit-level parallelism Instruction-level Thread-level (?) (TLP) 100,000,000 (ILP) Multiple micro-operations Superscalar /VLIW per cycle Simultaneous Single-issue CPI <1 u Multithreading SMT: (multi-cycle non-pipelined) Pipelined e.g. Intel’s Hyper-threading 10,000,000 CPI =1 u uuu u u Chip-Multiprocessors (CMPs) u Not Pipelined R10000 e.g IBM Power 4, 5 CPI >> 1 uuuuuuu u AMD Athlon64 X2 u uuuuu Intel Pentium D u uuuuuuuu u u 1,000,000 u uu uPentium u u uu i80386 u i80286
    [Show full text]
  • Conroe and Allendale Electrical, Mechanical, and Thermal
    Intel® Xeon® Processor 5500 Series Datasheet, Volume 1 March 2009 Document Number: 321321-001 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® Xeon® Processor 5500 Series may contain design defects or errors known as errata which may cause the product to deviate from published specifications.Current characterized errata are available on request. Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See http://www.intel.com/products/processor_number for details. Over time processor numbers will increment based on changes in clock, speed, cache, FSB, or other features, and increments are not intended to represent proportional or quantitative increases in any particular feature.
    [Show full text]
  • Multiprocessing Contents
    Multiprocessing Contents 1 Multiprocessing 1 1.1 Pre-history .............................................. 1 1.2 Key topics ............................................... 1 1.2.1 Processor symmetry ...................................... 1 1.2.2 Instruction and data streams ................................. 1 1.2.3 Processor coupling ...................................... 2 1.2.4 Multiprocessor Communication Architecture ......................... 2 1.3 Flynn’s taxonomy ........................................... 2 1.3.1 SISD multiprocessing ..................................... 2 1.3.2 SIMD multiprocessing .................................... 2 1.3.3 MISD multiprocessing .................................... 3 1.3.4 MIMD multiprocessing .................................... 3 1.4 See also ................................................ 3 1.5 References ............................................... 3 2 Computer multitasking 5 2.1 Multiprogramming .......................................... 5 2.2 Cooperative multitasking ....................................... 6 2.3 Preemptive multitasking ....................................... 6 2.4 Real time ............................................... 7 2.5 Multithreading ............................................ 7 2.6 Memory protection .......................................... 7 2.7 Memory swapping .......................................... 7 2.8 Programming ............................................. 7 2.9 See also ................................................ 8 2.10 References .............................................
    [Show full text]
  • Pentium Dual-Core Core2
    Intel Desktop CPU Roadmap 2004 2005 2008 2009 2010 2011 System Price 2006 2007 TDP Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 2H Q4 3.73GHz Core2 Extreme Kentsfield QX9775 (3.2GHz/ Northwood Presler Core2 Extreme Kentsfield 12MB/FSB1600) 6 cores/12MB L3 Prescott 2M QX6850 (3GHz/ Core2 Extreme Gulftown QX 3.2GHz(840) 3.46GHz(955) 3.73GHz(965) QX6700 (2.66GHz/ 8MB/FSB1333) Bloomfield 130W Extreme ≧ Extreme Extreme 3.46GHz 8MB/FSB1066) QX9770 (3.2GHz/ 965 (3.2GHz/8MB/ 975 (3.33GHz/8MB/ (XE) Smithfield-XE QX6800 (2.93GHz/ 12MB/FSB1600) Gulftown (XE) 130W Pentium 2.93GHz(X6800) 8MB/FSB1066) Yorkfield QPI6.4/DDR3 1066) QPI6.4/DDR3 1066) 999- Pentium 4 3.8GHz(670) Extreme Edition QX9650 (3GHz/ Extreme Edition Conroe XE 12MB/FSB1333) Core i7 4cores/PCIe x16 Nehalem/Core 2 Bloomfield $900 Prescott Gulftown Presler Core2 Quad Yorkfield Boundary 940 (2.93GHz/8MB/ 950 (3.06GHz/8MB/ 3.8GHz(571) 3.8GHz(672) 3.4GHz(950) 3.6GHz(960) Kentsfield Q9550 (2.83GHz/ QPI4.8/DDR3 1066) QPI4.8/DDR3 1066) Gulftown 3.8GHz(570) 12MB/FSB1333) Lynnfield Performance Conroe Q6600 (2.4GHz/ 130W Performance Performance 3.8GHz(670) 8MB/FSB1066) Q6700 (2.66GHz/ 2.xxGHz/8MB/ (P1) Prescott 3.6GHz(660) PCIe/DDR3 1066 (P1) Prescott 2M 3.2GHz(940) Pentium D 2.66GHz(E6700) 8MB/FSB1066) $560 Prescott 2M Q9650 (3GHz/ 3.2GHz(840) 9xx 12MB/FSB1333) Sandy Bridge 65W $4xx Smithfield Core2 Duo 4 cores/2 cores Pentium D Boundary Q9550s (2.83GHz/ 2.xxGHz/8MB/ 8xx Core2 Quad 12MB/FSB1333) PCIe/DDR3 1066 Cedar Mill Q9550 (2.83GHz/ Gulftown 3.6GHz(662) 3.6GHz(661)
    [Show full text]
  • Intel® Core™ Microarchitecture • Wrap Up
    EW N IntelIntel®® CoreCore™™ MicroarchitectureMicroarchitecture MarchMarch 8,8, 20062006 Stephen L. Smith Bob Valentine Vice President Architect Digital Enterprise Group Intel Architecture Group Agenda • Multi-core Update and New Microarchitecture Level Set • New Intel® Core™ Microarchitecture • Wrap Up 2 Intel Multi-core Roadmap – Updates since Fall IDF 3 Ramping Multi-core Everywhere 4 All products and dates are preliminary and subject to change without notice. Refresher: What is Multi-Core? Two or more independent execution cores in the same processor Specific implementations will vary over time - driven by product implementation and manufacturing efficiencies • Best mix of product architecture and volume mfg capabilities – Architecture: Shared Caches vs. Independent Caches – Mfg capabilities: volume packaging technology • Designed to deliver performance, OEM and end user experience Single die (Monolithic) based processor Multi-Chip Processor Example: 90nm Pentium® D Example: Intel Core™ Duo Example: 65nm Pentium D Processor (Smithfield) Processor (Yonah) Processor (Presler) Core0 Core1 Core0 Core1 Core0 Core1 Front Side Bus Front Side Bus Front Side Bus *Not representative of actual die photos or relative size 5 Intel® Core™ Micro-architecture *Not representative of actual die photo or relative size 6 Intel Multi-core Roadmap 7 Intel Multi-core Roadmap 8 Intel® Core™ Microarchitecture Based Platforms Platform 2006 20072007 Caneland Platform (2007) MP Servers Tigerton (QC) (2007) Bensley Platform (Q2’06)/ Glidewell Platform (Q2’06) ) DP Servers/ Woodcrest (Q3’06) DP Workstation Clovertown (QC) (Q1’07) Kaylo Platform (Q3’06)/ Wyloway Platform (Q3 ’06) UP Servers/ Conroe (Q3’06) UP Workstation Kentsfield (QC) (Q1’07) Bridge Creek Platform (Mid’06) Desktop -Home Conroe (Q3’06) Kentsfield (QC) (Q1’07) Desktop -Office Averill Platform (Mid’06) Conroe (Q3’06) Mobile Client Napa Platform (Q1’06) Merom (2H’06) All products and dates are preliminary 9 Note: only Intel® Core™ microarchitecture QC refers to Quad-Core and subject to change without notice.
    [Show full text]
  • Intel® Architecture Instruction Set Extensions and Future Features Programming Reference
    Intel® Architecture Instruction Set Extensions and Future Features Programming Reference 319433-041 OCTOBER 2020 Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. All product plans and roadmaps are subject to change without notice. The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade. Code names are used by Intel to identify products, technologies, or services that are in development and not publicly available. These are not “commercial” names and not intended to function as trademarks. Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be ob- tained by calling 1-800-548-4725, or by visiting http://www.intel.com/design/literature.htm. Copyright © 2020, Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries.
    [Show full text]
  • Nt* and Rtl* INT 2Eh CALL Ntdll!Kifastsystemcall
    ȘFĢ: Fųřțįm’ș Đěřįvǻțįvě Bỳ Jǿșěpħ Ŀǻňđřỳ ǻňđ Ųđį Șħǻmįř Țħě Ŀǻbș țěǻm ǻț ȘěňțįňěŀǾňě řěčěňțŀỳ đįșčǿvěřěđ ǻ șǿpħįșțįčǻțěđ mǻŀẅǻřě čǻmpǻįģň șpěčįfįčǻŀŀỳ țǻřģěțįňģ ǻț ŀěǻșț ǿňě Ěųřǿpěǻň ěňěřģỳ čǿmpǻňỳ. Ųpǿň đįșčǿvěřỳ, țħě țěǻm řěvěřșě ěňģįňěěřěđ țħě čǿđě ǻňđ běŀįěvěș țħǻț bǻșěđ ǿň țħě ňǻțųřě, běħǻvįǿř ǻňđ șǿpħįșțįčǻțįǿň ǿf țħě mǻŀẅǻřě ǻňđ țħě ěxțřěmě měǻșųřěș įț țǻķěș țǿ ěvǻđě đěțěčțįǿň, įț ŀįķěŀỳ pǿįňțș țǿ ǻ ňǻțįǿň-șțǻțě șpǿňșǿřěđ įňįțįǻțįvě, pǿțěňțįǻŀŀỳ ǿřįģįňǻțįňģ įň Ěǻșțěřň Ěųřǿpě. Țħě mǻŀẅǻřě įș mǿșț ŀįķěŀỳ ǻ đřǿppěř țǿǿŀ běįňģ ųșěđ țǿ ģǻįň ǻččěșș țǿ čǻřěfųŀŀỳ țǻřģěțěđ ňěțẅǿřķ ųșěřș, ẅħįčħ įș țħěň ųșěđ ěįțħěř țǿ įňțřǿđųčě țħě pǻỳŀǿǻđ, ẅħįčħ čǿųŀđ ěįțħěř ẅǿřķ țǿ ěxțřǻčț đǻțǻ ǿř įňșěřț țħě mǻŀẅǻřě țǿ pǿțěňțįǻŀŀỳ șħųț đǿẅň ǻň ěňěřģỳ ģřįđ. Țħě ěxpŀǿįț ǻffěčțș ǻŀŀ věřșįǿňș ǿf Mįčřǿșǿfț Ẅįňđǿẅș ǻňđ ħǻș běěň đěvěŀǿpěđ țǿ bỳpǻșș țřǻđįțįǿňǻŀ ǻňțįvįřųș șǿŀųțįǿňș, ňěxț-ģěňěřǻțįǿň fįřěẅǻŀŀș, ǻňđ ěvěň mǿřě řěčěňț ěňđpǿįňț șǿŀųțįǿňș țħǻț ųșě șǻňđbǿxįňģ țěčħňįqųěș țǿ đěțěčț ǻđvǻňčěđ mǻŀẅǻřě. (bįǿměțřįč řěǻđěřș ǻřě ňǿň-řěŀěvǻňț țǿ țħě bỳpǻșș / đěțěčțįǿň țěčħňįqųěș, țħě mǻŀẅǻřě ẅįŀŀ șțǿp ěxěčųțįňģ įf įț đěțěčțș țħě přěșěňčě ǿf șpěčįfįč bįǿměțřįč věňđǿř șǿfțẅǻřě). Ẅě běŀįěvě țħě mǻŀẅǻřě ẅǻș řěŀěǻșěđ įň Mǻỳ ǿf țħįș ỳěǻř ǻňđ įș șțįŀŀ ǻčțįvě. İț ěxħįbįțș țřǻįțș șěěň įň přěvįǿųș ňǻțįǿň-șțǻțě Řǿǿțķįțș, ǻňđ ǻppěǻřș țǿ ħǻvě běěň đěșįģňěđ bỳ mųŀțįpŀě đěvěŀǿpěřș ẅįțħ ħįģħ-ŀěvěŀ șķįŀŀș ǻňđ ǻččěșș țǿ čǿňșįđěřǻbŀě řěșǿųřčěș. Ẅě vǻŀįđǻțěđ țħįș mǻŀẅǻřě čǻmpǻįģň ǻģǻįňșț ȘěňțįňěŀǾňě ǻňđ čǿňfįřměđ țħě șțěpș ǿųțŀįňěđ běŀǿẅ ẅěřě đěțěčțěđ bỳ ǿųř Đỳňǻmįč Běħǻvįǿř Țřǻčķįňģ (ĐBȚ) ěňģįňě. Mǻŀẅǻřě Șỳňǿpșįș Țħįș șǻmpŀě ẅǻș ẅřįțțěň įň ǻ mǻňňěř țǿ ěvǻđě șțǻțįč ǻňđ běħǻvįǿřǻŀ đěțěčțįǿň. Mǻňỳ ǻňțį-șǻňđbǿxįňģ țěčħňįqųěș ǻřě ųțįŀįżěđ.
    [Show full text]