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Exynos 9110 with Eplp: First Generation of Samsung’S Fan-Out Panel Level Packaging (FO-PLP)

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Exynos 9110 with Eplp: First Generation of Samsung’S Fan-Out Panel Level Packaging (FO-PLP) REVERSE COSTING® – STRUCTURE, PROCESS & COST REPORT Samsung Exynos 9110 with ePLP: First Generation of Samsung’s Fan-Out Panel Level Packaging (FO-PLP) The first ultra-small multi-chip High Volume Manufacturing (HVM) FO-PLP device for consumer applications found in the Samsung Galaxy Watch. Until 2018, Samsung integrated its molded substrate on four redistribution Application Processor Engine (APE) in layers (RDL). standard Package-on-Package (PoP) packaging. Starting this year, with the Dedicated to smart watch application, the Exynos 9810 in the Samsung Galaxy S9, module has to be extremely power- Samsung has brought a new packaging efficient with a low z-height and good technology called iPoP. And following this thermal dissipation. Thanks to the FO-PLP new packaging integration, the company technology applied to this SiP, Samsung has also introduced a breakthrough could realize the smallest form factor, technology using Fan-Out Panel Level lowest power and highest performance Packaging (FO-PLP) in its latest smart- solution on the market. watch, the Samsung Galaxy Watch. The report includes a complete analysis of Dealing with the dimensions and footprint the SiP FO-PLP, featuring die analyses, constraints of the watch world, Samsung processes and package cross-sections. It has managed to bring together an APE also includes a comparison with Nepes’ and a Power Management Integrated Redistributed Chip Packaging (RCP) Circuit (PMIC) in the same package in technology applied in the NXP SCM- System-in-Package (SiP)-PoP configura- i.MX6Q, TSMC’s integrated Fan-Out (inFO) tion. technology applied to the Apple A11 and This complete tiny solution is integrated Shinko’s Molded Core embedded on the main board of the Samsung Galaxy Packaging (MCeP) technology applied to Watch. The module includes the Exynos the Qualcomm Snapdragon 845. Title: Samsung 9110 application processor, and Exynos 9110 FO- Samsung’s Power management system all PLP SiP in a single package smaller than 80 mm². COMPLETE TEARDOWN WITH This is the second multi-chip Fan-Out • Detailed photos and cross-sections Pages: 127 device we have found on the market, but the first for a consumer product, which • Precise measurements Date: November could be a key milestone for Fan-Out SiP • Material analysis 2018 technology. • Manufacturing process flow Format: The system uses advanced panel-level • Supply chain evaluation PDF & Excel file packaging developed by Samsung-SEMCO. It has innovative interconnections, • Manufacturing cost analysis Price: enabling a Package-on-Package (PoP) • Estimated sales price EUR 3,990 configuration with Samsung’s in-house DRAM memory chip. The interconnections • Comparison with Nepes’ FO-WLP SiP are made with an embedded structure and TSMC’s inFO technology along with the PMIC and the APE in a IC – LED – RF – MEMS – IMAGING – PACKAGING – SYSTEM – POWER - DISPLAY SAMSUNG EXYNOS 9110 WITH EPLP: FIRST GENERATION OF SAMSUNG’S FO-PLP TABLE OF CONTENTS Overview/Introduction Manufacturing Process Flow Samsung Company Profile • Die Fabrication Unit: APE, PMIC Samsung Galaxy Watch Teardown • Packaging Fabrication Unit Physical Analysis • FO-PLP SiP Package Process Flow • Physical Analysis Methodology Cost Analysis • FO-PLP SiP Packaging analysis • Overview of the Cost Analysis Package view and dimensions • Supply Chain Description Package x-ray view • Yield Hypotheses Package opening: RDL, line/space width • Die Cost Analyses: APE, PMIC Package cross-section: RDL, bumps, Front-end cost Fan-Out substrate Wafers and dies costs • Physical Analysis Comparison • FO-PLP SiP Package Cost Analysis SiP vs discrete FO-PLP SiP panel cost TSMC’s inFO FO-PLP SiP cost by process NEPES’ RCP SiP step • Die Analysis: APE, PMIC • Final Test Cost Die view and dimensions • Component Cost Die cross-section Estimated Price Analysis Die process AUTHORS Dr Stéphane Elisabeth has joined Yvon Le Goff has joined System System Plus Consulting's team in Plus Consulting in 2011 to setup its 2016. He has a deep knowledge laboratory. He previously worked of Materials characterizations for 25 years at Atmel Nantes and Electronics systems. Technological Analysis Laboratory He holds an Engineering Degree as fab support in physical analysis, in Electronics and Numerical and for three years at Hirex Technology, and a PhD in Engineering in Toulouse, in a Materials for Microelectronics. destructive physical analysis lab. RELATED REPORTS NXP SCM-i.MX6 Quad High Second Generation of TSMC’s Samsung’s Galaxy S9 Plus Density Fan-Out Wafer-Level inFO Packaging for the Apple Processor Packages: System-in-Package A11 found in the iPhone X Samsung’s iPoP vs. The first ultra-small multi-die low The latest Apple application Qualcomm/Shinko MCeP power module with boot processor engine : from the Comparison Samsung Galaxy S9 memory and power mgmt stacked board to the A11, and processor packages: Samsung integrated in a PoP compatible reverse costing of TSMC’s Exynos 9810 with new TMV PoP device for the IoT. updated inFO packaging. vs. Qualcomm Snapdragon 845 June 2017 - EUR 3,490* February 2018 - EUR 3,490* with MCeP Packaging. June 2018 - EUR 3,490* REVERSE COSTING® – STRUCTURE, PROCESS & COST REPORT COSTING TOOLS Parametric IC MEMS Power Display PCB Costing Tools Price+ Price+ Price+ Price+ Price+ Process-Based MEMS Power LED 3D Package Costing Tools CoSim+ CoSim+ CoSim+ SYSCost+ CoSim+ Our analysis is performed with our costing tools 3D Packaging CoSim+ and IC Price+. System Plus Consulting offers powerful costing tools to evaluate the production cost and selling price from single chip to complex structures. 3D Packaging CoSim+ IC Price+ Cost simulation tool to evaluate the cost of any The tool performs the necessary cost simulation of Packaging process: Wafer-level packaging, TSV, 3D any Integrated Circuit: ASICs, microcontrollers, integration… memories, DSP, smartpower… ABOUT SYSTEM PLUS CONSULTING System Plus Consulting is specialized WHAT IS A REVERSE COSTING®? in the cost analysis of electronics from semiconductor devices to Reverse Costing® is the process of disassembling a device (or a electronic systems. system) in order to identify its technology and calculate its A complete range of services and manufacturing cost, using in-house models and tools. costing tools to provide in-depth production cost studies and to estimate the objective selling price of a product is available. Our services: • STRUCTURE & PROCESS ANALYSES CONTACTS • CUSTOM ANALYSES Headquarters America Sales Office Asia Sales Office • COSTING SERVICES 22, bd Benoni Goullin Steve LAFERRIERE Takashi ONOZAWA • COSTING TOOLS Nantes Biotech Western USA Japan & Rest of Asia • TRAININGS 44200 Nantes +1 310-600-8267 +81 3 4405 9204 France [email protected] [email protected] +33 2 40 18 09 16 [email protected] Troy BLANCHETTE Mavis WANG www.systemplus.fr Eastern USA Greater China [email protected] Europe Sales Office +1 704-859-0453 +886 979 336 809 Lizzie LEVENEZ [email protected] [email protected] Frankfurt am Main Germany +49 151 23 54 41 82 [email protected] SAMSUNG EXYNOS 9110 WITH EPLP: FIRST GENERATION OF SAMSUNG’S FO-PLP REVERSE COSTING® – STRUCTURE, PROCESS & COST REPORT ORDER FORM Please process my order for “Samsung Exynos 9110 with ePLP: First Generation of Samsung’s Fan-Out Panel Level Packaging (FO-PLP)” Return order by: Reverse Costing® – Structure, Process & Cost Report FAX: +33 2 53 55 10 59 Ref: SP18444 MAIL: SYSTEM PLUS CONSULTING 22, bd Benoni Goullin Full Structure, Process & Cost Report : EUR 3,990* Nantes Biotech Annual Subscription offers possible from 3 reports, including this 44200 Nantes – France report as the first of the year. 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