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Samsung 9110 with ePLP: First Generation of ’s Fan-Out Panel Level Packaging (FO-PLP)

The first ultra-small multi- High Volume Manufacturing (HVM) FO-PLP device for consumer applications found in the Watch.

Until 2018, Samsung integrated its molded substrate on four redistribution Application Processor Engine (APE) in layers (RDL). standard Package-on-Package (PoP) packaging. Starting this year, with the Dedicated to smart watch application, the Exynos 9810 in the , module has to be extremely power- Samsung has brought a new packaging efficient with a low z-height and good technology called iPoP. And following this thermal dissipation. Thanks to the FO-PLP new packaging integration, the company technology applied to this SiP, Samsung has also introduced a breakthrough could realize the smallest form factor, technology using Fan-Out Panel Level lowest power and highest performance Packaging (FO-PLP) in its latest smart- solution on the market. watch, the . The report includes a complete analysis of Dealing with the dimensions and footprint the SiP FO-PLP, featuring die analyses, constraints of the watch world, Samsung processes and package cross-sections. It has managed to bring together an APE also includes a comparison with Nepes’ and a Power Management Integrated Redistributed Chip Packaging (RCP) Circuit (PMIC) in the same package in technology applied in the NXP SCM- System-in-Package (SiP)-PoP configura- i.MX6Q, TSMC’s integrated Fan-Out (inFO) tion. technology applied to the and This complete tiny solution is integrated Shinko’s Molded Core embedded on the main board of the Samsung Galaxy Packaging (MCeP) technology applied to Watch. The module includes the Exynos the Snapdragon 845. Title: Samsung 9110 application processor, and Exynos 9110 FO- Samsung’s Power management system all PLP SiP in a single package smaller than 80 mm². COMPLETE TEARDOWN WITH This is the second multi-chip Fan-Out • Detailed photos and cross-sections Pages: 127 device we have found on the market, but the first for a consumer product, which • Precise measurements Date: November could be a key milestone for Fan-Out SiP • Material analysis 2018 technology. • Manufacturing process flow Format: The system uses advanced panel-level • Supply chain evaluation PDF & Excel file packaging developed by Samsung-SEMCO. It has innovative interconnections, • Manufacturing cost analysis Price: enabling a Package-on-Package (PoP) • Estimated sales price EUR 3,990 configuration with Samsung’s in-house DRAM memory chip. The interconnections • Comparison with Nepes’ FO-WLP SiP are made with an embedded structure and TSMC’s inFO technology along with the PMIC and the APE in a

IC – LED – RF – MEMS – IMAGING – PACKAGING – SYSTEM – POWER - DISPLAY SAMSUNG EXYNOS 9110 WITH EPLP: FIRST GENERATION OF SAMSUNG’S FO-PLP

TABLE OF CONTENTS

Overview/Introduction Manufacturing Process Flow Samsung Company Profile • Die Fabrication Unit: APE, PMIC Samsung Galaxy Watch Teardown • Packaging Fabrication Unit Physical Analysis • FO-PLP SiP Package Process Flow • Physical Analysis Methodology Cost Analysis • FO-PLP SiP Packaging analysis • Overview of the Cost Analysis  Package view and dimensions • Supply Chain Description  Package x-ray view • Yield Hypotheses  Package opening: RDL, line/space width • Die Cost Analyses: APE, PMIC  Package cross-section: RDL, bumps,  Front-end cost Fan-Out substrate  Wafers and dies costs • Physical Analysis Comparison • FO-PLP SiP Package Cost Analysis  SiP vs discrete  FO-PLP SiP panel cost  TSMC’s inFO  FO-PLP SiP cost by process  NEPES’ RCP SiP step • Die Analysis: APE, PMIC • Final Test Cost  Die view and dimensions • Component Cost  Die cross-section Estimated Price Analysis  Die process AUTHORS

Dr Stéphane Elisabeth has joined Yvon Le Goff has joined System System Plus Consulting's team in Plus Consulting in 2011 to setup its 2016. He has a deep knowledge laboratory. He previously worked of Materials characterizations for 25 years at Atmel Nantes and Electronics systems. Technological Analysis Laboratory He holds an Engineering Degree as fab support in physical analysis, in Electronics and Numerical and for three years at Hirex Technology, and a PhD in Engineering in Toulouse, in a Materials for Microelectronics. destructive physical analysis lab.

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