Pentium® III Processor Implementation Tradeoffs
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Design and Implementation of Pentium-M Based Floswitch for Intracluster Communication Veerappa Chikkagoudar, Dr
Design and Implementation of Pentium-M Based Floswitch for Intracluster Communication Veerappa chikkagoudar, Dr. U. N. Sinha, Prof. B. L. Desai. [email protected], [email protected], [email protected] Department of Electronics and Communication B. V. Bhoomaraddi college of Engg. And Tech. Hubli-580031 Abstract: aero dynamical problems, [1].Since 1986, six Flosolver MK6 is a Parallel processing system, generations of Flosolver machine have evolved based on distributed memory concept and built namely Flosolver MK-1, MK-2, MK-3, MK-4, MK-5 around Pentium-III processors, which acts as and MK-6. processing elements (PEs). Communication Flosolver MK-6 is the latest of the parallel between processing elements is very important, computer based on 128 Pentium III processors which is done through hardware switch called (which act as processing elements, PEs) in 64 dual Floswitch. Floswitch supports both message processor boards each with 1GB RAM and 80 GB passing as well as message processing. Message HDD. It is essentially a distributed memory system. processing is a unique feature of Floswitch. A group of four Dual processor boards with a Floswitch and an optical module is a natural cluster. In existing MK-6 system, communication 16 such clusters form the system. Processing between PEs is done through the Intel 486-based elements (PEs) communicate through Floswitch (a Floswitch, which operates at 32MHz and has 32- communication switch) using PCI-DPM interface bit wide data path. The data transfer rate and card. Clusters communicate through Optical module. floating point computation of existing switch need to be increased. -
Inside Intel® Core™ Microarchitecture Setting New Standards for Energy-Efficient Performance
White Paper Inside Intel® Core™ Microarchitecture Setting New Standards for Energy-Efficient Performance Ofri Wechsler Intel Fellow, Mobility Group Director, Mobility Microprocessor Architecture Intel Corporation White Paper Inside Intel®Core™ Microarchitecture Introduction Introduction 2 The Intel® Core™ microarchitecture is a new foundation for Intel®Core™ Microarchitecture Design Goals 3 Intel® architecture-based desktop, mobile, and mainstream server multi-core processors. This state-of-the-art multi-core optimized Delivering Energy-Efficient Performance 4 and power-efficient microarchitecture is designed to deliver Intel®Core™ Microarchitecture Innovations 5 increased performance and performance-per-watt—thus increasing Intel® Wide Dynamic Execution 6 overall energy efficiency. This new microarchitecture extends the energy efficient philosophy first delivered in Intel's mobile Intel® Intelligent Power Capability 8 microarchitecture found in the Intel® Pentium® M processor, and Intel® Advanced Smart Cache 8 greatly enhances it with many new and leading edge microar- Intel® Smart Memory Access 9 chitectural innovations as well as existing Intel NetBurst® microarchitecture features. What’s more, it incorporates many Intel® Advanced Digital Media Boost 10 new and significant innovations designed to optimize the Intel®Core™ Microarchitecture and Software 11 power, performance, and scalability of multi-core processors. Summary 12 The Intel Core microarchitecture shows Intel’s continued Learn More 12 innovation by delivering both greater energy efficiency Author Biographies 12 and compute capability required for the new workloads and usage models now making their way across computing. With its higher performance and low power, the new Intel Core microarchitecture will be the basis for many new solutions and form factors. In the home, these include higher performing, ultra-quiet, sleek and low-power computer designs, and new advances in more sophisticated, user-friendly entertainment systems. -
The Microarchitecture of the Pentium 4 Processor
The Microarchitecture of the Pentium 4 Processor Glenn Hinton, Desktop Platforms Group, Intel Corp. Dave Sager, Desktop Platforms Group, Intel Corp. Mike Upton, Desktop Platforms Group, Intel Corp. Darrell Boggs, Desktop Platforms Group, Intel Corp. Doug Carmean, Desktop Platforms Group, Intel Corp. Alan Kyker, Desktop Platforms Group, Intel Corp. Patrice Roussel, Desktop Platforms Group, Intel Corp. Index words: Pentium® 4 processor, NetBurst™ microarchitecture, Trace Cache, double-pumped ALU, deep pipelining provides an in-depth examination of the features and ABSTRACT functions of the Intel NetBurst microarchitecture. This paper describes the Intel® NetBurst™ ® The Pentium 4 processor is designed to deliver microarchitecture of Intel’s new flagship Pentium 4 performance across applications where end users can truly processor. This microarchitecture is the basis of a new appreciate and experience its performance. For example, family of processors from Intel starting with the Pentium it allows a much better user experience in areas such as 4 processor. The Pentium 4 processor provides a Internet audio and streaming video, image processing, substantial performance gain for many key application video content creation, speech recognition, 3D areas where the end user can truly appreciate the applications and games, multi-media, and multi-tasking difference. user environments. The Pentium 4 processor enables real- In this paper we describe the main features and functions time MPEG2 video encoding and near real-time MPEG4 of the NetBurst microarchitecture. We present the front- encoding, allowing efficient video editing and video end of the machine, including its new form of instruction conferencing. It delivers world-class performance on 3D cache called the Execution Trace Cache. -
Intel Xeon Processor Can Be Identified by the Following Values
Intel® Xeon® Processor Specification Update December 2006 Notice: The Intel® Xeon® processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this specification update. Document Number: 249678-056 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND/OR USE OF INTEL PRODUCTS, INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT, OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://developer.intel.com/design/litcentr. Intel®, the Intel® logo, Pentium®, Pentium® III Xeon™, Celeron, Intel® NetBurst™ and Intel® Xeon™ are trademarks or registered trademarks of Intel® Corporation or its subsidiaries in the United States and other countries. -
Lecture #2 "Computer Systems Big Picture"
18-600 Foundations of Computer Systems Lecture 2: “Computer Systems: The Big Picture” John P. Shen & Gregory Kesden 18-600 August 30, 2017 CS: AAP CS: APP ➢ Recommended Reference: ❖ Chapters 1 and 2 of Shen and Lipasti (SnL). ➢ Other Relevant References: ❖ “A Detailed Analysis of Contemporary ARM and x86 Architectures” by Emily Blem, Jaikrishnan Menon, and Karthikeyan Sankaralingam . (2013) ❖ “Amdahl’s and Gustafson’s Laws Revisited” by Andrzej Karbowski. (2008) 8/30/2017 (©J.P. Shen) 18-600 Lecture #2 1 18-600 Foundations of Computer Systems Lecture 2: “Computer Systems: The Big Picture” 1. Instruction Set Architecture (ISA) a. Hardware / Software Interface (HSI) b. Dynamic / Static Interface (DSI) c. Instruction Set Architecture Design & Examples 2. Historical Perspective on Computing a. Major Epochs of Modern Computers b. Computer Performance Iron Law (#1) 3. “Economics” of Computer Systems a. Amdahl’s Law and Gustafson’s Law b. Moore’s Law and Bell’s Law 8/30/2017 (©J.P. Shen) 18-600 Lecture #2 2 Anatomy of Engineering Design SPECIFICATION: Behavioral description of “What does it do?” Synthesis: Search for possible solutions; pick best one. Creative process IMPLEMENTATION: Structural description of “How is it constructed?” Analysis: Validate if the design meets the specification. “Does it do the right thing?” + “How well does it perform?” 8/30/2017 (©J.P. Shen) 18-600 Lecture #2 3 [Gerrit Blaauw & Fred Brooks, 1981] Instruction Set Processor Design ARCHITECTURE: (ISA) programmer/compiler view = SPECIFICATION • Functional programming model to application/system programmers • Opcodes, addressing modes, architected registers, IEEE floating point IMPLEMENTATION: (μarchitecture) processor designer view • Logical structure or organization that performs the ISA specification • Pipelining, functional units, caches, physical registers, buses, branch predictors REALIZATION: (Chip) chip/system designer view • Physical structure that embodies the implementation • Gates, cells, transistors, wires, dies, packaging 8/30/2017 (©J.P. -
Intel Pentium III Processor
Intel® Pentium® III Processor – Low Power/440BX AGPset Design Guide December 2002 Order Number: 273532-002 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® Pentium® III Processor – Low Power/440BX AGPset, 82443BX Host Bridge/Controller, and 82371EB PCI-to-ISA/IDE Xcelerated Controller may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. -
Smart Trac™ Drives
Product Bulletin #140102 – 3115T CPU Upgrade Effective May 5, 2003, an upgraded processor will be shipped with all 3115T units. Instead of a Intel® Pentium® III 850 MHz processor, the 3115T will now be shipped with an Intel® Celeron® 1.2 GHz processor while maintaining all current pricing. UNITS AFFECTED • 3115T-8850256-… • 3115T-HMI-8850256-…IWS • 3115T-HMI-8850256-…WW • 3115T-HMI-8850256-…CIT • All Product Modifications done with 3115T units. SPECIFICATIONS The CPU board in the 3115T has been revamped to accommodate Intel Tualatin processors. The Intel Celeron 1.2 GHz (1200 MHz) processor has been chosen to maintain the pricing levels of the current 3115T while providing a significant performance increase. The current Intel Pentium III 850 MHz processor runs at 100 MHz system bus and has 256 K cache. The new Celeron 1.2 GHz also runs at 100 MHz system bus and has 256 K cache. Some competitors are calling this a "Pentium III Celeron" and selling it as a Pentium III. The 1.2 GHz Celeron processor is 40% faster in speed values, scores approximately 40% faster in PC Mark 2002 CPU Scores, and is 25-30% faster in Sysmark 2002 Scores than the Pentium III 850 MHz. The touchscreen driver and the Ethernet drivers were also changed for this revision. If you or your customer have created an image for this unit, adjustments in that image will be required to function optimally with this new hardware. Several of the mechanical pieces are different to accommodate this new revision, but do not affect the user functionality of the unit. -
Intel Pentium III Processor Thermal Design Guidelines (Order Number 245087)
Intel® Pentium® III Processor Thermal Design Guide Application Note December 2001 Order Number: 273325-004 Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Pentium® III processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. MPEG is an international standard for video compression/decompression promoted by ISO. Implementations of MPEG CODECs, or MPEG enabled platforms may require licenses from various entities, including Intel Corporation. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. -
Powerpc, and Alpha • Multiprocessor Computers • Physical Memory • Bus Architecture and Bus Types 4277C01.Qxd 5/3/03 8:47 AM Page 2
4277c01.qxd 5/3/03 8:47 AM Page 1 The Computer’s Brain: Processors and Memory 1 pro•cess v : to complete a series of actions Every computer consists of a microprocessor and memory. Without the two, the computer would not function. The microprocessor, commonly referred to as the Central Processing Unit (CPU), is the brain of the com- puter. Like the human brain, the CPU is responsible for managing the timing of each operation and carrying out the instructions or commands from an application or the operating system. The CPU uses memory as a place to store or retrieve information. Memory comes in several forms, such as random access memory (RAM) and read- only memory (ROM). Memory provides a temporary location for storing information and contains more permanent system configuration information. This chapter provides an overview of these topics related to microprocessors and memory: • Processor performance • Processor types • History andCOPYRIGHTED evolution of Intel processors MATERIAL • Intel’s competition—AMD, Cyrix, PowerPC, and Alpha • Multiprocessor computers • Physical memory • Bus architecture and bus types 4277c01.qxd 5/3/03 8:47 AM Page 2 Chapter 1 Processor Performance The most central component to the computer is the processor. It is responsible for executing the instructions that are given to the computer. The processor deter- single-edge mines the operating systems you can use, the software applications you can run cartridge (SEC) on the computer, and the computer’s stability and performance. It is also typically An advanced packaging one of the major factors in computer cost. Computers that contain newer and scheme that the Intel Pen- powerful processors are more expensive than computers with less complex tium II and later models use. -
Intel Processor Identification and the CPUID Instruction
E AP-485 APPLICATION NOTE Intel Processor Identification and the CPUID Instruction January 1999 Order Number : 241618-012 1/14/99 2:13 PM CPUID INTEL CONFIDENTIAL (until publication date) Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Intel’s Intel Architecture processors (e.g., Pentium® processor, Pentium processor with MMX™ technology, Pentium Pro processor, Pentium II processor, Pentium II Xeon™ processor, Intel Celeron™ processor, Pentium III processor and Pentium III Xeon processor) may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. -
Summary of the Radiation Testing of the Intel Pentium III (P3) Microprocessor Martin A
Summary of the Radiation Testing of the Intel Pentium III (P3) Microprocessor Martin A. Carts James W. Howard Jr. Ronald Stattel Jackson and Tull Charles E. Rogers Chartered Engineers Washington, D.C. Raytheon/ITSS Lanham, Maryland Kenneth A. LaBel Timothy L. Irwin NASA/GSFC Code 561 QSS Group, Inc. Greenbelt, Maryland Lanham, Maryland Outline • Introduction • Test Methodologies • Hardware • Software • Test Issues • Sample Data • Summary Introduction • Many future NASA missions will require extensive on-board computation capability which raises the issue of availability, cost and capability of radiation hardened or radiation tolerant microprocessor systems. Radiation hardened computer systems are often costly and are actually two or three generations behind in computational capability, a significant shortfall for missions that may require state-of-the-art (SOTA) capability. • To confront these issues, NASA instituted the Remote Exploration and Experimentation Project (REE) with the goal of transferring commercial supercomputer technology into space using SOTA, low power, non-radiation-hardened, commercial-off-the-shelf (COTS) hardware and software to the maximum extent possible. Testing of the Pentium III microprocessor was done with this effort in mind. Test Methodologies • Total Ionizing Dose/Displacement Damage Dose – Level of performance testing • Functional failure levels, timing errors, power draw • Biased vs. Unbiased, idle vs. operating – Changing technology testing • 0.25 µm vs. 0.18 µm • Design and operation speeds Test Methodologies • Single Event Effects – Architecture and technology implications • Test SOTA technology and exercise that technology • Exercise independent pieces of the architecture with maximum duty cycle • Investigate technology versus operational conditions (e.g., rated versus operation clock speeds) – System level impacts • Destructive events • Function interrupts vs. -
Robert P. Colwell
Case 3:07-cv-04748-VRW Document 57-2 Filed 06/09/2008 Page 1 of 6 ROBERT P. COLWELL 3594 NW BRONSON CREST LOOP PORTLAND, OR 97229 503-690-7139 [email protected] PROFESSIONAL EXPERIENCE Consultant, Portland, OR 2001-present General computer HW/SW consulting to industry and academia Named an Intel Fellow (27 Fellows in Intel's employee population of ~80,000) in 1997; winner of 2005 Eckert-Mauchly Award, highest award in field of computer architecture, for “outstanding achievements in the design and implementation of industry-changing microarchitectures, and for significant contributions to the RISC/CISC architecture debate”; elected to IEEE Fellow and the National Academy of Engineering in 2006 (the highest recognition in field of engineering) for “contributions to turning novel computer architecture concepts into viable, cutting-edge commercial processors.” Chief IA-32 Architect, Intel Corporation, Hillsboro OR, 1992-2001 Lead IA32 architect, responsible for all of Intel's Pentium CPU architecture efforts (my direct management included 40 – 110 people) Initiated and led Intel's Pentium 4 CPU development Senior CPU Architect, Intel Corporation, Hillsboro OR, 1990-1992 One of three senior architects responsible for conceiving Intel's P6 microarchitecture, the core of the company's Pentium II, Pentium III, Celeron, Xeon, and Centrino families Hardware Architect, Multiflow Computer, New Haven, CT 1985-1990 One of seven HW designers who created the world's first VLIW (very long instruction word) scientific supercomputer under direction