Intel® Pentium® III Processor – Low Power/440BX AGPset

Design Guide

December 2002

Order Number: 273532-002 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® Pentium® III Processor – Low Power/440BX AGPset, 82443BX Host Bridge/Controller, and 82371EB PCI-to-ISA/IDE Xcelerated Controller may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. AlertVIEW, AnyPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, CT Connect, CT Media, Dialogic, DM3, EtherExpress, ETOX, FlashFile, i386, i486, i960, iCOMP, InstantIP, Intel, Intel logo, Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel Create & Share, Intel GigaBlade, Intel InBusiness, Intel Inside, Intel Inside logo, Intel NetBurst, Intel NetMerge, Intel NetStructure, Intel Play, Intel Play logo, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel TeamStation, Intel Xeon, Intel XScale, IPLink, Itanium, LANDesk, LanRover, MCS, MMX, MMX logo, Optimizer logo, OverDrive, Paragon, PC Dads, PC Parents, PDCharm, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, RemoteExpress, Shiva, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside., The Journey Inside, TokenExpress, Trillium, VoiceBrick, Vtune, and Xircom are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © Intel Corporation, 2002

2 Design Guide Contents

Contents

1.0 Introduction ...... 11 1.1 Key Terms ...... 11 1.2 Overview...... 11 1.3 Related Documents ...... 13 2.0 Design Features ...... 15 2.1 Intel® Pentium® III Processor – Low Power ...... 15 2.2 Intel® 440BX AGPset...... 15 2.2.1 System Bus Interface...... 16 2.2.2 DRAM Interface ...... 16 2.2.3 Accelerated Graphics Port Interface...... 16 2.2.4 PCI Interface...... 16 2.2.5 System Clocking ...... 16 2.3 PCI ISA IDE Xcelerator (PIIX4E) ...... 17 3.0 System Bus Guidelines...... 19 3.1 Definitions ...... 19 3.2 Recommended Low Power GTL+ Design Guideline ...... 22 3.2.1 Components ...... 22 3.2.2 Initial Timing Analysis ...... 22 3.2.3 Determine General Layout, Routing and Topology...... 24 3.2.4 Estimate Component to Component Spacing for Low Power GTL+ Signals ...... 25 3.3 Simulation ...... 26 3.3.1 Overview...... 26 3.3.2 Extract Interconnect Information...... 26 3.3.3 Run Simulations...... 26 3.4 Summary of System Design Guidelines ...... 27 3.5 Timing Diagram for Processor Side Bus...... 28 4.0 Memory Guidelines...... 29 4.1 100 MHz SDRAM Interface Overview ...... 29 4.1.1 SDRAM Signal Description...... 30 4.1.2 SDRAM Signal Connectivity ...... 31 4.1.3 Pin Groups...... 31 4.1.4 Single Set DRAM Interface...... 32 4.2 General SDRAM Layout Guidelines ...... 32 4.2.1 SO-DIMM Connection to SDRAM...... 32 4.3 Trace Lengths for Three or Two SO-DIMM Designs ...... 34 4.3.1 MD[63:0] Signals ...... 34 4.3.2 DQMA[7:0] Signals ...... 35 4.3.3 Chip Select Signals - CSA[5:0] ...... 36 4.3.4 Clock Enable Signals - CKE[5:0] ...... 36 4.3.5 Command Signals - MAB[13:0]x, WEA#, SRASA#, and SCASA ...... 37 4.4 SODIMM DRAM Organization ...... 38 4.4.1 SDRAM System Examples ...... 39 4.5 SO-DIMM Placement Options ...... 40

Design Guide 3 Contents

5.0 Clocking Guidelines ...... 43 5.1 Clocking System Overview ...... 43 5.2 Clock Synthesizer Pinout and Specifications...... 44 5.3 Timing Guidelines...... 45 5.4 Host Clock Layout Guidelines...... 46 5.5 SDRAM Clock Layout Guidelines...... 47 5.5.1 General Clocking Guidelines ...... 47 5.5.2 SDRAM Clock Layout Guidelines ...... 48 5.5.3 DCLKWR Layout Guidelines ...... 50 5.6 PCI/AGP Clock Layout Guidelines ...... 51 5.7 Clock Vendors ...... 52 6.0 82443BX AGP Interface Guidelines ...... 53 6.1 Layout and Routing Guidelines...... 53 6.1.1 On-board AGP Compliant Device Layout Guidelines ...... 54 6.2 ACPI Compliance Requirements...... 55 6.3 AGP IDSEL Routing ...... 56 7.0 Design Guideline Checklists ...... 57 7.1 Resistor Values...... 57 7.2 Pentium III Processor – Low Power Design Checklist...... 58 7.2.1 GTL+ Signals...... 58 7.2.2 CMOS Signals ...... 59 7.2.3 TAP Signals ...... 60 7.2.4 Clock Signals ...... 61 7.2.5 Miscellaneous Signals ...... 61 7.2.6 Power Pins...... 62 7.2.7 NO CONNECT Pins...... 62 7.2.8 Processor Decoupling Requirements ...... 63 7.3 82443BX Design Checklist ...... 63 7.3.1 Host Interface Signals...... 63 7.3.2 DRAM (SO-DIMM) Interface Signals ...... 64 7.3.3 PCI Interface Signals...... 65 7.3.4 PCI Sideband Signals...... 65 7.3.5 AGP Interface Signals ...... 66 7.3.6 Clocks, Resets, and Miscellaneous Signals ...... 67 7.3.7 Power Management Interface...... 67 7.3.8 Reference Pins ...... 68 7.3.9 82443BX Decoupling Guidelines...... 68 7.3.10 82443BX Strapping Options ...... 69 7.4 82371EB (PIIX4E) Design Checklist...... 70 7.4.1 PCI Interface Signals...... 70 7.4.2 ISA/EIO Bus Interface Signals...... 71 7.4.3 X-Bus Interface Signals ...... 72 7.4.4 DMA Signals...... 72 7.4.5 Interrupt Controller/APIC Signals...... 73 7.4.6 CPU Interface Signals ...... 73 7.4.7 Clocking Signals ...... 74 7.4.8 IDE Signals...... 75 7.4.9 USB Signals...... 76

4 Design Guide Contents

7.4.10 Power Management Signals...... 77 7.4.11 Other System and Test Signals ...... 78 7.4.12 Power and Ground Pins...... 78 7.4.13 PIIX4E Decoupling Guidelines...... 78 8.0 Power Sequencing ...... 79 8.1 PIIX4E Power Sequencing ...... 79 8.1.1 Power Sequencing Requirements ...... 79 8.1.2 Suspend/Resume and Power Plane Control ...... 79 8.1.3 System Resume ...... 82 8.1.4 System Suspend and Resume Control Signaling...... 84 8.1.5 Power Management State Transition Timings...... 91 8.2 82443BX Host Bridge/Controller Power Sequencing ...... 104 8.2.1 Power Sequencing Requirements ...... 104 8.2.2 Intel® 440BX AGPset Power Management...... 104 A Bill of Materials...... 117 B Schematics...... 125 C PLD Code Listing...... 155

Design Guide 5 Contents

Figures

1Intel® Pentium® III Processor – Low Power/440BX AGPset System Block Diagram ...... 12 2 Definition of the Flight Time Criteria - Falling Edge ...... 20 3 Definition of the Flight Time Criteria - Rising Edge...... 21 4Pentium® III Processor – Low Power General GTL+ Interconnect and Topology Guidelines...... 24 5 Processor Routing Example ...... 24 6Pentium® III Processor- Low Power Component Placement Example...... 25 7 Processor Side Bus Timing Concepts ...... 28 8 SDRAM Connections...... 33 9 MD[63:0] Topology, Three SO-DIMM Sockets ...... 34 10 MD[63:0] Topology, Two SO-DIMM Sockets...... 34 11 DQMA [7:0] Topology, Three SO-DIMM Sockets...... 35 12 DQMA [7:0] Topology, Two SO-DIMM Sockets ...... 35 13 CSA [5:0] Topology ...... 36 14 CKE[5:0] Topology ...... 36 15 Command Signals Topology, Three SO-DIMM ...... 37 16 Command Signals Topology, Two SO-DIMM...... 37 17 Three SO-DIMM Slots on One Side (First Two Back-to-Back)...... 40 18 Two SO-DIMM Slots Back-to-Back, Third Slot on the Other Side...... 40 19 Two SO-DIMM Slots on One Side, Third Slot on the Other Side ...... 41 20 Two SO-DIMM Slots on One Side, Third Slot on the Other Side (Alternate Method)...... 41 21 Clock Connections to the Intel® Pentium® III Processor — Low Power and 440BX Chipset...... 43 22 Pinout for CK100-M Compatible Clock Synthesizer ...... 44 23 Pinout for CKBF-M Compatible Clock Buffer...... 44 24 Timing Specifications Layout...... 45 25 Host Clock Topology ...... 46 26 Clocking Layout Diagram ...... 48 27 DCLKWR (Figure 16, Variable B2) Guidelines...... 50 28 PCI and AGP Clocking Layout ...... 51 29 On-board AGP Compliant Device Layout Guidelines...... 54 30 Signal Layout Recommendations...... 54 31 Pull-up Resistor Example ...... 57 32 External Glue Logic ...... 59 33 82443BX Decoupling...... 68 34 VREF Supply Schematic ...... 79 35 PIIX4E Power Well Timings...... 85 36 RSMRST# and PWROK Timings ...... 85 37 Suspend Well Power and RSMRST# Activated Signals ...... 86 38 PCI Clock Stop Timing ...... 87 39 PCI Clock Start Timing ...... 87 40 Core Well Power and PWROK Activated Signals (RSMRST# Inactive before Core Well Power Applied) ...... 88 41 Core Well Power and PWROK Activated Signals (Core Well Power Applied before RSMRST# Inactive) ...... 89 42 Mechanical Off to On...... 91

6 Design Guide Contents

43 On to POS ...... 92 44 POS to On (with Processor and PCI Reset)...... 93 45 POS to On (with Processor Reset)...... 94 46 POS to On (No Reset)...... 95 47 On to STR...... 96 48 STR to On...... 98 49 On to STD/SOff...... 100 50 STD/SOff to On...... 102 51 REFVCC5 Supply Circuit Schematic...... 104 52 System Power-up Sequencing ...... 107 53 Suspend/Resume with PCIRST# Active...... 113 54 Suspend/Resume with CPURST#, PCIRST# Inactive ...... 114 55 Suspend/Resume with CPURST# Active, PCIRST# Inactive...... 115 56 Suspend/Resume from STD...... 116

Design Guide 7 Contents

Tables

1 Related Intel Documents ...... 13 2 Related Specifications ...... 13 3 Summary of Board Design Guidelines ...... 27 4 SDRAM Signal Descriptions...... 30 5 SDRAM Signals and Corresponding SO-DIMM Pins ...... 31 6 82443BX SDRAM Signals and Corresponding Onboard SDRAM Signals...... 31 7 MD[63:0] Topology, Three SO-DIMM Sockets - Section Tolerances ...... 34 8 MD[63:0] Topology, Two SO-DIMM Sockets - Section Tolerances...... 35 9 DQMA [7:0] Topology, Three SO-DIMM Sockets, Section Tolerances ...... 35 10 DQMA [7:0] Topology, Two SO-DIMM Sockets - Section Tolerances ...... 35 11 CSA[5:0] Topology - Section Tolerances ...... 36 12 CKE[5:0] Topology - Section Tolerances ...... 36 13 Command Signals Topology, Three SO-DIMM - Section Tolerances ...... 37 14 Command Signals Topology, Two SO-DIMM - Section Tolerances...... 37 15 SODIMM DRAM Organization...... 38 16 SDRAM System Examples...... 39 17 Timing Specifications for Maximum and Minimum Clock Skews...... 45 18 Host Clock Trace Length Guidelines ...... 46 19 SDRAM Clocks and DCLK Trace Lengths ...... 49 20 DCLKWR Guidelines - Section Tolerances ...... 50 21 PCI and AGP Clock Trace Length...... 51 22 Clock Vendors ...... 52 23 Data and Associated Strobe...... 53 24 Motherboard Recommendations ...... 54 25 Control Signal Line Length Recommendations ...... 55 26 GTL+ Signals...... 58 27 CMOS Signals ...... 60 28 Clock Signals...... 61 29 Miscellaneous Signals ...... 61 30 Power Pins ...... 62 31 NO CONNECT Pins ...... 62 32 Host Interface Signals ...... 63 33 DRAM (SO-DIMM) Interface Signals...... 64 34 PCI Interface Signals...... 65 35 PCI Sideband Signals...... 65 36 AGP Interface Signals ...... 66 37 Clocks, Resets, and Miscellaneous Signals ...... 67 38 Power Management Interface ...... 67 39 Reference Pins ...... 68 40 82443BX Strapping Options ...... 69 41 PCI Interface Signals...... 70 42 ISA/EIO Bus Interface Signals...... 71 43 X-Bus Interface Signals ...... 72 44 DMA Signals...... 72 45 Interrupt Controller/APIC Signals ...... 73 46 CPU Interface Signals ...... 73 47 Clocking Signals ...... 74 48 IDE Signals...... 75

8 Design Guide Contents

49 USB Signals...... 76 50 Power Management Signals...... 77 51 Other System and Test Signals...... 78 52 Power and Ground Pins...... 78 53 Power State Decode...... 81 54 Resume Events Supported In Different Power States...... 82 55 Resume Event Programming Model...... 83 56 Power Plane Control...... 84 57 Power Plane Control Using SUS[C:A]# Signals ...... 84 58 PIIX4E Power Well Timing Tolerances...... 85 59 RSMRST# and PWROK Timing Tolerance ...... 85 60 Suspend Well Power and RSMRST# Timing Tolerances...... 86 61 Core Well Power and PWROK Timing Tolerances...... 88 62 Core Well Power and PWROK Timing ...... 90 63 Mechanical Off to On Timing Tolerances ...... 91 64 On to POS Timing Tolerances...... 92 65 POS to On Timing Tolerances...... 93 66 POS to On (with Processor Reset) Timing Tolerances ...... 94 67 POS to On (No Reset) Timing ...... 95 68 On to STR Timing Tolerances ...... 97 69 STR to On Timing Tolerances ...... 99 70 On to STD/SOff Timing Tolerances...... 101 71 STD/SOff to On Timing Tolerances...... 103 72 System-wide Low-power Modes...... 105 73 System Power-up Sequencing Tolerances...... 108 74 Suspend Resume Events And Activities...... 109 75 Intel® 440BX AGPset Signal States During POS and STR Modes ...... 110 76 Suspend/Resume Timing Tolerances...... 112 77 Bill of Materials ...... 117

Design Guide 9 Contents

Revision History

Date Revision Description

Section 7.3.3, PLOCK# - In Pin Connection description, removed reference to PIIX4E in the second sentence. Section 7.3.5, Introductory bullet - Revised to state “To disable AGP, tie MAB9# high using a 10 K ohm pull-up to 3.3 V, connect GCLKO to GCLKIN through an 18 W resistor, and ground AGPREF. Section 7.3.6, DCLKWR - Revised Pin Connection description to state “22 Ω series termination at CKBFM. ‘T’ at the 22 Ω resistor with 15 pF cap to Vss.” Section 7.3.6, GCLKIN, Revised Pin Connection description to state “Connect to GCLKO through 18 Ω series resistor.” Section 7.4.5, IRQ [3:7, 9:11, and 14:15] - In Pin Connection description, added comma between 3:7 and 9:11. Section 7.4.5, PIRQ[A:D]# - In Pin Connection description, removed reference to 82443BX. December 2002 002 Section 7.4.7, CLK48 - In Pin Connection description, added second sentence to state “When not using USB, the may be connected to GND.” Section 7.4.10, PCIREQ[A:D] - In Pin Connection description, added second sentence to state “Connect to 82443BX and PCI slots.” Section 7.4.10, RSMRST# - Added sentence to Pin Connection description to state “When not using power management (suspend modes), this may be connected to PIIX4E PWROK. Section 7.4.10, Vss (USB) - Removed reference as it is duplicated. Section 7.4.11, PWROK - Revised second sentence in Pin Connection description to state “When not using power management (suspend modes), also connect to PIIX4E RSMRST#.” Section 7.4.11, SPKR - Added sentence to Pin Connection description to state “NO CONNECT if not used.” Section 4.1.1 - Changed note for MAB[13] from Note #1 to Note #2. August 2001 001 Initial release of this document.

10 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

1.0 Introduction

This document provides design guidelines for developing systems based on the Intel® Pentium® III processor – Low Power in a BGA2 package and the Intel® 440BX AGPset. System board and memory subsystem design guidelines are included. Special design recommendations and concerns are presented. Likely design errors have been listed here in a checklist format. These are recommendations only. It is recommended that you perform your own simulations to meet design-specific requirements.

Note: These guidelines also apply to the Intel® Celeron® processor – Low Power in a BGA2 package.

1.1 Key Terms

The Pentium® III processor – Low Power is specific to the applied computing market segment. A complete description of the processor is located in the Intel® Pentium® III Processor – Low Power Datasheet (order number 273500).

Intel 440BX AGPset refers to both the 82443BX Host Bridge/Controller and the 82371EB PCI ISA IDE Xcelerator.

82443BX refers to the Intel 82443BX Host Bridge/Controller.

PIIX4E refers to the Intel 82371EB PCI ISA IDE Xcelerator.

Design Features are items that allow the designer to fully use the capabilities of the Pentium III processor and the Intel 440BX AGPset.

Design Checklists are items which provide recommendations for designing an Pentium III processor – Low Power-based platform.

Design Considerations are items that should be considered but may not be applicable to your design.

1.2 Overview

A Pentium III processor – Low Power/440BX AGPset system contains the features summarized below. Figure 1 is a block diagram of a typical Pentium III processor – Low Power/440BX AGPset system design. • Full support for the Pentium® III processor – Low Power with system bus frequency of 100 MHz • Intel 440BX AGPset — 82443BX Host Bridge/Controller (443BX) — 82371EB PCI ISA IDE Accelerator (PIIX4E) • 100 MHz memory interface: A wide range of DRAM support including: — 64-bit memory data interface plus eight ECC bits and hardware scrubbing — 100 MHz SDRAM Support — 64-Mbit and 128-Mbit DRAM technologies

Design Guide 11 Intel® Pentium® III Processor – Low Power/440BX AGPset

• Five PCI masters — PCI Specification Rev 2.1 Compliant • Accelerated Graphics Port (AGP) Slot: — AGP Interface Specification Revision 1.0 compliant — AGP - 66/133 MHz, 3.3 V device support • Integrated IDE controller with Ultra DMA/33 support — PIO Mode 4 transfers — PCI IDE bus master support • Integrated Universal Serial Bus (USB) controller with two USB ports • Integrated System Power Management support

Figure 1. Intel® Pentium® III Processor – Low Power/440BX AGPset System Block Diagram

®

Pentium® III Processor Low Power 495-BGA2 100 MHz GTL+ Processor 100 MHz Interface SDRAM Bus PCI AGP AGP 82443BX 3.3 V Host Bridge/ Slots Enabled Interface Device Controller 492 mBGA 3.3 V PCI-0 (33 MHz, 5 V Tolerant)

82371EB USB Bus Master IDE PIIX4E GPIO (30+) 324 mBGA SMBus

3.3 V ISA (5 V Tolerant) Ultra DMA/33 IDE Audio MicroController Infrared Floppy Disc Parallel Port Serial Port Keyboard BIOS

A8984-01

12 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

1.3 Related Documents

Table 1. Related Intel Documents

Document Order Number

Intel® Pentium® III Processor – Low Power Datasheet 273500 Mobile Pentium® III Processor Specification Update 245306 Intel® 440BX AGPset: 82443BX Host Bridge/Controller Datasheet 290633 Intel® 440BX AGPset 82443BX Host Bridge/Controller Specification Update 290639 Intel® 82371AB PCI-to-ISA/IDE Xcelerator (PIIX4) Datasheet 290562 Intel® 82371AB PIIX4E, Intel 82371EB PIIX4E and Intel 82371MB PIIX4M Specification 297738 Update Intel® Architecture Software Developer’s Manual, Volume 1; Basic Architecture 243190 Intel® Architecture Software Developer’s Manual, Volume 2; Instruction Set Reference 243191 Intel® Architecture Software Developer’s Manual, Volume 3; System Programming Guide 243192 Intel® Architecture MMX™ Technology Developer’s Guide 243006 Low Power Module SDRAM DIMM Routing Guidelines 273317 CK97 Clock Synthesizer Design Guidelines Application Note 243867 AP-485 Intel Processor Identification and the CPUID Instruction Application Note 241618 Pentium® III Processor Active Thermal Management Technology Application Note 273405 Intel® Pentium® III Processor - Low Power Thermal Design Guide 273285 PIIX4 Universal Serial Bus Design Guide and Checklist NDA† † NDA documents are only available through an Intel Field Sales Representative.

Table 2. Related Specifications

Document URL/Contact

PCI Local Bus Specification, Revision 2.1 http://www.pcisig.com/specs.html Universal Serial Bus Specification, Revision 1.1 http://www.usb.org/developers/docs.html AGP Interface Specification, Revision 1.0 http://www.agpforum.org/index.htm AGP Platform Design Guide, Revision 1.1A http://www.agpforum.org/index.htm System Management Bus Specification http://www.sbs-forum.org/ 66-MHz Unbuffered SDRAM 64-bit (Non-ECC/Parity) http://developer.intel.com/technology/memory/ 144-pin SO-DIMM Specification, Revision 1.0 sodm1_0.htm http://developer.intel.com/design/USB/ Universal Host Controller Interface (UHCI) Design Guide UHCI11D.htm

Design Guide 13 Intel® Pentium® III Processor – Low Power/440BX AGPset

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14 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

2.0 Design Features

2.1 Intel® Pentium® III Processor – Low Power

The Intel® Pentium® III processor – Low Power is the first of the Pentium III processor family to be offered for the applied computing platform. It is offered in a 495 ball BGA2 package at 400 MHz, 500 MHz and 700 MHz with a processor system bus speed of 100 MHz. It consists of a Pentium III processor core with an integrated 256-Kbyte second-level cache and a 64-bit high-performance host bus. The second-level cache bus complements the host bus by providing critical data faster, improving performance, and reducing total system power consumption. The Pentium III processor – Low Power’s 64-bit wide low power GTL+ host bus is compatible with the Intel® 440BX AGPset and provides a glueless, point-to-point interface for an I/O bridge and memory controller.

2.2 Intel® 440BX AGPset

The Intel® 440BX AGPset is based on the Pentium III processor architecture. It interfaces with the Pentium III processor’s system bus at 100 MHz. Along with its Host-to-PCI bridge interface, the 82443BX Host Bridge/Controller has been optimized with a 100 MHz SDRAM memory controller and data path unit. The 82443BX also features the Accelerated Graphics Port (AGP) interface. The 82443BX component includes the following functions and capabilities: • 64-bit Low Power GTL+ based system data bus interface • 32-bit system address bus support • 64-bit main memory interface with optimized support for SDRAM • 32-bit PCI bus interface with integrated PCI arbiter • AGP interface with up to 133 MHz data transfer capability • Extensive data buffering between all interfaces for high throughput and concurrent operations

Figure 1 shows a block diagram of a typical platform based on the 440BX AGPset. The 82443BX system bus interface supports a Pentium III processor at a bus frequency of 100 MHz. The physical interface design is based on the Low Power GTL+ specification and is compatible with the Intel 440BX AGPset. The 440BX provides an optimized 72-bit DRAM interface (64-bit Data plus ECC). This interface supports 3.3 V DRAM technologies.

The 82443BX is designed to support the PIIX4E PCI-to-ISA bridge. The PIIX4E is a highly-integrated multifunctional component that supports the following functions and capabilities: • PCI Revision 2.1 compliant PCI-to-ISA bridge with support for 33 MHz PCI operations • ACPI Power Management support • Enhanced DMA controller, interrupt controller and timer functions • Integrated IDE controller with Ultra DMA/33 support • USB host interface with support for two USB ports • System Management Bus (SMB) with support for DIMM Serial Presence Detect

Design Guide 15 Intel® Pentium® III Processor – Low Power/440BX AGPset

2.2.1 System Bus Interface

The 82443BX supports a maximum of 4 Gbytes of memory address space from the processor perspective. The largest address size is 32 bits. The 82443BX provides bus control signals and address paths for transfers between the processor bus, PCI bus, Accelerated Graphics Port and main memory. The 82443BX supports a 4-deep-in-order queue, which provides support for pipelining of up to four outstanding transaction requests on the system bus. The Pentium III processor supports a second-level cache. All cache-control logic is provided on the processor.

For system bus-to-PCI transfers, the addresses are either translated or directly forwarded on the PCI bus, depending on the PCI address space being accessed. When the access is to a PCI configuration space, the processor I/O cycle is mapped to a PCI configuration space cycle. When the access is to a PCI I/O or memory space, the processor address is passed without modification to the PCI bus. Certain memory address ranges are dedicated for a graphics memory address space. When this space or a portion of it is mapped to main DRAM, the address is translated by the AGP address remapping mechanism and the request is forwarded to the DRAM subsystem. A portion of the graphics aperture may be mapped on the AGP, and the corresponding system bus cycles accessing that range are forwarded to the AGP without any translation. The AGP address map defines other system bus cycles that are forwarded to the AGP.

2.2.2 DRAM Interface

The 82443BX integrates a main memory controller that supports a 64-bit DRAM interface which operates at 100 MHz. The integrated DRAM controller features include: • 3.3 V interface • Support for up to three double-sided SODIMMs — 384 Mbytes using 128-Mbit technology — 192 Mbytes using 64-Mbit technology — 48 Mbytes using 16-Mbit technology • Support for ECC with hardware scrubbing

2.2.3 Accelerated Graphics Port Interface

The 82443BX supports an AGP interface. The AGP interface has a maximum theoretical transfer rate of ~532 Mbytes/s.

2.2.4 PCI Interface

The 82443BX PCI interface operates at 3.3 V (5 V tolerant), 33 MHz, is Revision 2.1 compliant, and supports up to five external PCI bus masters in addition to the PIIX4E I/O bridge.

2.2.5 System Clocking

Used with the Pentium® III processor, the 82443BX operates the system bus interface at 100 MHz, the PCI bus at 33 MHz and the AGP at a transfer rate of 66/133 MHz. The 82443BX clocking scheme uses an external clock synthesizer that produces reference clocks for the system bus and PCI interfaces. The 82443BX generates the AGP and DRAM clock signals. Please refer to the CK97 Clock Synthesizer/Design Guidelines Application Note (order number 243867).

16 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

2.3 PCI ISA IDE Xcelerator (PIIX4E)

The PCI ISA IDE Xcelerator (PIIX4E) is a multi-function PCI device that implements a PCI-to-ISA bridge function, a PCI IDE function, a Universal Serial Bus host/hub function, and an Enhanced Power Management function. Because it is a PCI-to-ISA bridge, the PIIX4E integrates many common I/O functions found in ISA-based PC systems; a seven channel DMA Controller, two 82C59 Interrupt Controllers, an 8254 Timer/Counter, and a Real Time Clock. In addition to DMA Compatible transfers, each DMA channel also supports Type F transfers.

The PIIX4E contains full support for PC/PCI and Distributed DMA protocols that implement PCI-based DMA. The Interrupt Controller has edge or level sensitive programmable inputs. Chip select decoding is provided for a BIOS, Real Time Clock, Keyboard Controller, second external microcontroller, and two Programmable Chip Selects. The PIIX4E provides full Plug-and-Play compatibility. The PIIX4E may be configured as a subtractive decode bridge or as a positive decode bridge.

The PIIX4E supports two IDE connectors. This provides an interface for IDE/EIDE hard disks and CD-ROMs. Up to four IDE devices may be supported in Bus Master mode. The PIIX4E contains support for Ultra DMA/33 compatible synchronous DMA devices.

The PIIX4E contains a Universal Serial Bus (USB) host controller that is Universal Host Controller Interface (UHCI) compatible. The host controller’s root hub has two programmable USB ports.

The PIIX4E supports Enhanced Power Management, including full clock control, device management for up to 14 devices, and suspend and resume logic with Power On Suspend, Suspend to RAM, or Suspend to Disk. The PIIX4E fully supports operating-system-directed power management according to the Advanced Configuration and Power Interface (ACPI) specification. The PIIX4E integrates both a System Management bus (SMBus) host and slave interface for serial communication with other devices.

For more information on the PIIX4E, please refer to the Intel® 82371AB PCI-to-ISA/IDE Xcelerator (PIIX4) Datasheet (order number 290562) and the Intel® 82371AB PIIX4, Intel® 82371EB PIIX4E and Intel® 82371MB PIIX4M Specification Update (order number 297738).

Design Guide 17 Intel® Pentium® III Processor – Low Power/440BX AGPset

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18 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

3.0 System Bus Guidelines

This section provides the guidelines required for the Pentium® III processor – Low Power and 82443BX bus portion of the PCB layout. The guidelines and methodologies do not provide absolute rules. They include recommendations on Processor System Bus (PSB) routing topologies and system board impedance. Even when the guidelines are followed, it is strongly recommended that you run analog simulations using the available I/O buffer models together with layout information extracted from your specific design.

3.1 Definitions

Frequently used abbreviations are defined below: Aggressor - A network that transmits a coupled signal to another network is called the aggressor network. Bus Agent - A component or group of components that, when combined, represent a single load on the GTL+ bus. Corner - Describes how a component performs when all parameters that could impact performance are adjusted to have the same impact on performance. Examples of these parameters include variations in the manufacturing process, the operating temperature, and the operating voltage. The results in performance of an electronic component that may change as a result of this in- clude but are not limited to: clock to output time, output driver edge rate, output drive current, and input drive current. Discussion of the ‘slow’ corner means having a component operating at its slowest, weakest performance. Similar discussion of the ‘fast’ corner means having a component operating at its fastest, strongest performance. Operation or simulation of a com- ponent at its slow corner and fast corner is expected to bind the extremes between slowest, weakest performance and fastest, strongest performance. The component packages, printed circuit boards and electrical connectors also have corner characteristics that effect Pentium III processor-Low Power based system designs. Crosstalk - The reception on a victim network of a signal imposed by aggressor network(s) through inductive and capacitive coupling between the networks. Backward Crosstalk - Coupling that creates a signal in a victim network that travels in the opposite direction as the aggressor’s signal. Even Mode Crosstalk - Coupling from one or more aggressors when all the aggressors switch in the same direction that the victim is switching. Forward Crosstalk - Coupling that creates a signal in a victim network that travels in the same direction as the aggressor’s signal. Odd Mode Crosstalk - Coupling from one or more aggressors when all the aggressors switch in the opposite direction that the victim is switching. Flight Time - The additional delay between the driver and receiver introduced by the printed circuit board interconnects and the component loading effects as compared to the data sheet specifi- cation load. Although the name implies that this is the time required for a signal to travel from one end of the interconnect to the other, a better definition of this term is simply that it is the total delay the layout (interconnects plus loads) adds to the component timings. (This is similar to the usage of the term ‘derating’, but that term fails to acknowledge that transmission line effects are being included in the analysis.) Flight time is therefore defined as the difference between when a signal at the input pin of a receiving agent crosses VREF and the time that the output pin of the driving agent crosses the VREF were it driving the test load used

Design Guide 19 Intel® Pentium® III Processor – Low Power/440BX AGPset

to specify that driver’s AC timings. VREF for the Pentium III processor- Low Power is 2/3 of VCCT. (VCCT = VTT)

Flight time is defined as:

TFLIGHT = TRECEIVER - TREF

where TREF is the reference delay discussed above, and TRECEIVER is the time at which the waveform has a valid VREF crossing. Figure 2 and Figure 3 show the definition of flight time. Notice that determining flight time requires a minimum of two simulations, one in which the driver is driving the test load, and one in which it is driving the actual system load. Also note that this method introduces the concept of negative flight time, as seen in Figure 3. Figure 2. Definition of the Flight Time Criteria - Falling Edge

20 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

Figure 3. Definition of the Flight Time Criteria - Rising Edge

Maximum and Minimum Flight Time - Flight time variations may be caused by many different parameters. The more obvious causes include variation of the board dielectric constant, changes in load condition, variation in termination resistance and differences in I/O buffer performance as a function of temperature, voltage and manufacturing process. Some less obvious causes include effects of multiple signals switching and additional packaging affects. Table 4 includes recommended adjustment factors. Maximum Flight Time – This is the largest flight time a network will experience under all variations of conditions. Minimum Flight Time - This is the smallest flight time a network will experience under all variations of conditions. FSB - Front Side Bus, a reference to the GTL+ bus on the front of the Pentium III processor – Low Power, as opposed to the cache or backside bus. This nomenclature is not used in this document. Please see PSB. GTL+ - The bus technology used by the Pentium III processor – Low Power. This is an incident wave switching, open drain bus with internal pullups at the processor that provide both the high logic level and termination at each processor end of the bus. It is an enhancement to the GTL+(Gunning Transceiver Logic) technology. Refer to the Pentium® II Processor Developer’s Manual for more information. Low Power GTL+ - A modification of the GTL+ bus technology for use in low power applied computing applications. Network - The trace of a Printed Circuit Board (PCB) that completes an electrical connection be tween two or more components. Network Length - The distance between extreme bus agents on the network and does not include the distance connecting the end bus agents to the termination resistors.

Design Guide 21 Intel® Pentium® III Processor – Low Power/440BX AGPset

Northbridge - The system logic component that interfaces directly to the processor’s PSB. OEM - Original Equipment Manufacturer.

Overdrive Region - The voltage range, at a receiver, from VREF to VREF + 200 mV for a low to high going signal and VREF to VREF - 200 mV for a high to low going signal.

Overshoot - A voltage amplitude that exceeds the maximum voltage, VIH, level as specified in the component specification. PSB - Processor System Bus, a reference to the Low Power GTL+ bus on the Pentium III processor – Low Power. Ringback - The re-crossing of a high or low input logic threshold after it has initially crossed that logic threshold. Settling Limit - The maximum allowed peak to peak oscillation after a signal has transitioned to the correct logic level as specified in the component specification.

Setup Window - The time between the beginning of Setup to Clock (TSU_MIN) and the clock input.

Undershoot - A voltage amplitude that negatively exceeds the minimum low voltage, VIL level as specified in the component specification. Victim - A network that receives a coupled crosstalk signal from another network is called the victim network.

3.2 Recommended Low Power GTL+ Design Guideline

The following step-by-step guideline was developed for systems based on one Pentium III processor – Low Power and one 82443BX load. The methodology recommended in this section is based on experience developed at Intel while developing many different Pentium III processor- based systems for validation and feasibility studies. This methodology relies on spreadsheet type calculations for initial timing analysis and performing signal integrity/noise analysis. The analog simulations should be validated after actual systems become available.

3.2.1 Components

The GTL+ PSB is restricted to two agents: the Pentium III processor – Low Power and the 82443BX.

3.2.2 Initial Timing Analysis

An initial timing analysis of the system is required. To complete the timing analysis, values for the clock skew and clock jitter are needed with the component specifications. These values should be sufficient for determining the bounds for system flight times. Equation 1 and Equation 2 are the basis for the timing analysis.

Equation 1. Maximum Frequency ≥ Clock Period TFLIGHT_MAX + TCO_MAX + TSU_MIN + CLKSKEW + CLKJITTER + TADJ_SU Equation 2. Hold Time ≥ TCO_MIN + TFLT_MIN THOLD + CLKSKEW + TADJ_Hold

22 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

Symbols used in Equation 1 and Equation 2:

1 TCO_MAX - the maximum clock to output specification. 1 TCO_MIN - the minimum clock to output specification. 1 TSU_MIN - the minimum required time specified to setup before the clock.

THOLD - the minimum specified input hold time.

TADJ - an empirical timing adjustment factor that accounts for timing ‘push out’ or ‘pull in’ seen when multiple bits change state at the same time. The factors that contribute to the adjustment factor include crosstalk on the PCB, substrate, and packages, simultaneous switching noise, and edge rate degradation caused by inductance in the ground return path.2 This number is also sometimes called Tsso. The SSO stands for Simultaneous Switching Output. This adjustment is for board SSO, not chip SSO, as chip SSO numbers are included in the Tco specification of the device.

CLKJITTER - the maximum clock edge to edge variation.

CLKSKEW - the maximum variation between components receiving the same clock edge.

TFLT_MAX - the maximum flight time as defined in Section 3.1.

TFLT_MIN - the minimum flight time as defined in Section 3.1.

NOTES: 1. The Clock to Output (TCO) and Setup to Clock (TSU) timings are both measured from the signals last crossing of VREF, with the requirement that the signal does not violate the ringback or edge rate limits. See the Pentium® II Processor Developer’s Manual for more details. 2. TADJ should be calculated for each individual system. A value of 0.5 ns is used throughout this document and may be used as a generic TADJ value during flight time calculations if an actual crosstalk flight time delay may not be calculated.

Solving these equations for flight time results in the following equations:

Equation 3. Maximum Flight Time

TFLIGHT_MAX = Clock Period - TCO_MAX - TSU_MIN - CLKSKEW - CLKJITTER - TADJ_SU Equation 4. Minimum Flight Time

TFLIGHT_MIN = THOLD + CLKSKEW + TADJ_Hold - TCO_MIN There are two cases to consider. Note that while the same trace connects two components (e.g., A and B), the minimum and maximum flight time requirements for A driving B as well as B driving A must be met. The cases discussed in this document are:

Pentium III processor – Low Power driving the 82443BX

82443BX driving the Pentium III processor – Low Power

GTL+ trace lengths required to meet these timings may be calculated using the maximum and minimum flight time calculations and the effective board propagation constant (SEFF). SEFF is a function of:

Design Guide 23 Intel® Pentium® III Processor – Low Power/440BX AGPset

ε Dielectric constant ( r) of the PCB material The type of trace connecting the components (stripline or microstrip)

The length of the trace and the load of the components on the trace. (Note that the board propagation constant multiplied by the trace length is a component of the flight time but not necessarily equal to the flight time.)

3.2.3 Determine General Layout, Routing and Topology

Once the processor bus components have been selected and the timing budget calculated, then determine their approximate location on the printed circuit board. Estimate the printed circuit board parameters from the placement and other information including the following general layout and routing given below: Figure 4. Pentium® III Processor – Low Power General GTL+ Interconnect and Topology Guidelines

Pentium® III Processor – Low Power

Processor 82443BX Core

1.5 – 6.0 inches

Figure 5. Processor Routing Example

® 82443BX Host Bridge/ PentiumPentium III® III Processor Processor – Low— Low Power Power 82443BXController

General recommendations for Low Power GTL+ bus topology, layout, and routing are given in the following list. Also refer to Figure 4 and Figure 5. • The net must not exceed 6.0 inches and must exceed 1.5 inches. Ω • Closely control the characteristic line impedance, Z0 = 55 +/- 10%. • PSB Traces should all be internal traces except for the breakout from the processor or chipset, which should not exceed 75 mils. • Successive dual-stripline trace layers should be routed orthogonally. • Trace width and spacing should be at least 4/6. (Trace width and spacing of 4/8 is even better. Do not route 5/5 except as necessary within the area of the processor or chipset.) • Triple and Quad-stripline stackups are discouraged. When these types of stackups are used, Intel recommends a rigorous post-layout validation of the design including crosstalk analysis.

24 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

• Route the same type of Low Power GTL+ I/O signals in isolated signal groups. That is, route the data signals in one group, the address signals in another group. Keep at least 12 mils between each group of signals. • Minimize use of vias. • Maximum parallel- trace routing length is 3.5 inches (at 4/6). • Always be sure to validate signal quality after making any changes in agent locations or changes to inter-agent spacing. • This document addresses Low Power GTL+ layout. Other chassis requirements including cooling, mechanical stability, and memory location may constrain the system topology and component placement location; therefore constraining the board routing. These issues are not directly addressed in this document.

3.2.4 Estimate Component to Component Spacing for Low Power GTL+ Signals

After determining the general layout, do a more specific preliminary component placement. Estimate the number of layers that will be required. Then determine the expected interconnect distances between the components on the Low Power GTL+ bus. Using the estimated interconnect distances, verify that the placement may support the system timing requirements. Figure 6. Pentium® III Processor- Low Power Component Placement Example

Pentium® III Pocessor– Low Power

GTL+ Bus PCI Bus 82443BX AGP Bus Host Bridge/ Controller Memory Bus

DRAMs

Figure 6 shows one example of a Pentium III processor – Low Power based system component placement.

The maximum network length between the bus agents is determined by the bus frequency and the maximum flight time propagation delay on the PCB. The minimum network length is independent of the required bus frequency. The equations DO NOT allow for any change in the propagation of the signal due to ringback, crosstalk on the network/package, or for any difference in buffer

Design Guide 25 Intel® Pentium® III Processor – Low Power/440BX AGPset

performance caused by driving actual loaded transmission lines instead of test loads that are used in the component specification. Intel suggests running analog simulations to ensure that each design has adequate noise and timing margin.

After the board layout is complete, extract real trace lengths and run analog simulations to verify the actual layout meets the timing and noise requirements.

3.3 Simulation

3.3.1 Overview

Intel strongly suggests running analog simulations for Pentium III processor – Low Power designs. Intel provides the Pentium III processor – Low Power I/O Buffer Models and the 82443BX I/O Buffer Models in IBIS 2.1 format. These models are available from your local Intel Field Sales Representative. Accurate simulations require that the actual range of parameters be used in the simulations.

Positioning drivers with faster edges closer to the middle of the network results in more noise than positioning them towards the ends. Intel has seen that the worst-case noise margin may be generated by drivers located in all positions (given appropriate variations in the other network parameters). Therefore, stimulating the networks from all driver locations and analyzing each receiver for each possible driver is recommended. Simulate using both values of RTT in the Pentium III processor – Low Power IBIS model.

Faster edge rates cause increased ringback, which reduces the noise margin on the rising edge (Low to High); therefore, only the fast corner (voltage, temperature, and process) I/O buffer model needs to be simulated for the Low to High transitions to evaluate signal quality. Analysis has also shown that both fast and slow models must be run to verify signal quality on the falling edge (High to Low). The fast corner is needed because the fast edge rate creates the most noise. The slow corner is needed because the buffer’s drive capability will be a minimum causing the VOL to shift up, which may cause the noise from the slower edge to exceed the available budget. The slow corner I/O buffer model is used to check the maximum flight time.

The transmission line package models must be inserted between the output of the buffer and the net it is driving. Likewise, the package model must also be placed between a net and the input of a receiver model. This is generally done by editing your simulator's net description or topology file.

3.3.2 Extract Interconnect Information

Extract the actual interconnect information for the board from the CAD layout tools.

3.3.3 Run Simulations

For timing and signal integrity analysis at the Pentium III processor – Low Power connector pins, simulations need to be performed using the fast/slow buffer models, board impedance and the dielectric extreme values, and VTT and RTT extremes. As shown in Equation 3 and Equation 4, both the minimum and maximum lengths need to be simulated.

26 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

± For timing simulations use a VREF voltage of 2/3 VCCT 2% for both the Pentium III processor – Ω Low Power and 82443BX. RTT for the Pentium III processor – Low Power is an idealized 50-65 internal resistor pulled up to VCCT. Flight times measured from the Pentium III processor- Low Power connector pins to other system components use the standard method of subtracting the reference delay with this load from the delay to the destination component at 2/3 VCCT.

3.4 Summary of System Design Guidelines

A quick summary of the board design guidelines presented in Section 3.0 is shown in Table 3.

Table 3. Summary of Board Design Guidelines

Parameter Value Units

Pentium III processor- Low Power to 82443BX Trace length 1.5 – 6.0 inches Trace line impedance 55 +/-10% ohms Trace line width 4 mils Trace line spacing >= 6 mils Breakout from Package 75 mils FR4 dielectric constant 3.9-4.5 n/a Maximum Parallel Routing 3.5 inches Traces Internally Routed (Stripline or Dual-Stripline)

• The Pentium III processor – Low Power has on-die RTT. The RESET# signal needs an off-die Ω ± 56.2 1% resistor pulled-up to VCCT. • The 82443BX GTL+ buffers are programmed for Low Power GTL+ setting (vs. desktop GTL+ choice) by strapping MAB6# high. See the Design Checklist in Section 7.0 for 82443BX strapping options.

Design Guide 27 Intel® Pentium® III Processor – Low Power/440BX AGPset

3.5 Timing Diagram for Processor Side Bus

Figure 7 illustrates the timing concepts for the processor side bus. Figure 7. Processor Side Bus Timing Concepts

Gen N Gen N+1

Tperiod CLK at Driver Vt Vt (Generate) TCO_max TCO_min Signal at Driver Pin Bit N Bit N+1 into Tester load

Signal at Driver Pin Bit N Bit N+1 into Actual board trace

Tclk_offset Tflt_max Tflt_min Sampling Bit N Signal at Setup/Hold Window Bit N+1 Receiver Pin

Tsetup Thold_margin T CLK at Receiver setup_margin Vt Vt T (Sample) hold

28 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

4.0 Memory Guidelines

This section lists guidelines to be followed when routing the signal traces for the board design. The order in which signals are routed first and last will vary from designer to designer. Some designers prefer routing the clock signals first, while others prefer routing the high-speed bus signals first. Either order may be used, as long as the guidelines listed here are followed. When the guidelines listed here are not followed, it is very important to simulate the design. Even when the guidelines are followed, it is recommended that you simulate these signals for proper signal integrity, flight time and cross talk.

4.1 100 MHz SDRAM Interface Overview

The 82443BX integrates a main memory DRAM controller that supports a 64-bit or 72-bit (64 bit memory data plus 8 bit ECC) DRAM array for 100 MHz embedded environments. A Pentium® III processor – Low Power/440BX system supports Synchronous DRAM (SDRAM); it does not support EDO memory. The 82443BX DRAM interface runs at 100 MHz. The DRAM controller interface is fully configured through a set of control registers. Complete descriptions of these registers are given in the Intel® 440BX AGPset: 82443BX Host Bridge/Controller Datasheet (order number 290633).

The 443BX supports industry standard 64-bit wide 144-pin SODIMM modules with SDRAM devices. Both symmetric and asymmetric addressing is supported. For write operations of less than a Qword in size, the 443BX will either perform a byte-wide write cycle (non-ECC protected configuration) or a read-modify-write cycle by merging the write data on a byte basis with the previously read data (ECC or error correction configurations). The 82443BX requires SDRAM with CAS latency of 2 (CL2), and supports 1-and 2-row SODIMMs. The 82443BX provides refresh functionality with programmable rates (normal DRAM rate is 1 refresh/15.6 µs). The 82443BX may be configured through the paging policy register to keep multiple pages open within the memory array. Pages may be kept open in all rows of memory. When using two bank SDRAM devices in a particular row, up to two pages may be kept open within that row.

The DRAM interface of the 82443BX is configured by the DRAM control registers, DRAM timing register, SDRAM control register, bits in the NBXCFG register and the eight DRAM row boundary (DRB) registers. The DRAM configuration registers control the DRAM interface to select EDO or SDRAM, RAS timing, and CAS rates. The eight DRB registers define the size of each row in the memory array, enabling the 82443BX to assert the proper CSA[7:0]#, CSB[7:0]# pair for accesses to the array.

Design Guide 29 Intel® Pentium® III Processor – Low Power/440BX AGPset

4.1.1 SDRAM Signal Description

The following sections explain which signals are used in applied computing platforms, and how they should be connected. Note that MAB[13,10] are not inverted because these address bits are used to define various SDRAM commands.

Table 4 identifies the SDRAM signals and the corresponding description.

Table 4. SDRAM Signal Descriptions

Name Type Voltage Description

I/O Memory ECC Data: These signals carry Memory ECC data MECC[7:0]1 V_3 CMOS during access to DRAM.

O Chip Select (SDRAM): These pins activate SDRAM. SDRAM CSA[5:0]# V_3 CMOS accepts any command when its CS# pin is active low.

O Input/Output Data Mask (SDRAM): These pins act as DQMA[7:0] V_3 synchronized output enables during a read cycle and as a byte CMOS mask during a write cycle. Memory Address (SDRAM): This is the row and column address MAB[9:0]# for DRAM. The 443BX Host Bridge system controller has two MAB[10]2 O identical sets of address lines (MAA and MAB#). The V_3 recommendations in this design guide are based on the use of MAB[12:11]# CMOS only one set of address lines. For additional addressing features, MAB[13]2 please refer to the Intel® 440BX AGPset: 82443BX Host Bridge/ Controller Datasheet (order number 290633).

O Memory Write Enable (SDRAM): MWEA# should be used as the MWEA# V_3 CMOS write enable for the memory data bus.

O SDRAM Row Address Strobe (SDRAM): When active low, this SRASA# V_3 signal latches Row Address on the positive edge of the clock. This CMOS signal also allows Row access and pre-charge.

O SDRAM Column Address Strobe (SDRAM): When active low, SCASA# V_3 this signal latches Column Address on the positive edge of the CMOS clock. This signal also allows Column access.

O SDRAM Clock Enable (SDRAM): The SDRAM clock enable pin. CKE[5:0] V_3 When these signals are deasserted, SDRAM enters power-down CMOS mode. Each row is individually controlled by its own clock enable.

I/O Memory Data: These signals are connected to the DRAM data MD[63:0] V_3 CMOS bus. NOTES: 1. MECC[7:0] signals on the 82443BX may be left unconnected if the design does not support ECC. For information regarding DIMM memory designs using ECC, refer to the Intel 440BX AGPset design guide. 2. MAB[13,10] signals are not inverted because these address bits are used to define various SDRAM commands.

30 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

4.1.2 SDRAM Signal Connectivity

The DRAM expansion socket is a 144-pin SO-DIMM. Table 5 identifies the SDRAM signals and the corresponding SO-DIMM pins. Table 6 identifies the 82443BX SDRAM signals and the corresponding onboard SDRAM signals.

Table 5. SDRAM Signals and Corresponding SO-DIMM Pins

Signal Name SO-DIMM Pin

MAB[11]# 106 MAB[12]# 70, 110 MAB[13] 72, 112

Table 6. 82443BX SDRAM Signals and Corresponding Onboard SDRAM Signals

Signal Name SDRAM Component Pin

MAB[11]# A13/BA0 MAB[12]# A12/BA1 MAB[13] A11

4.1.3 Pin Groups

The 82443BX has multiple copies of many of the signals interfacing to memory. However, the recommendations in this design guide are based on only a single copy of the memory signals. See “Single Set DRAM Interface” on page 32 for more information. The interface consists of the following pins:

Multiple copies:

MAA[13:0], MAB[12:11,9:0]# and MAB[13, 10] CSA[7:0]#, CSB[7:0]# SRASA#, SRASB# SCASA#, SCASB# WEA#, WEB# DQMA[7:0], DQMB[5:1]

Single copies:

CKE[5:0] (for three SODIMM configuration) MD[63:0] MECC[7:0] GCKE (for four DIMM configuration) FENA (FET switch control for four DIMM configuration)

Two CS# lines are provided per row. These are functionally equivalent. The extra copy is provided for loading reasons. The two SRAS#, SCAS# and WE# pins are also functionally equivalent and each copy drives two rows of DRAM. Most pins use programmable strength output buffers. When a row contains 16-Mbit SDRAMs, MAA11 and MAB11# function as Bank Select lines. When a row contains 64-Mbit SDRAMs, MAA[12:11], MAB[12:11] function as Bank Addresses

Design Guide 31 Intel® Pentium® III Processor – Low Power/440BX AGPset

(BA[1:0], or Bank Selects). When the design does not support ECC, you may leave MECC[7:0] unconnected. When the design supports ECC, perform simulations to determine which buffer strength is needed for loading requirements. This may require a BIOS change.

4.1.4 Single Set DRAM Interface

The following two sections explain which signals are used in embedded platforms. Note that MAB[13,10] are not active low because these address bits are used to define various SDRAM commands.

4.1.4.1 SDRAM

Single copies used:

MAB[12:11,9:0]# and MAB[13,10] MD[63:0] MECC[7:0] CSA[5:0]# DQMA[7:0] CKE[5:0] SRASA# SCASA# WEA#

4.2 General SDRAM Layout Guidelines

The following list identifies the SDRAM layout guidelines: 1. To obtain the most advantageous system electronics board layout, byte lanes may be swapped. Bits within a byte lane may also be swapped. However, bits between byte lanes may not be swapped. 2. A system electronics board nominal trace width should have an impedance of 55 Ω ± 10%. Impedance of a nominal trace width is a key parameter specified to board fabricators. Typically, nominal trace width is constrained by design density, the substrate material, and the board fabrication process. Common trace widths are 4 mils, 5 mils, and 6 mils. 3. All resistors should have a maximum ± 5% tolerance. 4. Populate the furthest SO-DIMM first to avoid stub reflections. 5. Any onboard memory should replace the furthest SO-DIMM socket. 6. Place onboard DRAM and SO-DIMM connectors as near as possible to each other. 7. CKBF-M should be powered by V_3 (the 3.3 V rail power supply which remains on during Suspend).

4.2.1 SO-DIMM Connection to SDRAM

Guidelines for the following memory configurations are provided: three SO-DIMM sockets, two SO-DIMM sockets, or two SO-DIMM sockets with onboard memory. For memory configurations with onboard memory, the onboard memory routing may be treated as a third SO-DIMM. For

32 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

example, the onboard memory is routed to a place on the board where a third SO-DIMM connector would otherwise be placed. In this document, the space is identified as a ‘virtual’ SO-DIMM connector. See Figure 8 for more detail.

The ‘virtual’ SO-DIMM connector is not a physical component but a design reference point (placeholder). Figure 8. SDRAM Connections

Virtual Connector CSA[1:0]# CSA[3:2]# CSA[5:4]#

PC-100 SDRAMs SRASA#

SCASA# Intel 82443BX Host Bridge/ DQMA[7:0] Controller WEA#

MAB[12:11, 9:0]#, MAB[13, 10] MD[63:0] 10Ω

CKE[5:4] CKE[3:2] CKE[1:0] Follow the 66/100 MHz SO-DIMM specification to route the signals SO-DIMM2 SO-DIMM1 SO-DIMM0

Replace the last slot by onboard memory

Follow the 100-MHz layout and routing guidelines

Design Guide 33 Intel® Pentium® III Processor – Low Power/440BX AGPset

4.3 Trace Lengths for Three or Two SO-DIMM Designs

The figures and tables below show the topology, and provide the minimum and maximum trace lengths to the SODIMM connector pads for each signal group in a three or two SO-DIMM design.

4.3.1 MD[63:0] Signals

Figure 9 and Table 7 list the three SO-DIMM socket trace lengths and illustrates the corresponding topology. Figure 9. MD[63:0] Topology, Three SO-DIMM Sockets

L0 L1 L2 L3

82443BX Host Bridge/ SO-DIMM Controller PAD

Table 7. MD[63:0] Topology, Three SO-DIMM Sockets - Section Tolerances

Minimum Maximum Section (inches) (inches)

L0 0.0 in 1.00 in L0+L1 1.1 in N/A L2+L3 0.0 in 2.75 in L0+L1+L2+L3 1.1 in 4.25 in

Figure 10 and Table 8 list the two SO-DIMM socket trace lengths and illustrates the corresponding topology. Figure 10. MD[63:0] Topology, Two SO-DIMM Sockets

L0 L1 L2

82443BX Host Bridge/ SO-DIMM Controller PAD

34 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

Table 8. MD[63:0] Topology, Two SO-DIMM Sockets - Section Tolerances

Minimum Maximum Section (inches) (inches)

L0 0.0 in 1.0 in L0+L1 1.1 in N/A L0+L1+L2 1.1 in 6.0 in

4.3.2 DQMA[7:0] Signals

Figure 11 and Table 9 list the three SO-DIMM trace lengths and illustrates the corresponding topology. Figure 11. DQMA [7:0] Topology, Three SO-DIMM Sockets

L0 L1 L2 L3

82443BX Host Bridge/ Controller SO-DIMM PAD

Table 9. DQMA [7:0] Topology, Three SO-DIMM Sockets, Section Tolerances

Minimum Maximum Section (inches) (inches)

L0 1.0 N/A L0+L1+L2 1.0 4.0

Figure 12 and Table 10 list the two SO-DIMM trace lengths and illustrates the corresponding topology. Figure 12. DQMA [7:0] Topology, Two SO-DIMM Sockets

L0 L1

82443BX Host Bridge/ Controller SO-DIMM PAD

Table 10. DQMA [7:0] Topology, Two SO-DIMM Sockets - Section Tolerances

Minimum Maximum Section (inches) (inches)

L0 1.0 N/A L0+L1 1.0 6.0

Design Guide 35 Intel® Pentium® III Processor – Low Power/440BX AGPset

4.3.3 Chip Select Signals - CSA[5:0]

Figure 13 and Table 11 list the Chip Select signals and illustrates the corresponding topology. Figure 13. CSA [5:0] Topology

82443BX Host Bridge/ L0 SO-DIMM Controller PAD

Table 11. CSA[5:0] Topology - Section Tolerances

Minimum Maximum Section (inches) (inches)

L0 1.0 6.0

4.3.4 Clock Enable Signals - CKE[5:0]

Figure 14 and Table 12 list the Clock Enable signals and illustrates the corresponding topology. Figure 14. CKE[5:0] Topology

82443BX Host Bridge/ L0 SO-DIMM Controller PAD

Table 12. CKE[5:0] Topology - Section Tolerances

Minimum Maximum Section (inches) (inches)

L0 1.0 6.0

36 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

4.3.5 Command Signals - MAB[13:0]x, WEA#, SRASA#, and SCASA

Figure 15 and Table 13 list the three SO-DIMM trace lengths for the command signals and illustrate the corresponding topology. Figure 15. Command Signals Topology, Three SO-DIMM

L0 L1 L2

82443BX Host Bridge/ Controller SO-DIMM PAD

Table 13. Command Signals Topology, Three SO-DIMM - Section Tolerances

Minimum Maximum Section (inches) (inches)

L0 1.0 N/A L0+L1+L2 1.0 6.0

Figure 16 and Table 14 list the two SO-DIMM trace lengths for the command signals and illustrates the corresponding topology. Figure 16. Command Signals Topology, Two SO-DIMM

L0 L1

82443BX Host Bridge/ Controller SO-DIMM PAD

Table 14. Command Signals Topology, Two SO-DIMM - Section Tolerances

Minimum Maximum Section (inches) (inches)

L0 1.0 N/A L0+L1 1.0 6.0

Design Guide 37 Intel® Pentium® III Processor – Low Power/440BX AGPset

4.4 SODIMM DRAM Organization

The 144-pin SODIMM (one inch height) has a maximum capacity of eight devices and provides the following configuration possibilities (see Table 15) for SDRAM.

Table 15. SODIMM DRAM Organization

SODIMM Component Devices Mbyte per Technology Organization Organization per Row SODIMM

16 Mbit 1 M x 64 / S 1 M x 16 4 8 Mbyte 2 M x 64 / D 1 M x 16 4 16 Mbyte 2 M x 64 / S 2 M x 8 8 16 Mbyte 64 Mbit 2 M x 64 / S 2 M x 32 2 16 Mbyte 4 M x 64 / D 2 M x 32 2 32 Mbyte 4 M x 64 / S 4 M x 16 4 32 Mbyte 8 M x 64 / D 4 M x 16 4 64 Mbyte 8 M x 64 / S 8 M x 8 8 64 Mbyte 128 Mbit 16 M x 64 /S 8 M x 16 4 128 Mbyte NOTE: ‘S’ denotes single-sided SODIMMs; ‘D’ denotes double-sided SODIMMs.

38 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

4.4.1 SDRAM System Examples

Table 16 lists five system examples. Each example is based on using three SODIMM sockets or one on-board DRAM and two SODIMM sockets. The terms used in Table 16 are defined below:

144 SODIMM: Number of SODIMM sockets plus on-board DRAM Row: RAS[5:0]# or CS[5:0]# connection. Technology: DRAM technology 16 Mbit, 64 Mbit, 128 Mbit Density/Width: DRAM configuration 16 Mbit: 2 M x 8, or 1 M x 16 64 Mbit: 8 M x 8, 4 M x16, or 2 M x 32 128 Mbit: 8 M x 16, or 16 M x 8 # Devices/Row: Number of DRAM components per row.

Table 16. SDRAM System Examples

144 Mbytes per Row Technology Density x Width # Devices/Row SODIMM SODIMM

Example #1

#1 or on-board 0 16 Mbit 2 M x 8 8 16 Mbytes 1 16 Mbit 1 M x 16 4 8 Mbytes #2 2 16 Mbit 1 M x 16 4 8 Mbytes #3 3 16 Mbit 2 M x 8 8 16 Mbytes Total 4 24 48 Mbytes

Example #2

#1 or on-board 0 16 Mbit 2 M x 8 8 16 Mbytes #2 1 16 Mbit 2 M x 8 8 16 Mbytes #3 2 16 Mbit 2 M x 8 8 16 Mbytes Total 3 24 48 Mbytes

Example #3

#1 or on-board 0 16 Mbit 2 M x 8 8 16 Mbytes #2 1 64 Mbit 8 M x 8 8 64 Mbytes #3 2 64 Mbit 4 M x 16 4 32 Mbytes Total 3 20 112 Mbytes

Example #4

#1 or on-board 0 64 Mbit 8 M x 8 8 64 Mbytes #2 1 64 Mbit 8 M x 8 8 64 Mbytes #3 2 64 Mbit 8 M x 8 8 64 Mbytes Total 3 24 192 Mbytes

Example #5

0 128 Mbit 8 M x 16 4 64 Mbytes #1 or on-board 1 128 Mbit 8 M x 16 4 64 Mbytes 2 128 Mbit 8 M x 16 4 64 Mbytes #2 3 128 Mbit 8 M x 16 4 64 Mbytes 4 128 Mbit 8 M x 16 4 64 Mbytes #3 5 128 Mbit 8 M x 16 4 64 Mbytes Total 6 24 384 Mbytes

Design Guide 39 Intel® Pentium® III Processor – Low Power/440BX AGPset

4.5 SO-DIMM Placement Options

There are many ways to place the SO-DIMMs on the system electronics. The following diagrams illustrate a few of the possibilities. The dotted outline indicates the SO-DIMM socket is on the other side of the board. In all the configurations, the last SO-DIMM (SODIMM0) slot may be replaced by on-board memory. Figure 17. Three SO-DIMM Slots on One Side (First Two Back-to-Back)

SODIMM2 SODIMM1 SODIMM0

82443BX Host Bridge Controller

Figure 18. Two SO-DIMM Slots Back-to-Back, Third Slot on the Other Side

SODIMM2 SODIMM1

82443BX Host Bridge/ Controller

SODIMM0

40 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

Figure 19. Two SO-DIMM Slots on One Side, Third Slot on the Other Side

SODIMM2 SODIMM0

82443BX Host Bridge/ Controller

SODIMM1

Figure 20. Two SO-DIMM Slots on One Side, Third Slot on the Other Side (Alternate Method)

SODIMM2 SODIMM1

82443BX Host Bridge/ Controller

SODIMM0

Design Guide 41 Intel® Pentium® III Processor – Low Power/440BX AGPset

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42 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

5.0 Clocking Guidelines

This section lists guidelines to be followed when routing the signal traces for the board design. The order in which signals are routed will vary from designer to designer. Some designers prefer routing all of the clock signals first, while others prefer routing the high-speed bus signals first. Either order may be used, as long as the guidelines listed here are followed. When the guidelines listed here are not followed, it is very important to simulate the design. Even when the guidelines are followed, it is recommended that you simulate signals for proper signal integrity, flight time and cross talk.

5.1 Clocking System Overview

This section provides guidelines and application information for clock layout in a Pentium® III processor – Low Power/440BX AGPset system. These guidelines are based on the HCLK, PCICLK and SDRAMCLK requirements and should be implemented along with the application instructions supplied by your clock chip vendor. Figure 21 shows the clock synthesizer connection to the processor, 82443BX, PIIX4E, and SDRAM.

S Figure 21. Clock Connections to the Intel® Pentium® III Processor — Low Power and 440BX Chipset

Intel® Pentium® III processor - Clock Low Power Synthesizer BCLK

BCLK 2.5V 100MHz

HCLKIN DCLK DCLKWR SDRAM 82443BX CLOCK BUFFER PCLK SDRAM

PCLK 3.3V 33MHz

Free running PCI clock

PCLK PIIX4E

Design Guide 43 Intel® Pentium® III Processor – Low Power/440BX AGPset

5.2 Clock Synthesizer Pinout and Specifications

A clock synthesizer that meets the CK97 Clock Synthesizer Design Guidelines (order number 243867) will meet the requirement for a Pentium III processor – Low Power/440BX AGPset-based system. Table 22 lists clock vendors that provide clock synthesizers which meet the CK97 Clock Synthesizer Design Guidelines.

Note: The CK100-M compatible clock synthesizer operates in multi-voltage mode. The processor clocks operate at 100 MHz at 2.5 V, and the PCI clocks operate at 33 MHz at 3.3 V. The CKBF-M compatible clock buffer provides clocks for SDRAM operating at 100 MHz at 3.3 V. See Figure 22 and Figure 23 for more details. Figure 22. Pinout for CK100-M Compatible Clock Synthesizer

XTAL_IN 1 28 Vssref XTAL_OUT 2 27 Vddref Vsspci0 3 26 REF PCICLK_F 4 25 Vddcpu PCICLK1 5 24 CPUCLK0 Vddpci0 6 CK100-M 23 CPUCLK1 PCICLK2 7 22 Vsscpu PCICLK3 8 21 Vddcore1 Vddpci1 9 20 Vsscore1 PCICLK4 10 19 PCISTOP# PCICLK5 11 18 CPUSTOP# Vsspci1 12 17 PWRDWN# Vddcore0 13 16 SEL Vsscore0 14 15 SEL100/66#

Figure 23. Pinout for CKBF-M Compatible Clock Buffer

Vdd0 1 28 Vdd9 Sdram0 2 27 Sdram15 Sdram1 3 26 Sdram14 Vss0 4 25 Vss9 Vdd1 5 24 Vdd8 Sdram2 6 23 Sdram13 Sdram3 7 CKBF-M 22 Sdram12 Vss1 8 21 Vss8 buf in 9 20 OE Vdd4 10 19 Vdd5 Sdram16 11 18 Sdram17 Vss4 12 17 Vss5 Vddiic 13 16 Vssiic Sdata 14 15 Sclock

44 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

5.3 Timing Guidelines

Figure 24 shows a simplified clocking layout for the timing specifications. See Table 17 for the clock skews. Figure 24. Timing Specifications Layout

Intel® Pentium ® III processor - Low AGP Device Power C A 82443BX GCLKIN Host Bridge Controller GCLKO SODIMM HCLKIN DCLKWR SDRAM F Component DCLKO PCLKIN D

Clock Clock E Buffer Synthesizer

PCI Device

E PCI Device

Table 17. Timing Specifications for Maximum and Minimum Clock Skews

CK100-M Symbol Description Boards Total pin to pin

CPU (BCLK) to 0 ps (max) 1 250 ps (max) 3 250 ps (max) 3 A 82443BX (HCLKIN) skew 0 ps (min) 1 -250 ps (min) 3 -250 ps (min) 3 AGP device (GCLK) to 100 ps (max) 100 ps (max) C N/A 82443BX (HCLKIN) skew -100 ps (min) - 100 ps (min) 82443BX (HCLKIN) to 4.0 ns (max.) 2 1.0 ns (max.) 5.0 ns (max.) D PCI (PCLK) skew 1.5 ns (min.) 0 ns (min.) 1.5 ns (min.) PCI (PCLK) to 500 ps (max) 1.5 ns (max) 2.0 ns (max) E PCI (PCLK) skew -500 ps (min) -1.5 ns (min) - 2.0 ns (min) DCLKWR to 250 ps (max) 380 ps (max) 4 630 ps (max) F SDRAM (SCLK) skew -250 ps (min) -380 ps (min) 4 - 630 ps (min) NOTES: 1. In a Pentium® III processor – Low Power based design, use the same clock output pin for both the 82443BX HCLK input and the processor clock input in a ‘T’ signal trace configuration. 2. The 82443BX PCICLK input should lag its HCLK input by a minimum of 1.5 ns to a maximum of 4.0 ns at the pins of the CK100-M device. An integrated buffer will offer the best control over these output to output drive skews. 3. The total allowable CPU(BCLK) to 82443BX(HCLKIN) skew for the Pentium III processor – Low Power is ±250 ps. 4. This skew allowance includes ±280 ps for I/O capacitance and SODIMM routing variation. Motherboards should be designed to allow for no more than ±100 ps contribution to the total skew.

Design Guide 45 Intel® Pentium® III Processor – Low Power/440BX AGPset

Note: .Clock period, jitter, offset and skew are measured on the rising edge of the clock signals at 1.25 V for the 2.5 V clocks and at 1.5 V for the 3.3 V clocks.

5.4 Host Clock Layout Guidelines

The following list provides Host Clock guidelines for a Pentium III processor – Low Power design: 1. The trunk trace length (from clock driver output pin to T-split) may range from 2.0 inches to 4.5 inches, with the entire length at an 8-mil trace width. (8-mil trace width on a layer where a 4-mil trace is nominally 55 Ω.) 2. Clocks must be routed on the same layer internally to contain EMI. Space all other signals at least 2 W from clock traces. 3. A series resistor at the clock driver is 22Ω ±5% tolerance, placed as near to the driver pin as possible (up to 0.5 inches). Intel recommends that the clock series resistors not be placed in the R-packs to allow individual tunability if necessary. 4. Minimize the vias on all clock traces. 5. Do not allow the clock traces to cross a plane split.

Table 18. Host Clock Trace Length Guidelines

Minimum Trace Length Maximum Trace Length Variable Trace Width Resistor (inches) (inches)

A 8 mil 2.0 in 4.5 in 22 Ω ± 5% J 4 mil 1.25 in 1.35 in N/A K 4 mil J + 0.876 in J + 0.878 in N/A

NOTE: Table 18 refers to a board where characteristic impedance is nominally 55 Ω ± 10% at 4 mils.

The Host Clock should be routed in an unbalanced ‘T’ topology. Route the branches of the ‘T’ in 4-mil wide traces and route the trunk of the ‘T’ in an 8-mil wide trace. Place the trunk of the ‘T’ such that the Pentium III processor – Low Power branch is equal to the BX branch + 0.877. Figure 25. Host Clock Topology

Intel® Pentium® III Processor – Low Power

K BCLK 4 mil

Clock A Generator 8 mil 82443BX Host Bridge/ Controller

J HCLKIN 4 mil

A8986-01

46 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

5.5 SDRAM Clock Layout Guidelines

This section defines the clock lengths and series termination for 100-MHz SDRAM clocks.

5.5.1 General Clocking Guidelines

The goal of the SDRAM clock guidelines is to route all SDRAM clock signals as near to the same length as possible, not deviating more than 0.2 inches from maximum to minimum.

The following list provides design considerations for the SDRAM clocks. 1. Series termination resistors are required. Place them as close to the driver pin as possible (within 1 inch). 2. Route all SDRAM clocks and DCLKWR on the same internal layer to provide better trace delay consistency as well as EMI containment. 3. A system electronics board nominal trace width should have an impedance of 55 Ω ± 10%. Impedance of a nominal trace width is a key parameter specified to board fabricators. Typically, nominal trace width is constrained by design density, the substrate material, and the board fabrication process. Common trace widths are 4 mils, 5 mils, and 6 mils. 4. Minimize the use of vias in clock signals. 5. All clocks should have 1:2 width-to-spacing ratio. 6. A zero delay buffer should not be used in place of the CKBF-M.

Design Guide 47 Intel® Pentium® III Processor – Low Power/440BX AGPset

5.5.2 SDRAM Clock Layout Guidelines

Figure 26 shows the SDRAM clock layout guidelines and Table 19 provides the measurement values. Figure 26. Clocking Layout Diagram

Follow the B2 SO-DIMM 82443BX DCLKWR Specification Onboard Host SDRAM Bridge/ C1 Controller D Onboard buf_in B1 SDRAM DCLK0 Onboard “Virtual” SDRAM Pad CKBF-M Onboard SDRAM B1 B1max SO-DIMM 0 B1nom

B1min B1 SO-DIMM 1

NOTES: 1. B1 represents memory SDRAM clock signals. 2. B1max represents the “Maximum” SDRAM clock trace length. 3. B1nom represents an imaginary “Nominal” SDRAM clock trace length. 4. B1min represents the “Minimum” SDRAM clock trace length.

Intel recommends the following guidelines for SDRAM clock trace length design. The terms used in Figure 26 are mathematically defined as follows: 1. SDRAM clock trace lengths should not differ in length from maximum to minimum by more than 0.2 inches. This means that the longest SDRAM clock trace length (B1max) minus the shortest SDRAM clock trace length (B1min) should be within 0.2 inches of each other; ≤ B1max - B1min 0.2 inches.

2. B1nom is an imaginary target nominal SDRAM clock trace length that is centered in length between the maximum and the minimum SDRAM clock lengths. This is defined as:

B1max - B1min B1 = B1 + nom min 2

3. B1= B1nom ± 0.1 inches (maximum = B1nom + 0.1 in, minimum = B1nom - 0.1 in).

4. B2 = DCLKWR = B1nom + 2.5 inches ± 0.1 inches (maximum = B1nom + 2.6 in, minimum = B1nom + 2.4 in).

48 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

Table 19. SDRAM Clocks and DCLK Trace Lengths

Variable Trace Zo Trace Length (min) Trace Length (max) Resistor

B1nom N/A 0.0 in 0.0 mm 4.0 in 101.6 mm N/A B1 - 0.1 B1 - 2.5 B1 55 Ω ± 10% nom nom B1 + 0.1 in B1 + 2.5 mm 10 Ω ± 5% in mm nom nom B1 + 2.4 B1 + 61 B2 55 Ω ± 10% nom nom B1 + 2.6 in B1 + 66.0 mm 22 Ω ± 5% in mm nom nom D 55 Ω ± 10% 0.0 in 0.0 mm 4.0 in 101.6 mm 18 Ω ± 5% Use a 0603 package size with an NPO or C0G dielectric and place it within 0.2 C1 15 pF ± 5% inches of the resistor. Route from the resistor pad through the capacitor pad and then into the via going into the system electronics board.

Design Guide 49 Intel® Pentium® III Processor – Low Power/440BX AGPset

5.5.3 DCLKWR Layout Guidelines

Intel recommends that a capacitor be added to the system electronics on the DCLKWR signal. Notebook designers should use a capacitor value that will minimize the skew between the SDRAM clocks and the Intel 82443BX component. The capacitor should be placed no more than 0.2 inches from the 22-Ω series dampening resistor. Intel recommends using the topology shown in Figure 27. This allows the capacitor to be removed from a design without creating an open-ended stub on DCLKWR. See Table 20 for section tolerances. 1. Series matching resistors are required. Placement: As near to the driver pin as possible (within 1 inch). 2. Route all clocks on internal layers to provide better trace delay consistency as well as EMI containment. 3. Board impedance should be 55 Ω ± 10%. 4. Minimize the use of vias in clock signals. 5. All clocks should have 1:2 width to spacing ratio. Figure 27. DCLKWR (Figure 16, Variable B2) Guidelines

22 Ω CKBF-M L1

Pads L2

82443BX L3 Host Bridge/ Controller New Capacitor

A8985-01

Table 20. DCLKWR Guidelines - Section Tolerances

Minimum Maximum Section (inches) (inches)

L1 0.0 1.0 L2 0.0 0.2 L3 N/A N/A

L1+L2+L3 B1nom +2.4 in B1nom +2.6 in

50 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

5.6 PCI/AGP Clock Layout Guidelines

Note: Figure 28 assumes AGP and PCI devices are ‘down’ on the motherboard and not on a connector. When designing a board that will use connectors to add AGP or PCI devices, be sure to take into account the trace length already routed on the AGP or PCI card. PCI cards have a PCI CLK trace length of 2.5 inches. AGP cards have an AGP CLK trace length of approximately 3.3 inches.

Figure 28. PCI and AGP Clocking Layout

E 82443BX GCLKO Host Bridge/ F Controller GCLKIN AGP Device F

K PCL

CK100-M

C1 3.3V 33MHz C2 PCICLK_F OTHER PCI DEVICES 82371EB PIIX4E

Table 21. PCI and AGP Clock Trace Length

Trace Minimum Trace Maximum Trace Resistor Variable Tolerance Width Length Length Value A+J+4 inch C 5 mil A+J 33 Ω ± 5% 1 (A+J+101.6 mm) ± 4.5 inch C 5 mil C C 33 Ω ± 5% 2 1 1 (± 114.3mm) 0 inch 1 inch E 10 mil None (0 mm) (25.4 mm) 0 inch 8.5 inch F5 mil 18 Ω ± 5% (0 mm) (215.9 mm) NOTE: Tolerance refers to the allowed difference in length between multiple traces sharing the same variable name.

Design Guide 51 Intel® Pentium® III Processor – Low Power/440BX AGPset

5.7 Clock Vendors

This vendor list is provided as a service to our customers for reference only. The inclusion of this list should not be considered a recommendation or product endorsement by Intel Corporation.

Table 22. Clock Vendors

Vendor Name Address

525 Los Coches Street Milpitas, CA 95035 International Microcircuits, Inc. (408) 263-6300 http://www.imicorp.com 1271 Parkmoor Avenue San Jose, CA 95126-3448 Integrated Circuit Systems, Inc. (408) 925-9493 http://www.icst.com 12020 113th Ave. Northeast Kirkland, WA 98034 Cypress Semiconductor (425) 398-3400 http://www.cypress.com

52 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

6.0 82443BX AGP Interface Guidelines

This section lists guidelines to be followed when routing the signal traces for the board design. Even when the guidelines are followed, it is recommended that you simulate as many signals as possible for proper signal integrity and cross talk. See Section 7.3.5 for AGP pull-up requirements. See Section 5.0, “Clocking Guidelines” on page 43 for AGP clocking information.

6.1 Layout and Routing Guidelines

For the definition of AGP interface functionality (protocols, rules and signaling mechanisms, and the platform level aspects of AGP functionality), refer to the latest AGP Interface Specification and AGP Platform design guide. This document focuses only on specific 440BX platform recommendations for the AGP interface.

Throughout this section the term ‘data’ refers to G_AD[31:0], G_C/BE[3:0]# and SBA[7:0]. The term ‘strobe’ refers to AD_STB[B:A] and SB_STB. When the term ‘data’ is used, it is referring to one of three groups of data as indicated in Table 23. When the term ‘strobe’ is used it is referring to one of the three strobes as it relates to the data in its associated group.

Table 23. Data and Associated Strobe

Data Associated Strobe

G_AD[15:0] and G_C/BE[1:0]# AD_STBA G_AD[31:16] and G_C/BE[3:2]# AD_STBB SBA[7:0] SB_STB

Design Guide 53 Intel® Pentium® III Processor – Low Power/440BX AGPset

6.1.1 On-board AGP Compliant Device Layout Guidelines

Longer trace lengths require a greater amount of spacing between traces in order to reduce crosstalk. When using 1:2 spacing, maximum trace length of data lines is 9.5 inches. The line length mismatch is 0.5 inches. The strobe is the longest trace of the group. This restricts the maximum trace length of data lines to less than 4.5 inches for a 1:1 trace spacing. The strobe requires a 1:2 trace spacing. Trace length guidelines given in this section do not reflect signal integrity and EMI. It is recommended that you simulate the routes to ensure that signal quality requirements are met. See Figure 29 for the AGP compliant device layout guidelines and Figure 30 for signal layout recommendations. Figure 29. On-board AGP Compliant Device Layout Guidelines

1.0”-4.5” 1:1 Data Routing Always 1:2 Strobe Routing AGP 82443BX Compliant Host Bridge/ Graphics Controller Device 1.0”-9.5” 1:2 Data Routing Always 1:2 Strobe Routing

Figure 30. Signal Layout Recommendations

1:1 AD Signals

1:2 AD Strobe

1:1 ADAD SignalsSignals

6.1.1.1 Data and Strobe Signal Routing Recommendations

Table 24. Motherboard Recommendations

Width:Space Trace Line Length Line Length Matching

1:1(Data)/1:2(Strobe) Data /Strobe 1.0 in < line length < 4.5 in 0.5 in, strobe longest trace 1:2 Data/Strobe 1.0 in < line length < 9.5 in 0.5 in, strobe longest trace

The line length mismatch must be less than 0.5 inches and the strobe must be the longest signal of the group. For example, if the strobe is at 4.0 inches, the data line may be from 3.5 to 4.0 inches in length. It is best to reduce the line length mismatch wherever possible to ensure added margin. The strobe is always required to have 1:2 trace spacing. It is also best to separate the traces by as much as possible in order to reduce the amount of trace-to-trace coupling.

54 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

Note: Under certain layouts, crosstalk and ground bounce may be observed on the AD_STB signals of the AGP interface. Although Intel has not observed system failures due to this issue, noise margin has been improved by enhancing the AGP buffers on the 82443BX. For new designs, additional margin may be obtained by following AGP layout guidelines.

6.1.1.2 Control Signal Routing Recommendations

Some of the control signals require pull-up resistors to be installed on the motherboard. Pull-up resistors should be discrete resistors, since resistor packs will need longer stub lengths and may violate timing requirements. The stub length to these pull-up resistors must be controlled. The maximum stub length on a strobe trace is < 0.1 inch. The maximum stub trace length on all other traces is < 0.5 inch. See Table 25 for control signal line length recommendations. For pull-up recommendations, see “AGP Interface Signals” on page 66.

Table 25. Control Signal Line Length Recommendations

Width:Space Board Trace Line Length Pull-up Stub Length

1:1 Motherboard Control Signals 1.0 in < line length < 8.5 in < 0.5 in (Strobes < 0.1 in) 1:2 Motherboard Control Signals 1.0 in < line length < 10.0 in < 0.5 in (Strobes < 0.1 in)

6.2 ACPI Compliance Requirements

Based on the Advanced Configuration and Power Interface (ACPI) specification, the AGP graphics device must be ACPI compliant and must implement its self power management circuitry, such as self clock-gating and an idle bus detection mechanism to reduce power. However, in a Pentium® III processor-based platform the AGP device clock is a derivative of the host clock.

When the host clock stops (C3 state - Deep Sleep), the AGP clock also stops. An AGP_BUSY# protocol solves this instantaneous AGP stop clock problem. The AGP graphics device must signal the operating system or the south bridge that it is currently busy and the AGP clock should not be stopped.

The AGP device internally protects its core logic to ensure that an illegal clock will not corrupt the AGP device state. This protection gates the internal clock nets used for the device’s logic from the time STP_AGP# is asserted until it is deasserted. The STP_AGP# signal is an indication that the AGP clock will not be valid for much longer and should be gated off for protection. STP_AGP# should be connected to the PIIX4E’s SUS_STAT1# signal.

The AGP_BUSY# signal indicates that the graphics controller requires the GCLK to be running. This signal should be connected to one of the PIIX4E’s PCIREQ# pins. When the PCIREQ# pin must be shared, it may be logically ORed with one of the PIIX4E’s PCIREQ# inputs. AGP_BUSY# is an open-drain signal from the graphics device and requires a 10 KΩ pull-up resistor.

AGP_SUSPEND# is for AGP devices that support Suspend mode. The AGP_SUSPEND# signal may be connected to the PIIX4E’s SUSB# signal.

Design Guide 55 Intel® Pentium® III Processor – Low Power/440BX AGPset

6.3 AGP IDSEL Routing

An AGP compliant master is composed of a PCI compliant target interface and an AGP compliant master interface. (Optionally the device may also include a PCI compliant master interface when required.) When used in a PCI mode of operation, the AGP device must provide an external IDSEL that is connected to AD16. When the AGP device is designed for exclusive operation on the AGP interface the device does not have an external IDSEL pin, therefore IDSEL does not need to be routed.

56 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

7.0 Design Guideline Checklists

Design checklists provided in this section are intended to be used for schematic reviews of the Pentium® III processor – Low Power/440BX AGPset platform designs. The checklists do not represent the only way to design a system, but do provide recommendations. The system designer should examine the checklist items for correctness. Additional design considerations are also provided.

7.1 Resistor Values

Pull-up and pull-down resister values are system dependent. The appropriate value for your system may be determined from an AC/DC analysis of the pull-up voltage used, the current drive capability of the output driver, input leakage currents of all devices on the signal net, the pull-up voltage tolerance, the pull-up/pull-down resistor tolerance, the input high/low voltage specifications, the input timing specifications (RC rise time), etc. Analysis should be done to determine the minimum and maximum values that may be used on an individual signal. Engineering judgment should be used to determine the optimal value. This determination may include cost concerns, commonality considerations, manufacturing issues, specification and other considerations. See Figure 31 for an example for a pull-up resistor configuration.

A simplistic DC calculation for a pull-up value is: R MAX = (Vcc PU MIN - V IH MIN) / I Leakage MAX R MIN = (Vcc PU MAX - V IL MAX) / I OL MAX Figure 31. Pull-up Resistor Example

VccPU MIN

RMAX

VIH MIN ILeakage MAX

VccPU MAX

RMIN

VIL MAX IOLMAX

Design Guide 57 Intel® Pentium® III Processor – Low Power/440BX AGPset

7.2 Pentium III Processor – Low Power Design Checklist

7.2.1 GTL+ Signals

Table 26. GTL+ Signals

CPU Pin Pin Connection

A[35:3]# A[31:3]#: Connect to 82443BX. A[35:32]#: NO CONNECT ADS# Connect to 82443BX AERR# NO CONNECT AP[1:0]# NO CONNECT BERR# NO CONNECT BINIT# NO CONNECT BNR# Connect to 82443BX BP[3:2]# NO CONNECT BPM[1:0]# NO CONNECT BPRI# Connect to 82443BX BREQ0# Connect to 82443BX pin BREQ0#. Optional 10 Ω pull-down to Vss. D[63:0]# Connect to 82443BX DBSY# Connect to 82443BX DEFER# Connect to 82443BX DEP[7:0] NO CONNECT DRDY# Connect to 82443BX HIT# Connect to 82443BX HITM# Connect to 82443BX LOCK# Connect to 82443BX REQ[4:0]# Connect to 82443BX

RESET# Terminate to VCCT with 56.2 Ω 1% resistor / Connect to 82443BX RP# NO CONNECT RS[2:0]# Connect to 82443BX RSP# NO CONNECT TRDY# Connect to 82443BX

58 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

7.2.2 CMOS Signals

• FERR# is an open-drain signal from the Pentium III processor – Low Power and must be pulled-up to VCCT with a 1.5 KΩ resistor. In addition to this pull-up, external glue logic is needed to convert the 1.5 V signal to 2.5 V or 3.3 V. Figure 32 illustrates the implementation of the glue logic. Figure 32. External Glue Logic

1.5 V 1.5 V 2.5 V or 3.3 V

1.5 KΩ 1KΩ Intel® 82371EB Pentium® III 10 KΩ PIIX4E Processor – Low Power FERR# FERR# 3904

A8987-01

• CMOS open-drain signals should have maximum trace length of five inches. When CMOS undershoot specifications are not met with the recommended pull-ups, stronger pull-ups may be required. Please see the Intel® Pentium® III Processor — Low Power Datasheet (order number 273500) for details on CMOS signal specifications. • Intel recommends that the PWRGOOD signal from the power supply not be connected directly to logic on the board, without first going through a Schmitt trigger type circuitry to square-off and maintain the signal integrity. • To enable Quick Start state: Pull-up SLP# pin on the processor to VCCT with a 1.5 KΩ resistor, pull-up MAB10 on 443BX to 3 V with a 10 KΩ resistor, leave SLP# on PIIX4 unconnected.

Design Guide 59 Intel® Pentium® III Processor – Low Power/440BX AGPset

Table 27. CMOS Signals

CPU Pin Pin Connection

A20M# 1.5 KΩ pull-up to VCCT. Connect to PIIX4E.

1.5 KΩ pull-up to VCCT. Connect to PIIX4E. FERR# For an example of level conversion logic see Figure 32, “External Glue Logic” on page 59

FLUSH# 1.5 KΩ pull-up to VCCT if not used.

IERR# 1.5 KΩ pull-up to VCCT. Connect to error logic. No connect if not used.

IGNNE# 1.5 KΩ pull-up to VCCT. Connect to PIIX4E.

INIT# 1 KΩ pull-up to VCCT. Connect to PIIX4E.

LINT[1]/NMI 1.5 KΩ pull-up to VCCT. Connect to PIIX4E.

LINT[0]/INTR 1.5 KΩ pull-up to VCCT. Connect to PIIX4E.

PICD[1:0] 1 KΩ pull-down to Vss.

PREQ# 1.5 KΩ pull-up to VCCT. Connect to ITP.

PWRGOOD 1.5 KΩ pull-up to 2.5 V. Connect to power sense logic

Ω SLP# 1.5 K pull-up to VCCT. Connect to PIIX4E. Ω SMI# 270 pull-up to VCCT. Connect to PIIX4E. Ω STPCLK# 680 pull-up to VCCT. Connect to PIIX4E.

7.2.3 TAP Signals

CPU Pin Pin Connection

PRDY# 56.2 Ω 1% pull up to VCCT, 240 Ω series resistor to ITP connector

1 KΩ pull-up to VCCT. 47 Ω series resistor to ITP connector; 1 KΩ pull-down if not TCK used.

TDO 150 Ω pull-up to VCCT. Connect to ITP. No connect if not used

TDI 150 Ω pull-up to VCCT. Connect to ITP; 1 KΩ pull-down if not used.

1 KΩ pull-up to VCCT. 47 Ω series resistor to ITP connector; 1 KΩ pull-down if not TMS used. TRST# 1 KΩ pull-down to Vss. Connect to ITP

60 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

7.2.4 Clock Signals

• Ensure that the clock generation logic is at a 2.5-V level (BCLK and PICCLK) and at a 1.5 V level (TCK) into the Pentium III processor – Low Power. • Use discrete resistors for the BCLK signals from the CK100M. Do not mix HCLK, and PCLK signals coming from the CK100M device in resistor packs.

Table 28. Clock Signals

CPU Pin Pin Connection

Connect to 82443BX HCLKIN and CK100M with 22 Ω series resistor at the CK100M BCLK device. See Section 5.0 for clock routing guidelines. PICCLK 1 KΩ pull-down to Vss.

7.2.5 Miscellaneous Signals

Table 29. Miscellaneous Signals

CPU Pin Pin Connection

BSEL0 1 KΩ pull-up to VCCT. BSEL1 1 KΩ pull-down to Vss. EDGCTRLP 110 Ω 1% Pull-down to Vss. GHI# NO CONNECT RTTIMPEDP 56.2 Ω 1% pull-down to Vss

TESTHI 1 KΩ pull-up to VCCT. TESTLO[2:1] 1 KΩ pull-down to Vss. THERMDC NO CONNECT if not used. Otherwise connect to thermal sensor. THERMDA NO CONNECT if not used. Otherwise connect to thermal sensor. For Voltage Regulator’s (VR) that do not contain internal pull-ups use a 10 KΩ VID[4:0] pull-up to 5 V; Connect to VR.

Design Guide 61 Intel® Pentium® III Processor – Low Power/440BX AGPset

7.2.6 Power Pins

Table 30. Power Pins

CPU Pin Pin Connection

Board divider on V CC2.5 or V CC3.3 to create 1.25 V reference with a 0.1 µF CLKREF decoupling capacitor. Resistor divider must be created from 1% tolerance resistors. Do not use VCCT as source voltage for this reference.

Board divider on V CC2.5 or V CC3.3 to create 1.0 V reference with a 0.1 uF decoupling CMOSREF capacitor. Resistor divider must be created from 1% tolerance resistors. Do not use VCCT as source voltage for this reference.

Typically a 4.7 µH inductor in series with VCCT is connected to PLL1 then through a PLL[2:1] series 33µF capacitor to PLL2. Refer to the Intel® Pentium® III Processor – Low Power Datasheet (order number 273500) for more information.

VCC Connect to Voltage Regulator output. For decoupling guidelines see Section 7.2.8

VCCT Connect to Voltage Regulator output. For decoupling guidelines see Section 7.2.8

V REF = 2/3 VCCT. Create with voltage divider made up of 1 KΩ ± 1% and 2 KΩ ± 1% VREF resistors connected to VCCT. Decouple with 3 (min) 0.1 µF high freq. caps close to processor. Vss Tie to GND

7.2.7 NO CONNECT Pins

Table 31. NO CONNECT Pins

CPU Pin Pin Connection

The following pins must be left as NO CONNECTS: A15, A16, A17, C14, D8, D14, NC D16, E15, G2, G4, G5, G18, H3, H4, H5, J5, M4, M5, P3, P4, R2, AA5, AA17, AA19, AC3, AC17, AC20, AD15, AD20 RSVD The following pins must be left as NO CONNECTS: AB19

62 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

7.2.8 Processor Decoupling Requirements

For a processor operating at 700 MHz and above, the following decoupling is recommended. The processor core power plane (VCc) should have 15 0.68 µF 0603 ceramic capacitors (using X7R dielectric for thermal reasons) placed directly under the package using two vias for power and two vias for ground to reduce the trace inductance. Also to minimize inductance, traces to those vias should be 22mils (in width) from the capacitor pads to match the via-pad size (assuming 22-mil pad size). Twenty-four 2.2 µF 0805, X5R mid frequency decoupling capacitors should be placed around the die as close to the die as flex solution allows.

The system bus buffer power plane (VCCT) should have twenty (20) 0.1-µF high frequency decoupling capacitors around the die.

For a processor operating at 650 MHz and below, the following decoupling is recommended. The processor core power plan (VCc) should have twelve (12) 0.1 µF high frequency decoupling capacitors placed underneath the die and twenty seven (27) 0.1 µF mid frequency decoupling capacitors placed around the die as close to the die (< 0.8 inch away) as flex solution allows. The system bus buffer power plane (VCCT) should have 15 0.1-µF high frequency decoupling capacitors no further than 0.25 inch away from the VCCT vias (balls).

7.3 82443BX Design Checklist

7.3.1 Host Interface Signals

Table 32. Host Interface Signals

82443BX Pin Pin Connection

CPURST# Connect to CPU and ITP (240 Ω series resistor) HA[31:3]# Connect to CPU HD[63:0]# Connect to CPU ADS# Connect to CPU BNR# Connect to CPU BPRI# Connect to CPU Connect to CPU. Optional, leave as No Connect if CPU BREQ0# pin is pulled to Vss BREQ0# with a 10 Ω resistor DBSY# Connect to CPU DEFER# Connect to CPU DRDY# Connect to CPU HIT# Connect to CPU HITM# Connect to CPU HLOCK# Connect to CPU HREQ[4:0] Connect to CPU HTRDY# Connect to CPU RS[2:0]# Connect to CPU

Design Guide 63 Intel® Pentium® III Processor – Low Power/440BX AGPset

7.3.2 DRAM (SO-DIMM) Interface Signals

• For standard DIMM SDRAM interface signal guidelines refer to the Intel® 440BX AGPset Design Guide. • MD[63:0] should have 10 Ω series termination resistors for SO-DIMM designs. • Clock signals from the CKBF-M to each SO-DIMM should have 10 Ω series termination resistors. • A zero delay buffer should not be used in place of the CKBF-M.

Table 33. DRAM (SO-DIMM) Interface Signals

82443BX Pin Pin Connection

RASA[5:0]# Connect two CSA[5:0]# signals to each SO-DIMM. /CSA[5:0]# CASA[7:0]# Connect DQMA[7:0]# to each SO-DIMM. /DQMA[7:0]# CKE[5:0] Connect two CKE signals to each SO-DIMM SRASA# Connect SRASA# to each SO-DIMM SCASA# Connect SCASA# to each SO-DIMM MAB[0:9]# Connect to associated address pin of SO-DIMM MAB10 Connect to A10 pin of SO-DIMM MAB11# Connect to SO-DIMM pin #106 MAB12# Connect to SO-DIMM pin #70, #110 MAB13 Connect to SO-DIMM pin #72, #112 WEA# Connect WEA# to each SO-DIMM MD[63:0] 10 Ω series resistor. Connect MD[63:0] to each SO-DIMM 10 Ω series resistor. Connect MECC[7:0] to each SODIMM. Leave as No Connect MECC[7:0] if not used.

64 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

7.3.3 PCI Interface Signals

• The 82443BX supports up to five PCI masters with its REQ[4:0]#/GNT[4:0]# pairs. The PCI bus supports up to ten PCI loads. The 82443BX and the PIIX4E each represent one load; other PCI components soldered on the motherboard add one load each; and each PCI connector adds approximately two loads. A design with four PCI slots and no motherboard devices uses all available PCI loads. When all five REQ[4:0]#/GNT[4:0]# pairs are used, simulation is required to ensure that the PCI Bus Specification, Rev. 2.1, timings are met.

Table 34. PCI Interface Signals

82443BX Pin Pin Connection

AD[31:0] Connect to PCI Slots and PIIX4E. DEVSEL# 2.7 K Ω pull-up to 5 V or 10 KΩ pull-up to 3.3 V. Connect to PCI Slots and PIIX4E. FRAME# 2.7 KΩ pull-up to 5 V or 10 KΩ pull-up to 3.3 V. Connect to PCI Slots and PIIX4E. IRDY# 2.7 ΚΩ pull-up to 5 V or 10 KΩ pull-up to 3.3 V. Connect to PCI Slots and PIIX4E. C/BE[3:0]# Connect to PCI Slots and PIIX4E. PAR Connect to PCI Slots and PIIX4E. PLOCK# 2.7 KΩ pull-up to 5 V or 10 KΩ pull-up to 3.3 V. Connect to PCI Slots. TRDY# 2.7 KΩ pull-up to 5 V or 10 KΩ pull-up to 3.3 V. Connect to PCI Slots and PIIX4E. SERR# 2.7 KΩ pull-up to 5 V or 10 KΩ pull-up to 3.3 V. Connect to PCI Slots and PIIX4E. STOP# 2.7 KΩ pull-up to 5 V or 10 KΩ pull-up to 3.3 V. Connect to PCI Slots and PIIX4E.

7.3.4 PCI Sideband Signals

Table 35. PCI Sideband Signals

82443BX Pin Pin Connection

PHOLD# 10 KΩ pull-up to 3.3 V. Connect to PIIX4E. PHLDA# 10 KΩ pull-up to 3.3 V. Connect to PIIX4E. WSC# NO CONNECT PREQ[4:0] 10 KΩ pull-up to 3.3 V. Connect to PCI Slots. PGNT[4:0] 10 KΩ pull-up to 3.3 V. Connect to PCI Slots.

Design Guide 65 Intel® Pentium® III Processor – Low Power/440BX AGPset

7.3.5 AGP Interface Signals

• To disable AGP, tie MAB9# high using a 10 KΩ pull-up to 3.3 V, connect GCLKO to GCLKIN through an 18 Ω resistor, and ground AGPREF. When AGP is properly disabled, all AGP signals are tri-stated and isolated; no termination is needed.

Table 36. AGP Interface Signals

82443BX Pin Pin Connection

PIPE# 8.2 KΩ pull-up to 3.3 V. Connect to AGP connector. SBA[7:0] Connect to AGP connector. RBF# 8.2 KΩ pull-up to 3.3 V. Connect to AGP connector. ST[2:0] Connect to AGP connector. ADSTB_A 8.2 KΩ pull-up to 3.3 V. Connect to AGP connector. ADSTB_B 8.2 KΩ pull-up to 3.3 V. Connect to AGP connector. SBSTB 8.2 KΩ pull-up to 3.3 V. Connect to AGP connector. GFRAME# 8.2 KΩ pull-up to 3.3 V. Connect to AGP connector. GIRDY# 8.2 KΩ pull-up to 3.3 V. Connect to AGP connector. GTRDY# 8.2 KΩ pull-up to 3.3 V. Connect to AGP connector. GSTOP# 8.2 KΩ pull-up to 3.3 V. Connect to AGP connector. GDEVSEL# 8.2 KΩ pull-up to 3.3 V. Connect to AGP connector. GREQ# 8.2 KΩ pull-up to 3.3 V. Connect to AGP connector. GGNT# 8.2 KΩ pull-up to 3.3 V. Connect to AGP connector. GAD[31:0] Connect to AGP connector. GC/BE[3:0]# Connect to AGP connector. 100 KΩ pull-down to Vss. Pull-down not required if the AGP device uses GFRAME# GPAR only.

66 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

7.3.6 Clocks, Resets, and Miscellaneous Signals

• See Section 5.0 for clock routing guidelines.

Table 37. Clocks, Resets, and Miscellaneous Signals

82443BX Pin Pin Connection

Connect to CPU BCLK and CK100M through 22 Ω series resistor at CK100M HCLKIN device PCLKIN Connect to CK100M through 33 Ω series resistor. DCLKO Connect to CKBFM through 18 Ω series resistor placed next to 82443BX. DCLKWR 22 Ω series termination at CKBFM. ‘T’ at the 22 Ω resistor with 15 pF cap to Vss. PCIRST# Connect to AGP, PCI, and PIIX4E. 33 Ω series resistor next to PIIX4E. GCLKIN Connect to GCLKO through 18 Ω series resistor. GCLKO Connect to AGP device through 18 Ω series resistor. CRESET# NO CONNECT. Optional connect to bus ratio logic for qualification processors. TESTIN# 8.2 KΩ pull-up to 3.3 V. May be removed if validation permits.

7.3.7 Power Management Interface

Table 38. Power Management Interface

82443BX Pin Pin Connection

When not connected to PIIX4E, pull-down with a 100 Ω resistor at both the CLKRUN# 82443BX and PIIX4E. Otherwise, pull-up to 3.3 V with a 10 KΩ and connect to PIIX4E. 10 KΩ pull-up to 3.3 V. Connect to PIIX4E SUS_STAT1# pin for POS SUSTAT# implementation. Connect to processor PWRGOOD pin through voltage conversion logic. Connect to BXPWROK PIIX4E PWROK pin.

Design Guide 67 Intel® Pentium® III Processor – Low Power/440BX AGPset

7.3.8 Reference Pins

Table 39. Reference Pins

82443BX Pin Pin Connection

GTLREF = 2/3 VCCT. Use voltage divider with R1 = 1.0 KΩ 1%, and R2 = 2.0 KΩ 1%. GTLREF[B:A] Place two 0.1uF caps next to 82443BX

VTT[B:A] Tie to VCCT voltage plane. VCC Power pin at 3.3 V.

VSS Tie to GND.

For a 5 V tolerant PCI bus connect to 5 V through a 1 KΩ resistor. See Section 8.2.1 REF5V for voltage sequencing requirements. For non-5 V tolerant PCI connect directly to 3.3 V. AGPREF = (2/5)3.3 V. Use a voltage divider with R1 = 3.48 KΩ 1% and AGPREF R2 = 2.32 KΩ 1%. Place 0.1uF cap next to 82443BX. When disabling AGP, tie to ground.

7.3.9 82443BX Decoupling Guidelines

Decoupling caps should be placed at the corners of the 82443BX (BGA Package). A minimum of four 0.1 µF and four 0.01 µF are recommended. The system bus, AGP, PCI, and DRAM interface may break out from the BGA package on all four sides. Additional caps will also help reduce EMI and cross-talk. Refer to Figure 33 for decoupling topology. Figure 33. 82443BX Decoupling

0.1uF 0.1uF 0.01uF 0.01uF 82443BX Host Bridge/ Controller 492 BGA 0.1uF 0.1uF 0.01uF 0.01uF

68 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

7.3.10 82443BX Strapping Options

• Highlighted strapping options shown below are required for this platform. • Internal resistors are 50 KΩ pull-up or pull-down. • Use external resistors of 10 KΩ to configure modes. • Strapping option pull-ups should be to 3.3 V.

Table 40. 82443BX Strapping Options

Internal Status Pin Name Function Low High Resistor Register

MAB12# Host Frequency Select 66 MHz 100 MHz Pull-down NBXCFG[13] In-Order Queue Depth MAB11# 1 (no pipelining) 4 (max) Pull-up NBXCFG[2] Enable Quick Start MAB10 Quick Start Select Stop Clock Mode Pull-down PMCR[3] Mode MAB9# AGP Disable AGP Enabled AGP Disabled Pull-down PMCR[1] Tri-states certain MAB7# MM Configuration Normal Operation Pull-down DRAMC[5] Memory signals Host Bus Buffer Mode Low Power MAB6# Desktop GTL+ Pull-down None Select GTL+

Design Guide 69 Intel® Pentium® III Processor – Low Power/440BX AGPset

7.4 82371EB (PIIX4E) Design Checklist

7.4.1 PCI Interface Signals

• For systems in which the PCIRST# signal is lightly loaded (< 50pF), place a 47 pF capacitor to Vss on this signal. The capacitor should be placed as close as possible to the PIIX4E.

Table 41. PCI Interface Signals

PIIX4E Pin Pin Connection

AD[31:0] Connect to PCI slots and 82443BX. C/BE#[3:0] Connect to PCI slots and 82443BX. 10 KΩ pull-up to 3.3 V. Connect to 82443BX. When not used, tie a 100 Ω pull-down CLKRUN# at both the 82443BX and PIIX4E. 2.7 KΩ pull-up to 5 V or 10 KΩ pull-up to 3.3 V. Connect between 82443BX, DEVSEL# PCI slots, and PIIX4E. 2.7 KΩ pull-up to 5 V or 10 KΩ pull-up to 3.3 V. Connect between 82443BX, FRAME# PCI slots, and PIIX4E. IDSEL 100 Ω series resistor to AD18.

2.7 KΩ pull-up to 5 V or 10 KΩ pull-up to 3.3 V. Connect between 82443BX, IRDY# PCI slots, and PIIX4E. PAR Connect to PCI slots and 82443BX. PCIRST# 33 Ω series resistor next to PIIX4E. Connect to AGP, PCI, and 82443BX. PHOLD# Connect to 82443BX. 10 KΩ pull-up to 3.3V. PHLDA# Connect to 82443BX. 10 KΩ pull-up to 3.3V. 2.7 KΩ pull-up to 5 V or 10 KΩ pull-up to 3.3 V. Connect between 82443BX, SERR# PCI slots, and PIIX4E. 2.7 KΩ pull-up to 5 V or 10 KΩ pull-up to 3.3 V. Connect between 82443BX, STOP# PCI slots, and PIIX4E. 2.7 KΩ pull-up to 5 V or 10 KΩ pull-up to 3.3 V. Connect between 82443BX, TRDY# PCI slots, and PIIX4E.

70 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

7.4.2 ISA/EIO Bus Interface Signals

• Recommendations below are for ISA implementation. • When implementing Power On Suspend (POS) mode, ISA signals should be pulled up to 3.3 V. Otherwise use 5 V.

Note: This pull-up voltage is referred to VCCISA in this checklist.

Table 42. ISA/EIO Bus Interface Signals

PIIX4E Pin Pin Connection

AEN Connect to SIO and ISA slots. Ω BALE/GPO0 10K pull-up to VCCISA. Connect to ISA slots. Ω IOCHK# /GPI0 1K pull-up to VCCISA. Connect to ISA slots. Ω IOCHRDY 1K pull-up to VCCISA. Connect to ISA slots and Ultra I/O. Ω IOCS16# 1K pull-up to VCCISA. Connect to ISA slots. Ω IOR# 10K pull-up to VCCISA. Connect to ISA slots, Ultra I/O, LM79. Ω IOW# 10K pull-up to VCCISA. Connect to ISA slots, Ultra I/O, LM79. LA[23:17] 10K Ω pull-up to V . Connect to ISA slots. /GPO[7:1] CCISA Ω MEMCS16# 1K pull-up to VCCISA. Connect to ISA slots. Ω MEMR# 10K pull-up to VCCISA. Connect to ISA slots and Flash. Ω MEMW# 10K pull-up to VCCISA. Connect to ISA slots and Flash. Ω REFRESH# 1K pull-up to VCCISA. Connect to ISA slots. RSTDRV Connect to Ultra I/O, ISA slots, and IDE (IDE through a Schmitt trigger). Ω SA[19:0] 10K pull-up to VCCISA. Connect to ISA slots, Ultra I/O, Flash, LM79. Ω SBHE# 10K pull-up to VCCISA. Connect to ISA slots. Ω SD[15:0] 10K pull-up to VCCISA. Connect to ISA slots, Ultra I/O, LM79. Ω SMEMR# 10K pull-up to VCCISA. Connect to ISA slots. Ω SMEMW# 10K pull-up to VCCISA. Connect to ISA slots. Ω ZEROWS# 1K pull-up to VCCISA. Connect to ISA slots.

Design Guide 71 Intel® Pentium® III Processor – Low Power/440BX AGPset

7.4.3 X-Bus Interface Signals

Value of pull-up on A20GATE# and RCIN# could vary depending on SIO output type.

Table 43. X-Bus Interface Signals

PIIX4E Pin Pin Connection

A20GATE# 10 KΩ pull-up to 3.3 V. Connect to SIO. BIOSCS# Connect to Flash.

KBCCS# NO CONNECT. When the KBCCS# signal is not used, this signal may be /GPO26 programmed to be a general-purpose output. MCCS# NO CONNECT PCS[0:1]# 10 KΩ pull-up to 3.3 V. Connect to LM79. NO CONNECT if not used. RCIN# 10 KΩ pull-up to 3.3 V. Connect to SIO.

RTCALE NO CONNECT. When the internal Real Time Clock is used, this signal may be /GPO25 programmed as a general-purpose output.

RTCCS# NO CONNECT. When the internal Real Time Clock is used, this signal may be /GPO24 programmed as a general-purpose output.

XDIR# Connect to SIO. NO CONNCET if not used. When the X-Bus not used, this signal /GPO22 may be programmed to be a general-purpose output.

XOE# Connect to SIO. NO CONNECT if not used. When the X-Bus not used, this signal /GPO23 may be programmed to be a general-purpose output.

7.4.4 DMA Signals

Table 44. DMA Signals

PIIX4E Pin Pin Connection

DACK[0,1,2,3]# Connect to ISA slots. DACK#[3:0] also connect to SIO. DACK[5,6,7]# DREQ[0,1,2,3] Connect to ISA slots. 5.6 KΩ pull-down. DREQ[5,6,7]

REQ[A:C]# 10 K Ω pull-up to 3.3 V. When the PC/PCI DMA request is not needed, these pins /GPI[2:4] may be used as general-purpose inputs.

GNT[A:C]# NO CONNECT. When the PC/PCI DMA acknowledge is not needed, these pins /GPO[9:11] may be used as general-purpose outputs. TC Connect to SIO and ISA slots.

72 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

7.4.5 Interrupt Controller/APIC Signals

Table 45. Interrupt Controller/APIC Signals

PIIX4E Pin Pin Connection

APICACK# Connect to IOAPIC. When the external APIC is not used, this pin is a /GPO12 general-purpose output. APICCS# 2.7 KΩ pull-up to 3.3 V. Connect to IOAPIC. When the external APIC is not used, /GPO13 this pin is a general-purpose output. APICREQ# 10 KΩ pull-up to 3.3 V. Connect to IOAPIC. When the external APIC is not used, this /GPI5 pin is a general-purpose input. Connect to INTIN2 of IOAPIC. When the external APIC is not used, this pin is a IRQ0/GPO14 general-purpose output. Ω IRQ1 10 K pull-up to VCCISA. Connect to ISA slots and Ultra I/O. Connect to IOAPIC. Ω IRQ[3:7, 9:11] - 10 K pull-up to VCCISA. Connect to ISA slots and Ultra I/O. IRQ[3:7, 9:11] Connect to IOAPIC. Ω IRQ[14:15] IRQ[14:15] - 10 K pull-up to VCCISA. Connect to ISA slots, Ultra I/O and IDE. Connect to IOAPIC. IRQ8#/GPI6 10 KΩ pull-up to 3.3VSB. Connect to IOAPIC through tri-state buffer. IRQ9OUT Connect to IOAPIC. When the external APIC is not used, this pin is a general- /GPO29 purpose output. Ω IRQ12/M 10 K pull-up to VCCISA. Connect to ISA slots and Ultra I/O. Connect to IOAPIC. 2.7 KΩ pull-up to 5 V or 10 KΩ pull-up to 3.3 V. Connect between PCI slots and PIRQ[A:D]# PIIX4E. PIRQ[A:B]# also go to AGP. SERIRQ 10 KΩ pull-up to 3.3 V. When not using serial interrupts, this pin may be used as a /GPI7 genera purpose input.

7.4.6 CPU Interface Signals

Table 46. CPU Interface Signals

PIIX4E Pin Pin Connection

A20M# 1.5 KΩ pull-up to VCCT. CPURST NO CONNECT FERR# Connect to voltage conversion logic as described in processor checklist.

IGNNE# 1.5 KΩ pull-up to VCCT.

INIT 1 KΩ pull-up to VCCT.

INTR 1.5 KΩ pull-up to VCCT. Connect to IOAPIC.

NMI 1.5 KΩ pull-up to VCCT.

SLP# 1.5 KΩ pull-up to VCCT.

SMI# 270 Ω pull-up to VCCT. Connect to IOAPIC.

STPCLK# 680 Ω pull-up to VCCT.

Design Guide 73 Intel® Pentium® III Processor – Low Power/440BX AGPset

7.4.7 Clocking Signals

• USB Clock – A 48 MHz clock with a duty cycle of better than 40%/60% should be fed into the PIIX4E’s USB clock input, pin L3. • The RTC capacitor value should be chosen to provide the manufacturer’s specified load capacitance of the trace, socket (if used), and package which may vary from 0 pF to 8 pF. When choosing the value the following equation may be used:

Specified Crystal Load = (Cap1*Cap2)/Cap1+Cap2) + parasitic capacitance

Table 47. Clocking Signals

PIIX4E Pin Pin Connection

Connect to 48 MHz clock through a 33 Ω series resistor. When not using USB, this CLK48 may be connected to GND. PCICLK Connect to CK100M through a 33 Ω series resistor. OSC Connect to CK100M through a 33 Ω series resistor. Connect to 32.768 KHz crystal. Place capacitors on each side of crystal to Vss. For RTCX1, RTCX2 capacitor values see above. SUSCLK NO CONNECT SYSCLK Connect to LM79 and ISA slots. NO CONNECT if not using ISA.

74 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

7.4.8 IDE Signals

• Series termination resistors should be placed within one inch of the PIIX4E. • When not using IDE the following primary and secondary IDE signals, they may be left as NO CONNECTS: xDA[2:0], xDCS1#, xDCS3#, xDD[15:8,6:0], xDDACK#, xDIOR#, xDIOW#.

Table 48. IDE Signals

PIIX4E Pin Pin Connection

PDA[2:0] Connect to IDE connector through 33 Ω series resistors. PDCS1# Connect to IDE connector through 33 Ω series resistor. PDCS3# Connect to IDE connector through 33 Ω series resistor. Connect to IDE connector through 33 Ω series resistors. It is recommended that PDD[15:0] PDD[7] have a 10 KΩ pull-down resistor even if IDE is not used. PDDACK# Connect to IDE connector through 33 Ωseries resistor. Connect to IDE through 33 Ω series resistor. 5.6 KΩ pull-down on the PIIX4E side of PDDREQ the series resistor. When not used, a 5.6 KΩ pull-down is still required. PDIOR# Connect to IDE connector through 33 Ω series resistor. PDIOW# Connect to IDE connector through 33 Ω series resistor. Connect to IDE through 47 Ω series resistor. 1 KΩ pull-up to V on the PIIX4E PIORDY CCISA side of the series resistor. When not used, a 1 KΩ pull-up is still required SDA[2:0] Connect to IDE connector through 33 Ω series resistors. SDCS1# Connect to IDE connector through 33 Ω series resistor. SDCS3# Connect to IDE connector through 33 Ω series resistor. Connect to IDE connector through 33 Ω series resistors. It is recommended that SDD[15:0] SDD[7] have a 10 KΩ pull-down resistor even if IDE is not used. SDDACK# Connect to IDE connector through 33 Ω series resistor. Connect to IDE through 33 Ωseries resistor. 5.6 KΩ pull-down on the PIIX4E side of SDDREQ the series resistor. When not used, a 5.6 KΩ pull-down is still required. SDIOR# Connect to IDE connector through 33 Ω series resistor. SDIOW# Connect to IDE connector through 33 Ω series resistor. Connect to IDE through 47 Ω series resistor. 1 KΩ pull-up to V on the PIIX4E SIORDY CCISA side of the series resistor. When not used, a 1 KΩ pull-up is still required.

Design Guide 75 Intel® Pentium® III Processor – Low Power/440BX AGPset

7.4.9 USB Signals

• When not using USB, a 10 KΩ pull-up to 3.3 V is required on OC[1:0]# and 15 KΩ pull-downs are required on all USBP signals. • Refer to the PIIX4 Universal Serial Bus design guide and Checklist for USB layout guidelines, available from your Intel field sales representative. Table 49. USB Signals

PIIX4E Pin Pin Connection

OC[1:0]# Driven by USB over-current detection voltage divider. USBP0+ 47pF cap to Vss with 27 Ω series resistor to USB port. These should be /USBP0- placed as close as possible to the PIIX4E. USBP1+ 47pF cap to Vss with 27 Ω series resistor to USB port. These should be /USBP1- placed as close as possible to the PIIX4E.

76 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

7.4.10 Power Management Signals

• SUSA# is primarily used to control the primary power plane. This signal is asserted during POS, STR, and STD suspend states. • SUSB# is primarily used to control the secondary power plane. This signal is asserted during STR, and STD suspend states. • SUSC# is primarily used to control the tertiary power plane. This signal is asserted during STD suspend state.

Table 50. Power Management Signals (Sheet 1 of 2)

PIIX4E Pin Pin Connection

10 KΩ pull-up to 3.3 VSB if BATLOW# is not used. When the Battery Low BATLOW# /GPI19 function is not needed, this pin may be used as a general-purpose input. CPU_STP# /GPO17 NO CONNECT, or connect to CK100M with 10 KΩ pull-up to 3.3 VSB. EXTSMI# Connect to LM79. 10 KΩ pull-up to 3.3 VSB. LID/GPI10 10 KΩ pull-up to 3.3 VSB if LID is not used. PCIREQ[A:D]# 10 KΩ pull-up to 3.3 V. Connect to 82443BX and PCI slots. No connect, or connect to CK100M with 10 KΩ pull-up to 3.3 VSB. When this PCI_STP#/GPO18 function is not needed, this pin may be used as a general-purpose output. PWRBTN# From power button circuitry. When not used, add a 10 KΩ pull-up to 3.3 VSB. 10 KΩ pull-up to 3.3 VSB. Connect to AGP connector AGP_PME# (pin A48). RI#/GPI12 When this function is not needed, this signal may be individually used as a general-purpose input. From ATX connector buffer/delay circuitry. When not using power management RSMRST# (suspend modes), this may be connected to PIIX4E PWROK. 10 KΩ pull-up to 3.3 VSB. Connect to MAX1617. When this function is not SMBALERT#/GPI11 needed, this pin may be used as a general-purpose input. 2.7 KΩ pull-up to 3.3 V. Connect to all devices on SMBus. This value may need SMBCLK to be adjusted based on bus loading. 2.7 KΩ pull-up to 3.3 V. Connect to all devices on SMBus. This value may need SMBDATA to be adjusted based on bus loading. No connect, or connect to CK100M power down control with 10 K Ω pull-up to SUSA# 3.3 V. Controls secondary power plane during STR and STD suspend state. When the SUSB# /GPO15 power plane control is not needed, this pin may be used as a general-purpose output. Controls tertiary power plane during STD suspend state. When the power plane SUSC#/GPO16 control is not needed, this pin may be used as a general-purpose output. No Connect or connect to 82443BX for POS implementation. When this SUS_STAT1#/GPO20 function is not needed, this pin may be used as a general-purpose output. NO CONNECT. When this function is not needed, this pin may be used as a SUS_STAT2#/GPO21 general-purpose output. 10 KΩ pull-up to 3.3 V. Connect to LM75. When this function is not needed, this THRM#/GPI8 pin may be used as a general-purpose input. NO CONNECT. When this function is not needed, this pin may be used as a ZZ/GPO19 general-purpose output. GPI[21:0] 10 KΩ pull-up to 3.3 V if these pins are not used.

Design Guide 77 Intel® Pentium® III Processor – Low Power/440BX AGPset

Table 50. Power Management Signals (Sheet 2 of 2)

PIIX4E Pin Pin Connection

GPO[30:0] NO CONNECT if these pins are not used.

7.4.11 Other System and Test Signals

Table 51. Other System and Test Signals

PIIX4E Pin Pin Connection

CONFIG1 10 KΩ pull-up to 3.3 VSB. CONFIG2 10 KΩ pull-down to Vss Connect to 82443BX and power up logic. When not using power management PWROK (suspend modes), also connect to PIIX4E RSMRST#. SPKR Connect to speaker circuit. NO CONNECT if not used. TEST# 10 KΩ pull-up to 3.3VSB.

7.4.12 Power and Ground Pins

Table 52. Power and Ground Pins

PIIX4E Pin Pin Connection

Vcc Tie to 3.3 V.

Vcc(RTC) Tie to 3.3 V. Connect to battery circuitry. Also referred to as VBAT Tie to 3.3 V Standby plane (Also referred to as 3.3 VSB). The 3.3 VSB should power Vcc(SUS) off only when the system is mechanically off. When power management is not used, tie directly to 3.3 V.

Vcc(USB) Tie to 3.3 V.

For a 5 V tolerant PCI bus connect to 5 V. It must be powered up before or simultaneous to 3.3 V. It must power down after or simultaneous to 3.3 V. See Section V REF 8.1.1 for example circuit. For non-5 V tolerant PCI (3.3 V only) connect directly to 3.3 V. There are no sequencing requirements.

Vss Tie to GND.

Vss (USB) Tie to GND.

7.4.13 PIIX4E Decoupling Guidelines

Use the same guidelines as shown in Section 7.3.9, “82443BX Decoupling Guidelines” on page 68.

78 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

8.0 Power Sequencing

This section provides a summary of the power sequencing requirements and options of the 440BX AGPset. It provides a detailed description of the PIIX4E Suspend/Resume sequence, signaling protocols, and timings. The recommended usage model for power plane control in a 440BX platform using PIIX4E power management signals is described.

This section does not represent the only way to design a system, but it does provide recommendations for using the 440BX AGPset.

8.1 PIIX4E Power Sequencing

8.1.1 Power Sequencing Requirements

In systems requiring 5 V tolerance, the VREF signal must be tied to 5 V. This signal must power up before or simultaneous to VCC. It must power down after or simultaneous to VCC. In a non 5 V tolerant system (3.3 V only), this signal may be tied directly to VCC. There are then no sequencing requirements. Refer to Figure 34 for an example circuit schematic, which may be used to ensure the proper VREF sequencing.

The PIIX4E VCC and VCC(USB) supplies are separated internally in order to reduce noise on USB signals. They should not be powered up or down independently of one another. They should be connected to the same power plane on the motherboard. There are no other power sequencing requirements for the various VCC power supplies to the PIIX4E. Figure 34. VREF Supply Schematic

VCC Supply 5V Supply (3.3V)

1k

Schottky Diode 1 uF

To SystemVREF To System

8.1.2 Suspend/Resume and Power Plane Control

The PIIX4E supports three different Suspend modes. The common system usage model for these modes is described here and includes Power On Suspend (POS), Suspend to RAM (STR), and Suspend to Disk (STD). This mode definition allows for other system usage models that use the PIIX4E suspend/resume control signals in other ways. The common system mode names are used throughout this document.

Design Guide 79 Intel® Pentium® III Processor – Low Power/440BX AGPset

The PIIX4E power management architecture is designed to allow systems to support multiple suspend modes, and to switch between those modes as required. A suspended system may be resumed by a number of different events. The system returns to full operation, and may then continue processing or be placed into another suspend mode. The new mode may be at a lower power mode than the mode from which it resumed.

8.1.2.1 Power On Suspend (POS) System Model

All devices are powered up except for the clock synthesizer. The Host and PCI clocks are inactive, and the PIIX4E provides control signals and the 32 KHz Suspend Clock (SUSCLK) to allow for DRAM refresh and to turn off the clock synthesizer. The only power consumed in the system while it is in POS mode is due to DRAM refresh and leakage current of the powered devices.

When the system resumes from POS mode, the PIIX4E may resume without resetting the system, may reset the processor only, or may reset the entire system. When no reset is performed, the PIIX4E only needs to wait for the clock synthesizer and processor PLLs to lock before the system is resumed. This takes typically 20 ms.

8.1.2.2 Suspend to RAM (STR)

Power is removed from most of the system components during STR, except the DRAM. Power is supplied to the host bridge (for DRAM Suspend Refresh) and the PIIX4E’s RTC and Suspend Well logic. The PIIX4E provides control signals and a 32 KHz Suspend Clock (SUSCLK) to allow for DRAM refresh and to turn off the clock synthesizer and other power planes.

The PIIX4E resets the system on resume from STR.

8.1.2.3 Suspend to Disk (STD) and Soft Off (SOff)

Power is removed from most of the system components during STD. Power is maintained to the RTC and Suspend Well logic in the PIIX4E.

The PIIX4E resets the system on resume from STD.

The STD state is also called the Soft Off (SOff) state. The difference depends on whether the system state is restored by software to a pre-suspend condition or the system is rebooted.

80 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

8.1.2.4 Mechanical Off (MOff)

This is not a suspend state. This is a condition where all power except the RTC battery has been removed from the system. It is typically controlled by a mechanical switch that turns off AC power to a power supply. It could be used as a condition in which an embedded system’s main battery has been removed.

The PIIX4E controls the system entering the various suspend states through the suspend control signals listed in Table 53. Upon initiation of suspend, the PIIX4E asserts the SUS_STAT[1-2]#, SUSA#, SUSB#, and SUSC# signals in a well defined sequence to switch the system into the desired power state. The SUSA#, SUSB#, and SUSC# signals may be used to control various power planes in the system. The SUS_STAT1# signal is a status signal that indicates to the host bridge when to enter or exit a suspend state, or when to enter or exit a stop clock state (when the system is still running). This is typically used to place the DRAM controller into a Suspend Refresh mode of operation. The SUS_STAT2# signal is a status signal that may be used to indicate to other system devices when to enter or exit a suspend state (like the graphics and Cardbus controllers). See “System Suspend and Resume Control Signaling” on page 84 for sequencing details. Note that these signals are associated with a particular type of suspend mode and power plane for descriptive purposes here. The system designer is free to use these signals to control any type of function desired.

The system is placed into a suspend mode by programming the Power Management Control register. The Suspend Type is first programmed and then the Suspend Enable bit is set. This causes the PIIX4E to automatically sequence into the programmed suspend mode.

Table 53. Power State Decode

Power State RSMRST# SUS_STAT1# SUS_STAT2# SUSA# SUSB# SUSC#

On 1 x† 1111 POS 1 0 0 0 1 1 STR 1 0 0 0 0 1 STD/SOFF 1 0 0 0 0 0 Mechanical 00 0000 Off † SUS_STAT1# is also used when the system is running. It indicates to the Host-to-PCI bridge when to switch between the normal and suspend refresh mode for DRAM Stop Clock support. In the Stop Clock condition, HCLK is stopped and the Host-to-PCI bridge must run DRAM refresh from the internal oscillator.

Design Guide 81 Intel® Pentium® III Processor – Low Power/440BX AGPset

8.1.3 System Resume

The PIIX4E may be resumed from either a Suspend or Soft Off state. Depending on the suspend state that the system is in, different features may be enabled to resume the system. There are two classes of resume events, those whose logic resides in the PIIX4E main power well and those whose logic resides in the PIIX4E suspend well. Those in the suspend well may resume the system from any Suspend or Soft Off state. Those in the main power well may only resume the system from a Power On Suspend state. Table 54 lists the suspend states for which a particular resume event may be enabled.

Upon detection of an enabled resume event, the PIIX4E sets appropriate status signals and automatically transitions its suspend control signals to bring the system into a ‘full on’ condition. The sequencing is shown in “System Suspend and Resume Control Signaling” on page 84.

Table 54. Resume Events Supported In Different Power States

Suspend States Resume Event POS STR STD/SOff MOff

RTC Alarm (IRQ8) † xx x SMBus Resume Event (Slave Port Match) x x x Serial A Ring (RI) x x x Power Button (PWRBTN#) x x x EXTSMI (EXTSMI#) x x x LID (LID) x x x GPI 1 x x x GSTBY Timer Expiration x x x Interrupt (IRQ 1,3-15) x USB x † RTC Alarm only supports internal RTC. For external RTC implementations, the IRQ8 must be tied to one of the other resume input signals (GPI[1], LID, EXTSMI#,RI#) for the resume functionality.

82 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

8.1.3.1 System Resume Events

Table 55 indicates the various resume events and their corresponding programming models.

Table 55. Resume Event Programming Model

System Resume Event Programming Model

PWRBTN# Asserted [PWRBTN_EN] LID Asserted [LID_EN] - Polarity Select [LID_POL] GPI[1] Asserted [GPI_EN] EXTSMI# Asserted [EXTSMI_EN] [ALERT_EN] [SLV_EN] SMBus Events: [SHDW1_EN] [SHDW2_EN] Global Standby Timer Expiration: [GSTBY_EN] Ring Indicate Assertion (RI#) [RI_EN] RTC Alarm (IRQ8)† [RTC_EN] USB Resume Signaling: (POS Only) [USB_EN] IRQ[1,3-7,9-15]: (POS Only) [IRQ_RSM_EN] † RTC Alarm only supports internal RTC. For external RTC implementations, the IRQ8 must be tied to one of the other resume input signals (GPI[1], LID, EXTSMI#,RI#) for the resume functionality.

8.1.3.2 Global Standby Timer Resume

The Global Standby Timer is used to monitor system activity during normal operation and may be reloaded by system activity events. Upon expiration, it generates an SMI#. When the system is placed in a Suspend Mode, the Global Standby Timer may be used to generate a resume event. The Global Standby Timer may enable two different timer resolutions for wake-up times from approximately 30 seconds to 8.5 hours. This may allow the system to transition into a lower power suspend state.

See the System Management Section of the Intel® 82371AB PCI-to-ISA/IDE Xcelerator (PIIX4) Datasheet (order number 290562) for additional information about the Global Standby Timer.

Design Guide 83 Intel® Pentium® III Processor – Low Power/440BX AGPset

8.1.4 System Suspend and Resume Control Signaling

The PIIX4E automatically controls the signals required to transition the system between the various power states. It provides control for Host and PCI clocks, main memory and video memory refresh, system power plane control, and system reset. Table 56 and Table 57 indicate the common usage model for power plane control using the SUS[C:A]# signals. The PIIX4E Resume well should always be powered by a trickle supply (main battery or backup battery in an embedded system).

Table 56. Power Plane Control

SUSA# (POS) SUSB# (STR) SUSC# (STD)

Processor (Low Power GTL+ supplies) 82443BX Host Bridge/Controller Clock synthesizer PIIX4E Core DRAM Video display1 Other system devices2 Graphics Controller NOTES: 1. The video display (flat panel or CRT) may optionally be powered off in POS. This could be accomplished by using the PIIX4E’s SUSA# or SUS_STAT2# signals to assert the video controller’s STANDBY signal. 2. Devices may include mass storage, audio, or other devices that will not generate system resume events.

Table 57. Power Plane Control Using SUS[C:A]# Signals

Suspend Mode (Suspend Mode Signals Asserted by the PIIX4E) Power Plane POS STR STD Full On (SUSA#, (SUS[B:A]# (SUS[C:A]# (None) SUS_STAT[2:1]#) SUS_STAT[2:1]#) SUS_STAT[2:1]#)

Clock Synthesizer On Off Off Off Video Display On On/Off1 Off Off CPU On On Off Off PIIX4E Core On On Off Off Other Devices2 On On Off Off 82443BX On On On Off DRAM On On On Off Graphics Controller On On On Off PIIX4E Resume On On On On PIIX4E RTC On On On On NOTES: 1. The video display (flat panel or CRT) may optionally be powered off in POS. This could be accomplished by using the PIIX4E’s SUSA# or SUS_STAT2# signals to assert the video controller’s STANDBY signal. 2. Devices may include mass storage, audio, or other devices that will not generate system resume events.

8.1.4.1 Power Well and Reset Signal Timings

Figure 35 shows the system timings for changing the power states of a system using the POS/STR/ STD models.

84 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

8.1.4.2 PIIX4E Power Well Timings

Figure 35 describes the relative transitions for PIIX4E power supplies. Table 58 indicates the PIIX4E power well timing tolerances. Figure 35. PIIX4E Power Well Timings

RTC Well Power

t1 Suspend Well Power

t2 Core Well Power

Table 58. PIIX4E Power Well Timing Tolerances

Sym Parameter Min Max Unit Notes

t1 RTC Well Power to Suspend Well Power 0 ns t2 Suspend Well Power to Core Well Power 0 ns

8.1.4.3 RSMRST# and PWROK Timing

Figure 36 describes the required timings for PIIX4E power level active status signals. Table 59 indicates the RSMRST# and PWROK timing tolerances. Figure 36. RSMRST# and PWROK Timings

Suspend Well Power

t3 RSMRST#

Core Well Power

t5

t4 PWROK

Table 59. RSMRST# and PWROK Timing Tolerance

Sym Parameter Min Max Unit Notes

t3 Suspend Well Power to RSMRST# Inactive 1 ms t4 Core Well Power to PWROK Active 1 ms t5 RSMRST# Inactive to PWROK Active 0 ns

Design Guide 85 Intel® Pentium® III Processor – Low Power/440BX AGPset

8.1.4.4 Suspend Well Power and RSMRST# Activated Signals

Figure 37 shows the timing relationships for the PIIX4E power management signals that are powered from the Suspend Well Power signal. These timings hold independent of the condition of Core Well Power or the PWROK signal. Table 60 indicates the Suspend Well Power and RSMRST# timing tolerances. Figure 37. Suspend Well Power and RSMRST# Activated Signals

Suspend Well Power

RSMRST#

t6 SUS_STAT[1-2]#

t7 t9 SUS[A-C]#

t8 SUSCLK

Table 60. Suspend Well Power and RSMRST# Timing Tolerances

Sym Parameter Min Max Unit Notes

Resume Well Power and RSMRST# Active to t6 1RTC † SUS_STAT[1:2]# Active Resume Well Power and RSMRST# Active to SUS t7 1RTC † [A:C]# Active Resume Well Power and RSMRST# Active to t8 1RTC † SUSCLK Low t9 RSMRST# Inactive to SUS[A:C]# Inactive 1 2 RTC † † These signals are controlled off an internal RTC clock. One RTC unit is approximately 32 µs.

86 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

8.1.4.5 PCI Clock Control Timings

This section describes the timing requirements for the control of the system PCICLK. The system PCICLK timing shown in Figure 38 must be followed exactly for proper operation of the PC/PCI DMA or Serial IRQ logic. When the PC/PCI DMA and Serial IRQs are not used in the system, the system PCICLK stop timings must meet the system developer’s requirements. Figure 38. PCI Clock Stop Timing

PCI_STP#

PIIX4 PCICLK

SYSTEM PCICLK

Figure 39 describes the timing requirements for the control of the system PCICLK. The system PCICLK timings shown in Figure 39 must be followed exactly for proper operation of PC/PCI DMA or Serial IRQ logic. When PC/PCI DMA and Serial IRQs are not used in the system, the system PCICLK stop timings must meet the system developer’s requirements. Figure 39. PCI Clock Start Timing

PCI_STP#

PIIX4 PCICLK

SYSTEM PCICLK

Design Guide 87 Intel® Pentium® III Processor – Low Power/440BX AGPset

8.1.4.6 Core Well Power and PWROK Activated Signals (RSMRST# Inactive Before Core Well Power Applied)

Figure 40 shows the timing relations for Power Management signals powered from the PIIX4E Main Core well. The Suspend Well Power active status signals (RSMRST#) transitions before the application of core well power to the PIIX4E. This figure corresponds to the usage model for PIIX4E power management. Table 61 indicates the Core Well Power and PWROK timing tolerances. Figure 40. Core Well Power and PWROK Activated Signals (RSMRST# Inactive before Core Well Power Applied)

RTC Well Power Suspend Well Power RSMRST# SUS[C:A]# Core Well Power

PWROK t20 t26 CPU_STP# / PCI_STP# Float t25 t27 PCICLK / CPU Running Stopped t21 PCIRST# t22 CPURST Active t23 SLP# t24 STPCLK#

Table 61. Core Well Power and PWROK Timing Tolerances

Sym Parameter Min Max Unit Notes Core Well Power and PWROK Inactive to CPU_STP# and t20 1RTC1 PCI_STP# Float t21 Core Well Power and PWROK Inactive to PCIRST# Active 1 RTC 1 t22 Core Well Power and PWROK Inactive to CPURST Active 1 RTC 1 t23 Core Well Power and PWROK Inactive to SLP# Active 1 RTC 1 t24 Core Well Power and PWROK Inactive to STPCLK# Active 1 RTC 1 t25 CPU_STP# and PCI_STP# Float to Clocks Running 2 t26 PWROK Active to CPU_STP# and PCI_STP# Active 1 RTC 1 t27 CPU_STP# and PCI_STP# Active to Clocks Stopped 2 NOTES: 1. These signals are controlled off an internal RTC clock. One RTC unit is approximately 32 µs. 2. There are no specific requirements for these timings related to the PIIX4E. The system manufacturer should make sure that the clocks on power up meet any other system specifications. As a minimum, the clocks must be available and stable after time t29 shown in Figure 42.

88 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

8.1.4.7 Core Well Power and PWROK Activated Signals (Core Well Power Applied Before RSMRST# Inactive)

Figure 41 shows the timing relations for Power Management signals powered from the PIIX4E Core well. Here the power active status signals (RSMRST# and PWROK) transition after the application of all power to the PIIX4E. This is an example of an implementation in which the Core Well power plane is not controlled by the SUSB# signal. It may be applied to situations where two or more of the PIIX4E power planes are connected together. It also shows timings when RSMRST# and PWROK are connected together. Figure 41. Core Well Power and PWROK Activated Signals (Core Well Power Applied before RSMRST# Inactive)

RTC Well Power Suspend Well Power Core Well Power RSMRST# PWROK t10 t16 CPU_STP# / PCI_STP# Float t15 t17 PCICLK / CPU CLK Stopped t11 PCI_RST# t12 CPURST Active t19 t13 t18 SLP# t19a t14 t18a STPCLK#

Design Guide 89 Intel® Pentium® III Processor – Low Power/440BX AGPset

Table 62. Core Well Power and PWROK Timing

Sym Parameter Min Max Unit Notes

Core Well Power and PWROK Inactive to t10 1RTC 1 CPU_STP# and PCI_STP# Float Core Well Power and PWROK Inactive to PCIRST# t11 1RTC 1 Active Core Well Power and PWROK Inactive to CPURST t12 1RTC 1 Active Core Well Power and PWROK Inactive to SLP# t13 1RTC 1 Inactive Core Well Power and PWROK Inactive to STPCLK# t14 1RTC 1 Inactive t15 CPU_STP# and PCI_STP# Float to Clocks Running 2 PWROK Active to CPU_STP# and PCI_STP# t16 1RTC 1 Active CPU_STP# and PCI_STP# Active to Clocks t17 2 Stopped t18 PWROK Active to SLP# Active 0 ns 3 t18a PWROK Active to STPCLK# Active 0 ns 1 t19 PWROK Active to SLP# Inactive 1 2 RTC 1, 3 t19a PWROK Active to STPCLK# Inactive 1 2 RTC 1, 3 NOTES: 1. These signals are controlled off an internal RTC clock. One RTC unit is approximately 32 µs. 2. There are no specific requirements for these timings related to the PIIX4E. The system manufacturer should make sure that the clocks on power up meet any other system specifications. As a minimum, the clocks must be available and stable after time t29 shown in Figure 42. 3. These timings depend on the relative timings between RSMRST# and PWROK. When RSMRST# goes inactive two RTC periods before PWROK active, SLP# and STPCLK# will remain inactive. When RSMRST# goes inactive less than two RTC periods before PWROK active, an active pulse will be seen on SLP# and STPCLK#.

90 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

8.1.5 Power Management State Transition Timings

8.1.5.1 Mechanical Off to On

Figure 42 shows the transition from a Mechanical Off condition to the On condition. Table 63 describes the mechanical Off to On timing tolerances. Figure 42. Mechanical Off to On

RSMRST# PWROK SUS[A-C]#

t30 SUS_STAT[1-2]#

t31 SUSCLK Running t28 CPU_STP# / PCI_STP# Float

t29 PCICLK / CPU CLK Stopped Running t32 PCI_RST#

t33 CPURST Active Inactive SLP# STPCLK#

Table 63. Mechanical Off to On Timing Tolerances

Sym Parameter Min Max Unit Notes

SUS[A:C]# Inactive to CPU_STP# and PCI_STP# t28 16 ms 1 Inactive t29 CPU_STP# and PCI_STP# Inactive to Clocks Running 2 PCICLK 2 CPU_STP# and PCI_STP# Inactive to t30 1ms SUS_STAT[1:2]# Inactive t31 SUS_STAT[1:2]# Inactive to SUSCLK Running 1 RTC 3 t32 SUS_STAT[1:2]# Inactive to PCI_RST# Inactive 1 RTC 3 t33 PCI_RST# Inactive to CPURST Inactive 1 RTC 3 NOTES: 1. This transition requires a minimum of 16 ms wait for the clock synthesizer PLL to lock and PWROK to be active. When PWROK goes active after 16 ms from SUS[A:C]# inactive, the transition occurs a minimum of one RTC period from PWROK active. 2. See Figure 38 and Figure 39 for exact PCICLK requirements for use with PC/PCI DMA and Serial IRQs. 3. These signals are controlled from an internal RTC clock. One RTC unit is approximately 32 µs.

Design Guide 91 Intel® Pentium® III Processor – Low Power/440BX AGPset

8.1.5.2 On to POS

Figure 43 describes the signal transitions from the On state to the Power On Suspend state. Table 64 indicates the On to POS timing tolerances. Figure 43. On to POS

PWROK

t36 SUS_STAT[1-2]#

38 SUS[A]#

SUS[B-C]#

SUSCLK Running

t37 CPU_STP# / PCI_STP#

t39 PCICLK / CPU CLK Clocks Running Clocks Stopped

PCI_RST#

CPURST Inactive

t35 SLP#

t34 STPCLK#

Table 64. On to POS Timing Tolerances

Sym Parameter Min Max Unit Notes

CPU_STP# and PCI_STP# Inactive to t34 1RTC1, 2 STPCLK# Active t35 STPCLK# Active to SLP# Active 1 RTC 1, 3 t36 SLP# Active to SUS_STAT[1:2]# Active 1 RTC 1 SUS_STAT[1:2]# Active to CPU_STP# and t37 1RTC1 PCI_STP# Active CPU_STP# and PCI_STP# Active to SUS[A]# t38 1RTC1 Active CPU_STP# and PCI_STP# Active to Clocks t39 2 PCICLK 4, 5 Stopped (if applicable) NOTES: 1. These signals are controlled from an internal RTC clock. One RTC unit is approximately 32 µs. 2. CPU_STP# and PCI_STP# will only be active when the system is under clock control. 3. This transition waits for the Stop Grant cycle to execute. 4. It is up to the system vendor to determine whether CPU_STP# and PCI_STP# signals are used to control system clocks. 5. See Figure 38 and Figure 39 for exact PCICLK requirements for use with PC/PCI DMA and Serial IRQs.

92 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

8.1.5.3 POS to On (with Processor and PCI Reset)

Figure 44 describes the system transition from Power On Suspend to On with a full system reset. Table 65 indicates the POS to On timing tolerances. Figure 44. POS to On (with Processor and PCI Reset)

Resume Event PWROK

t47 SUS_STAT[1-2]#

t40 SUS[A]# SUS[B-C]#

SUSCLK Running

t45 t49 CPU_STP# / PCI_STP#

t46 PCICLK / CPU CLK Clocks Stopped Clocks Running

t41 t48 PCI_RST#

t42 t50 CPURST Inactive Active Inactive t43 SLP#

t44 STPCLK#

Table 65. POS to On Timing Tolerances

Sym Parameter Min Max Unit Notes t40 Resume Event to SUS[A]# Inactive 1 RTC 1 t41 Resume Event to PCI_RST# Active 1 RTC 1 t42 Resume Event to CPURST Active 1 RTC 1 t43 Resume Event to SLP# Inactive 1 RTC 1 t44 Resume Event to STPCLK# Inactive 1 RTC 1 SUS[A]# Inactive to PCI_STP# and CPU_STP# t45 16 ms 2 Inactive PCI_STP# and CPU_STP# Inactive to Clocks t46 2 PCICLK 3 Running PCI_STP# and CPU_STP# Inactive to t47 1ms SUS_STAT[1:2]# Inactive t48 SUS_STAT[1:2]# Inactive to PCI_RST# Inactive 1 RTC 1 PCI_RST# Inactive to PCI_STP# and CPU_STP# t49 1RTC1 allowed to change t50 PCI_RST# Inactive to CPURST Inactive 1 RTC 1 NOTES: 1. These signals are controlled from an internal RTC clock. One RTC unit is approximately 32 µs. 2. This transition requires a minimum of 16 ms wait for the clock synthesizer PLL to lock and PWROK to be active. When PWROK goes active after 16 ms from SUS[A:C]# inactive, the transition will occur a minimum of one RTC period from PWROK active. PWROK remains active throughout POS system usage. 3. See Figure 38 and Figure 39 for exact PCICLK requirements for use with PC/PCI DMA and Serial IRQs.

Design Guide 93 Intel® Pentium® III Processor – Low Power/440BX AGPset

8.1.5.4 POS to On (with Processor Reset)

Figure 45 describes the system transition from Power On Suspend (POS) to On with only a processor reset. Table 66 indicates the POS to On (with processor reset) timing tolerances. Figure 45. POS to On (with Processor Reset)

Resume Event PWROK

t57 SUS_STAT[1-2]#

t51 SUS[A]# SUS[B-C]#

SUSCLK Running

t55 t58 CPU_STP# / PCI_STP#

t56 PCICLK / CPU CLK Clocks Stopped Clocks Running PCI_RST#

t52 t59 CPURST Inactive Active Inactive

t53 SLP#

t54 STPCLK#

Table 66. POS to On (with Processor Reset) Timing Tolerances

Sym Parameter Min Max Unit Notes

t51 Resume Event to SUSA# Inactive 1 RTC 1 t52 Resume Event to CPURST Active 1 RTC 1 t53 Resume Event to SLP# Inactive 1 RTC 1 t54 Resume Event to STPCLK# Inactive 1 RTC 1 t55 SUS[A]# Inactive to PCI_STP# and CPU_STP# Inactive 16 ms 2 t56 PCI_STP# and CPU_STP# Inactive to Clocks Running 2 PCICLK 3 PCI_STP# and CPU_STP# Inactive to SUS_STAT[1:2]# t57 1ms Inactive SUS_STAT[1:2]# Inactive to PCI_STP# and CPU_STP# t58 2RTC1 allowed to change t59 SUS_STAT[1:2]# Inactive to CPURST Inactive 2 RTC 1 NOTES: 1. These signals are controlled from an internal RTC clock. One RTC unit is approximately 32 µs. 2. This transition requires both a minimum of 16 ms wait for the clock synthesizer PLL to lock and PWROK to be active. When PWROK goes active after 16 ms from SUS[A:C]# inactive, the transition will occur a minimum of one RTC period from PWROK active. PWROK remains active throughout POS system usage. 3. See Figure 38 and Figure 39 for exact PCICLK requirements for use with PC/PCI DMA and Serial IRQs.

94 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

8.1.5.5 POS to On (No Reset)

Figure 46 describes the system transition from Power On Suspend to On with no resets performed. Table 67 indicates the POS to On (no reset) timing tolerances. Figure 46. POS to On (No Reset)

Resume Event PWROK

t63 SUS_STAT[1-2]#

t60 SUS[A]# SUS[B-C]#

SUSCLK Running

t61 t64 CPU_STP# / PCI_STP#

t62 PCICLK / CPU CLK Clocks Stopped Clocks Running PCI_RST#

CPURST Inactive

t65 SLP#

t66 STPCLK#

Table 67. POS to On (No Reset) Timing

Sym Parameter Min Max Unit Notes

t60 Resume Event to SUS[A]# Inactive 1 RTC 1 SUS[A]# Inactive to PCI_STP# and CPU_STP# t61 16 ms 2 Inactive t62 PCI_STP# and CPU_STP# Inactive to Clocks Running 2 PCICLK 3 PCI_STP# and CPU_STP# Inactive to t63 1ms SUS_STAT[1:2]# Inactive SUS_STAT[1:2]# Inactive to PCI_STP# and t64 2RTC1 CPU_STP# allowed to change t65 SUS_STAT[1:2]# Inactive to SLP# Inactive 1 RTC 1 t66 SLP# Inactive to STPCLK# Inactive 1 RTC 1 NOTES: 1. These signals are controlled from the internal RTC clock. One RTC is approximately 32 µs. 2. This transition requires both a minimum of 16 ms wait for the clock synthesizer PLL to lock and PWROK to be active. When PWROK goes active after 16 ms from SUS[A:C]# inactive, the transition will occur a minimum of one RTC period from PWROK active. PWROK remains active throughout POS system usage. 3. See Figure 38 and Figure 39 for exact PCICLK requirements for use with PC/PCI DMA and Serial IRQs.

Design Guide 95 Intel® Pentium® III Processor – Low Power/440BX AGPset

8.1.5.6 On to STR

Figure 47 describes the signal transitions from On state to Suspend to RAM state. Table 68 indicates the On to STR timing tolerances. Figure 47. On to STR

t73 PWROK

t80 Core Well Power

t69 SUS STAT[1-2]# SUS[A-B]# t72 SUS[C]#

SUSCLK Running

t70 t74 t81 CPU STP# /PCI_STP# Float Invalid

t71 t79 PCICLK / CPU CLK Running Stopped Invalid

t75 t82 PCI_RST# Invalid t76 t83 CPURST Inactive Active Invalid

t68 t77 t84 SLP# Invalid

t67 t78 t85 STPCLK# Invalid

96 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

Table 68. On to STR Timing Tolerances

Sym Parameter Min Max Unit Notes

t67 CPU_STP# and PCI_STP# Inactive to STPCLK# Active 1 RTC 1, 2 t68 STPCLK# Active to SLP# Active 1 RTC 1, 3 t69 SLP# Active to SUS_STAT[1:2]# Active 1 RTC 1 SUS_STAT[1:2]# Active to CPU_STP# and PCI_STP# t70 1RTC1 Active t71 CPU_STP# and PCI_STP# Active to CLOCKS Stopped 2 PCICLK 4, 5 CPU_STP# and PCI_STP# Inactive to SUS[A:B]# t72 1RTC1 Active t73 SUS[A:B]# Active to PWROK Inactive 0 ns 6 t74 PWROK Inactive to CPU_STP# and PCI_STP# Float 1 RTC 1 t75 PWROK Inactive to PCI_RST# Active 1 RTC 1 t76 PWROK Inactive to CPURST Active 1 RTC 1 t77 PWROK Inactive to SLP# Inactive 1 RTC 1 t78 PWROK Inactive to STPCLK# Inactive 1 RTC 1 t79 CPU_STP# and PCI_STP# Float to Clocks Invalid 0 ns 7 t80 PWROK Inactive to Core Well Power Removed 0 ns Core Well Power Removed to PCI_STP# and t81 0ns CPU_STP# Invalid t82 Core Well Power Removed to PCIRST# Invalid 0 ns t83 Core Well Power Removed to CPURST Invalid 0 ns t84 Core Well Power Removed to SLP# Invalid 0 ns t85 Core Well Power Removed to STPCLK# Invalid 0 ns NOTES: 1. These signals are controlled from the internal RTC clock. One RTC is approximately 32 µs. 2. CPU_STP# and PCI_STP# will only be active if the system is under clock control. 3. This transition will also wait for the Stop Grant cycle to execute. 4. It is up to the system vendor to determine if CPU_STP# and PCI_STP# signals are used to control system clocks. 5. See Figure 38 and Figure 39 for exact PCICLK requirements for use with PC/PCI DMA and Serial IRQs. 6. It is up to the system vendor to determine if SUS[A:B]# signals are used to control system power planes. When power remains applied to system board and PWROK stays active during STR, the PIIX4E signals will remain in the states shown after t73. 7. Clocks may or may not be running depending on the condition of the Power Supply voltages.

Design Guide 97 Intel® Pentium® III Processor – Low Power/440BX AGPset

8.1.5.7 STR to On

Figure 48 describes the system transition from Suspend To RAM to On with a full system reset. Table 56 indicates the STR to On timing tolerances. Figure 48. STR to On

Resume Event t94 PWROK t87 Core Well Power t100 SUS_STAT[1-2]#

SUS[A-B]# t86 SUS[C]# SUSCLK Running t97 t88 t95 t98 t101 CPU_STP# /PCI_STP# Invalid Float

t93 t96 t99 PCICLK / CPU CLK Invalid Running Stopped Running t89 t101a PCI_RST# Invalid t90 t102 CPURST Invalid Active Inactive t91 SLP# Invalid t92 STPCLK# Invalid

98 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

Table 69. STR to On Timing Tolerances

Sym Parameter Min Max Unit Notes

t86 Resume Event to SUS[A:B]# Inactive 1 RTC 1 t87 SUS[A:B]# Inactive to Core Well Power Applied 0 ns Core Well Power Applied to PCI_STP# and t88 0ns CPU_STP# Float t89 Core Well Power Applied to PCI_RST# Active 0 ns t90 Core Well Power Applied to CPURST Active 0 ns t91 Core Well Power Applied to SLP# Inactive 0 ns t92 Core Well Power Applied to STPCLK# Inactive 0 ns t93 PCI_STP# and CPU_STP# Float to Clocks Running 2 t94 Core Well Power Applied to PWROK Active 1 ms t95 PWROK Active to CPU_STP# and PCI_STP# Active 0 ns t96 PCI_STP# and CPU_STP# Active to Clocks Stopped 2 PCICLK 3 PWROK Active to CPU_STP# and PCI_STP# t97 1RTC1 Inactive SUS[A-B]# Inactive to CPU_STP# and PCI_STP# t98 16 ms Inactive CPU_STP# and PCI_STP# Inactive to Clocks t99 2 PCICLK 3 Running CPU_STP# and PCI_STP# Inactive to SUS_STAT[1- t100 1ms 2]# Inactive SUS_STAT[1-2]# Inactive to CPU_STP# and t101 2RTC1 PCI_STP# allowed to change t101a SUS_STAT[1-2]# Inactive to PCI_RST# Inactive 1 RTC 1 t102 PCI_RST# Inactive to CPURST Inactive 1 RTC 1 NOTES: 1. These signals are controlled from the internal RTC clock. One RTC is approximately 32 µs. 2. There are no specific requirements for these timings related to the PIIX4E. The system manufacturer should make sure that the clocks meet any other system specifications upon power up. At a minimum, the clocks must be available and stable after time t99. 3. See Figure 38 and Figure 39 for exact PCICLK requirements for use with the PC/PCI DMA and Serial IRQs.

Design Guide 99 Intel® Pentium® III Processor – Low Power/440BX AGPset

8.1.5.8 On to STD/SOff

Figure 49 describes the signal transitions from the On state to the Suspend to Disk/Soft Off state. Table 70 indicates the On to STD/SOff timing tolerances. Figure 49. On to STD/SOff

t110 PWROK

t117 Core Well Power

t105 SUS_STAT[1-2]#

t108 SUS[A-C]#

t109 SUSCLK Running

t106 t111 t118 CPU_STP# / PCI_STP# Float Invalid

t107 t116 PCICLK / CPU CLK Running Stopped Invalid

t112 t119 PCI_RST# Invalid

t113 t120 CPURST Inactive Active Invalid

t104 t114 t121 SLP# Invalid

t103 t115 t122 STPCLK# Invalid

100 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

Table 70. On to STD/SOff Timing Tolerances

Sym Parameter Min Max Unit Notes

CPU_STP# and PCI_STP# Inactive to STPCLK# t103 1RTC1, 2 Active t104 STPCLK# Active to SLP# Active 1 RTC 1, 3 t105 SLP# Active to SUS_STAT[1:2]# Active 1 RTC 1 SUS_STAT[1:2]# Active to CPU_STP# and t106 1RTC1 PCI_STP# Active CPU_STP# and PCI_STP# Inactive to CLOCKS t107 2 PCICLK 1, 4, 5 Stopped CPU_STP# and PCI_STP# Inactive to SUS[A:C]# t108 1RTC1 Active t109 SUS[A:C]# Active to SUSCLK Low 1 RTC 1 t110 SUS[A:C]# Active to PWROK Inactive 0 ns 6 PWROK Inactive to CPU_STP# and PCI_STP# t111 1RTC1 Float t112 PWROK Inactive to PCI_RST# Active 1 RTC 1 t113 PWROK Inactive to CPURST Active 1 RTC 1 t114 PWROK Inactive to SLP# Inactive 1 RTC 1 t115 PWROK Inactive to STPCLK# Inactive 1 RTC 1 t116 CPU_STP# and PCI_STP# Float to Clocks Invalid 0 ns 1 t117 PWROK Inactive to Core Well Power Removed 0 ns Core Well Power Removed to PCI_STP# and t118 0ns CPU_STP# Invalid t119 Core Well Power Removed to PCIRST# Invalid 0 ns t120 Core Well Power Removed to CPURST Invalid 0 ns t121 Core Well Power Removed to SLP# Invalid 0 ns t122 Core Well Power Removed to STPCLK# Invalid 0 ns NOTES: 1. These signals are controlled from the internal RTC clock. One RTC is approximately 32 µs. 2. CPU_STP# and PCI_STP# will only be active if the system is under clock control. 3. This transition will also wait for the Stop Grant cycle to execute. 4. It is up to the system vendor to determine if CPU_STP# and PCI_STP# signals are used to control system clocks. 5. See Figure 38 and Figure 39 for exact PCICLK requirements for use with the PC/PCI DMA and Serial IRQs. 6. It is up to the system vendor to determine if SUS[A:C]# signals are used to control system power planes. When the power remains applied to the system board and the PWROK stays active during STD, the PIIX4E signals will remain in the states shown after t110.

Design Guide 101 Intel® Pentium® III Processor – Low Power/440BX AGPset

8.1.5.9 STD/SOff to On

Figure 50 describes the system transition from Suspend To Disk/Soft Off to On with a full system reset. Table 71 indicates the STD/SOff to On timing tolerances. Figure 50. STD/SOff to On

Resume Event t131 PWROK t124 Core Well Power t137 SUS_STAT[1-2]# t123 SUS[A-C]# t138 SUSCLK Running t134 t135 t125 t132 t140 CPU_STP# / PCI_STP# Invalid Float

t130 t133 t136 PCICLK / CPU CLK InvalidRunning Stopped Running t126 t139 PCI_RST# Invalid t127 t141 CPURST Invalid Active Inactive t128 SLP# Invalid t129 STPCLK# Invalid

102 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

Table 71. STD/SOff to On Timing Tolerances

Sym Parameter Min Max Unit Notes

t123 Resume Event to SUS[A:C]# Inactive 1 RTC 1 t124 SUS[A-C]# Inactive to Core Well Power Applied 0 ns Core Well Power Applied to PCI_STP# and t125 0ns CPU_STP# Float t126 Core Well Power Applied to PCI_RST# Active 0 ns t127 Core Well Power Applied to CPURST Active 0 ns t128 Core Well Power Applied to SLP# Inactive 0 ns t129 Core Well Power Applied to STPCLK# Inactive 0 ns PCI_STP# and CPU_STP# Float to Clocks t130 2 Running t131 Core Well Power Applied to PWROK Active 1 ms PWROK Active to CPU_STP# and PCI_STP# t132 0ns Active PCI_STP# and CPU_STP# Active to Clocks t133 2 PCICLK 3 Stopped SUS[A-C]# Inactive to CPU_STP# and PCI_STP# t134 16 ms Inactive PWROK Active to CPU_STP# and PCI_STP# t135 1RTC1 Inactive PCI_STP# and CPU_STP# Active to Clocks t136 12PCICLK3 Running CPU_STP# and PCI_STP# Inactive to t137 1ms SUS_STAT[1:2]# Inactive t138 SUS_STAT[1:2]# Inactive to SUSCLK Running 1 RTC 1 t139 SUS_STAT[1:2]# Inactive to PCI_RST# Inactive 1 RTC 1 SUS_STAT[1:2]# Inactive to CPU_STP# and t140 2RTC1 PCI_STP# allowed to change t141 PCI_RST# Inactive to CPURST Inactive 1 RTC 1 1. These signals are controlled from the internal RTC clock. One RTC is approximately 32 µs. 2. There are no specific requirements for these timings related to the PIIX4E. The system manufacturer should make sure that the clocks on power up meet any other system specifications. At a minimum, the clocks must be available and stable after time t136. 3. See Figure 38 and Figure 39 for exact PCICLK requirements for use with the PC/PCI DMA and Serial IRQs.

Design Guide 103 Intel® Pentium® III Processor – Low Power/440BX AGPset

8.2 82443BX Host Bridge/Controller Power Sequencing

8.2.1 Power Sequencing Requirements

In systems requiring 5 V tolerance, the REF5V signal must be tied to 5 V. This signal must power up before or simultaneous to VCC. It must power down after or simultaneous to VCC. In a non-5 V tolerant system (3.3 V only), this signal may be tied directly to VCC. There are then no sequencing requirements. Refer to Figure 51 for an example circuit schematic that may be used to ensure the proper REF5V sequencing. This is the same circuit that is recommended for the PIIX4E VREF supply. However, different power planes may supply the PIIX4E core and the 82443BX Host Bridge/Controller (the PIIX4E core may be powered down during STR). In this case a separate circuit must be used for each of the two devices.

VCC must power up before or simultaneous to the AGP supplies (VCC_AGP and AGP_REF) and Low Power GTL+ supplies (VTT and GTL_REF). VCC must power down after or simultaneous to the AGP and Low Power GTL+ supplies. The AGP and Low Power GTL+ supplies must not be powered up while VCC is powered down. There are no other power sequencing requirements for the 82443BX Host Bridge/Controller. Figure 51. REFVCC5 Supply Circuit Schematic

VCC Supply 5V Supply (3.3V)

1k

Schottky Diode 1 uF

To SystemREFVCC5 To System

8.2.2 Intel® 440BX AGPset Power Management

The Intel® 440BX AGPset supports a variety of system-wide low-power modes using the following functions: • Hardware interface with the PIIX4E that is used to indicate: — Suspend mode entry — Resume from suspend — Whether to automatically switch from suspend to normal refresh • Automatic transition from normal to suspend refresh • Optional automatic transition from suspend to normal refresh • Optional CPU reset during resume from Power On Suspend (POS) • Variety of Suspend refresh types: — Self Refresh for SDRAMs — Optional Self Refresh for EDO — Optional CAS Before RAS (CBR) refresh for EDO. An Integrated Ring oscillator is used to provide the time base for the associated logic.

104 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

— Programmable slow refresh (relevant for CBR refresh only) • Isolated I/O pins to significantly reduce power consumption while in POS and STR modes

Based on the above functions, the Intel® 440BX AGPset recognizes the following system-wide low power modes: • STR and POS suspend entry and exit are generally handled in the same manner. The following exceptions are related to POS mode: — The POS resume sequence may or may not include a processor reset. STR, with PCIRST# active always includes a processor reset. — The POS resume sequence requires a hardware transition from suspend to a normal refresh. STR with PCIRST# active requires a software initiated transition. • STD resume is handled in the same way as the power on sequence, including a complete reset of the Intel 440BX AGPset state.

8.2.2.1 System Power Modes

Table 72 provides an overview of how the above features map into system-wide low power modes.

Table 72. System-wide Low-power Modes (Sheet 1 of 2)

POS System 82443BX External Clk Description Exit Suspend State State HCLK PCLK PCIRST

82443BX AGPset is fully on and operating normally. Power On ON N/A Active Active Internal clock gating as well as PCI CLKRUN# may be enabled. CPU This is transparent to the Intel 82443BX STOP_GRANT AGPset since the external HCLK and PCLK are or ON unaffected. The Host Bus is Idle. N/A Active Active QUICK_START Internal clock gating and PCI CLKRUN# may (C2) be enabled. System PLLs remain powered, but are disabled. HCLK clock is kept low. The only guaranteed running clock is SUSCLK. CPU STOP The 82443BX maintains DRAM refresh using Low or CLOCK (C3) POS N Low suspend refresh. Active (DEEP SLEEP) The Intel 82443BX’s internal PLLs are disabled. The 82443BX PCI and AGP arbiters are disabled. NOTE: The processor will generally be powered off during STR (the processor voltage regulator will be controlled by the PIIX4E’s SUSB# signal). In this case, the 82443BX Low Power GTL+ supply (VTT and GTL_REF) should also be controlled by SUSB#, and hence be powered off during STR.

Design Guide 105 Intel® Pentium® III Processor – Low Power/440BX AGPset

Table 72. System-wide Low-power Modes (Sheet 2 of 2)

System PLLs are powered down. The only running clock is the RTC clock and SUSCLK. The 82443BX maintains DRAM refresh using suspend refresh. The 82443BX’s PLLs are disabled. Power On POS The 82443BX PCI and AGP arbiters are Y Low Low Suspend (POS) disabled. When resumed, the 82443BX may or may not generate a processor reset. All 82443BX logic, with the exception of resume and refresh, are inactive. The processor and other components (with the exception of the DRAM and PIIX4E resume logic) are assumed to be powered OFF.

The 82443BX VCC supply is on and all I/O buffers are isolated (with the exception of Suspend to RAM suspend and DRAM signals). POS Y Low Low (STR) The 82443BX Low Power GTL+ supplies should be powered down with the processor. The 82443BX maintains DRAM refresh using a suspend refresh. All 82443BX logic, with the exception of resume and refresh, are inactive. Suspend -to- The entire system is powered OFF except for Disk (STD) or OFF the PIIX4E resume and RTC wells. Upon N/A X X Powered-Off resume, the 82443BX resets its entire state. NOTE: The processor will generally be powered off during STR (the processor voltage regulator will be controlled by the PIIX4E’s SUSB# signal). In this case, the 82443BX Low Power GTL+ supply (VTT and GTL_REF) should also be controlled by SUSB#, and hence be powered off during STR.

106 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

8.2.2.2 System Power-up Sequencing

The waveforms in Figure 52 show the powerup sequence and timing information for the Intel® 440BX AGPset. Table 73 indicates the system power-up sequencing tolerances. Figure 52. System Power-up Sequencing

PIIX4E VCC(SUS)

3 RSMRST# 14

SUS[C:A]#

1 4 PIIX4E VCC(CORE) 5 PIIX4E 9 PWROK

12 SUS_STAT# 2 16 CPU_STP# FLOAT PCI_STP# 7 13

CLOCKS RUNNING

15 PCIRST#

8 17 BX_VCC 6

BXPWROK 11

CPURST#

10 18

Design Guide 107 Intel® Pentium® III Processor – Low Power/440BX AGPset

Table 73. System Power-up Sequencing Tolerances

Sym Parameter Min Max Units Notes

t1 PIIX4E VCC(SUS) nominal to SUS[C:A]# active 1 RTC 1

t2 PIIX4E VCC(SUS) nominal to SUS_STAT[2:1]# active 1 RTC 1

t3 PIIX4E VCC(SUS) nominal to RSMRST# active 1 ms

t4 RSMRST# inactive to SUS[C:A]# inactive 1 2 RTC 1

t5 SUS[B]# inactive to PIIX4E VCC(CORE) nominal 0 ms

t6 SUS[C]# inactive to BX_VCC nominal 0 ms

t7 PIIX4E VCC(CORE) nominal to CPU_STP#, PCI_STP# float 1 RTC 1

t8 PIIX4E VCC(CORE) nominal to PCIRST# active 1 RTC 1

t9 PIIX4E VCC(CORE) nominal to PIIX4E PWROK active 1 ms

t10 BX_VCC nominal to CPURST# active 10 ns

t11 BX_VCC nominal to BXPWROK active 1 ms

t12 BXPWROK active to PIIX4E PWROK active 0 ns 2

t13 PIIX4E PWROK active to CPU_STP#, PCI_STP# active 1 RTC 1

t14 SUS[C:A]# inactive to CPU_STP#, PCI_STP# inactive 16 ms 3

t15 CPU_STP#, PCI_STP# inactive to clocks running 2 PCICLK

t16 CPU_STP#, PCI_STP# inactive to SUS_STAT[2:1]# inactive 1 ms

t17 SUS_STAT[2:1]# inactive to PCIRST# inactive 1 RTC 1

t18 PCIRST# inactive to CPURST# inactive 1 ms NOTES: 1. One RTC unit is approximately 32 µs 2. This parameter only applies if BXPWROK will not transition to an active state within 15 ms of SUS[C:A]# de-assertion 3. This transition requires both a minimum of 16 ms wait for the clock synthesizer PLL lock and PIIX4 PWROK to be active. When PWROK goes active after 16 ms from SUS[C:A]# inactive, the transition will occur a minimum of one RTC period from PWROK active.

108 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

8.2.2.3 Suspend Resume Protocols

The suspend resume sequences are indicated to the 82443BX by the PIIX4E, using SUS_STAT# and PCIRST#. In addition, the 82443BX contains NREF_EN and CRst_En configuration bits that participate in the suspend resume sequences.

As a result of suspend resume, the 82443BX performs the following activities: • Changing its refresh mode • Performing internal and processor reset • Isolate or re-enable normal IO buffers

Table 74 indicates the suspend resume events and activities.

Table 74. Suspend Resume Events And Activities

SUSSTAT# PCIRST# CrstEn Reset Refresh I/O Buffers

Assert Inactive - - Switch to suspend refresh Isolate

Reset Suspend refresh exclude Deassert Active - Enable resume/ref NREF_EN remains logic inactive Auto switch to normal ref Deassert Inactive 0 No resets Enable NREF_EN is set

Reset Auto switch to normal ref Deassert Inactive 1 processor Enable only NREF_EN is set

The requirements for suspending the 82443BX are: • The system must be idle when SUS_STAT# is asserted. There must be no active processor or bus masters’ cycles and there must be no meaningful pending cycle’s information in a chipset or peripheral device’s buffers. • After the assertion of SUS_STAT#, the PIIX4E provides the 82443BX 32 µs with stable power and clocks to perform the necessary suspend sequence. • The PCICLK must not be stopped with CLKRUN# during the suspend sequence. • The 82443BX isolates its IO buffers within less than 32 µs time allocated from SUS_STAT# assertion. — The 82443BX does not isolate PCIRST# (being pulled up) or clock inputs. The clock inputs are driven low by the clock synthesizer, and 32 µs later the clock synthesizer device may be powered down.

The requirements for resuming the 82443BX are: • Power and clocks must be stable for at least 1 ms before SUS_STAT# is deasserted. • When resuming from POS, STPCLK# remains active for about 100 µs after SUS_STAT# deassertion, to allow an automatic switch to normal DRAM operation before processor pending cycles take place.

The 82443BX provides isolation of its I/O buffers during POS and STR. During the events that were specified in Table 74, the isolation takes effect. Table 75 provides information about the state of each of the 82443BX signals during POS and STR.

Design Guide 109 Intel® Pentium® III Processor – Low Power/440BX AGPset

Table 75. Intel® 440BX AGPset Signal States During POS and STR Modes (Sheet 1 of 2)

Signal Name State During POS/STR CPURST# Three-state A[31:3]# Three-state HD[63:0]# Three-state ADS# Three-state BNR# Three-state BPRI# Three-state DBSY# Three-state DEFER# Three-state DRDY# Three-state HIT# Three-state HITM# Three-state HLOCK# HREQ[4:0]# Three-state HTRDY# Three-state RS[2:0]# Three-state RASA[5:0]# / CSA[5:0]# High1 RASB[5:0]# / CSB[5:0]# High1 CKE[3:2] / CSA[7:6]# Low/High2 CKE[5:4] / CSB[7:6]# Low/High2 CASA[7:0]# / DQMA[7:0]# High1 CASB[5,1]# / DQMB[5,1]# High1 GCKE / CKE1 Low/High2 SRAS[B:A]# Low/High2 CKE0 / FENA Low/High2 SCAS[B:A]# High/Low2 MAA[13:0] Driven3 MAB[9:7]# / MAB[13,10] Driven3 MAB[12:11]# Driven3 MAB[6:0]# Driven3 WEA#, WEB# High MD [63:0] Driven3 MECC[7:0] Driven3 AD[31:0] Low DEVSEL# Three-state FRAME# Three-state IRDY# Three-state C/BE[3:0]# Low PAR Low PLOCK# Three-state NOTES: 1. SDRAM Mode: After putting the SDRAMs into self-refresh mode, these signals are driven high. EDO Mode: For self-refresh mode, RAS and CAS are driven low. Otherwise, the 82443BX continues to refresh during the POS/STR state. 2. SDRAM Mode: SRAS#, SCAS#, CKE[5:0] and GCKE are driven to the first value listed. EDO Mode: These signals are driven to the second value listed. 3. MA lines are always driven by the 82443BX, except for MAB[13:11,9:0]# and MAB10, which are three- stated during reset. MD/MECC are always driven by the 82443BX when there is no active cycle. The values driven on MA, MD and MECC are indeterminate during and after reset.

110 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

Table 75. Intel® 440BX AGPset Signal States During POS and STR Modes (Sheet 2 of 2)

Signal Name State During POS/STR TRDY# Three-state SERR# Three-state STOP# Three-state PHOLD# Three-state PHLDA# Three-state WSC# Three-state PREQ[4:0]# Three-state PGNT[4:0]# Three-state PIPE# Three-state SBA[7:0] Three-state RBF# Three-state ST[2:0] Low AD_STBA Three-state AD_STBB Three-state SB_STB Three-state G_FRAME# Three-state G_IRDY# Three-state G_TRDY# Three-state G_STOP# Three-state G_DEVSEL# Three-state G_REQ# Three-state G_GNT# Three-state G_AD[31:0] Low G_C/BE[3:0]# Low G_PAR Low HCLKIN PCLKIN DCLKO Low DCLKRD DCLKWR CRESET# Three-state PCIRST# GCLKIN GCLKO Low TESTIN# SMBCLK Three-state SMBDATA Three-state CLKRUN# Three-state SUSTAT# NOTES: 1. SDRAM Mode: After putting the SDRAMs into self-refresh mode, these signals are driven high. EDO Mode: For self-refresh mode, RAS and CAS are driven low. Otherwise, the 82443BX continues to refresh during the POS/STR state. 2. SDRAM Mode: SRAS#, SCAS#, CKE[5:0] and GCKE are driven to the first value listed. EDO Mode: These signals are driven to the second value listed. 3. MA lines are always driven by the 82443BX, except for MAB[13:11,9:0]# and MAB10, which are three- stated during reset. MD/MECC are always driven by the 82443BX when there is no active cycle. The values driven on MA, MD and MECC are indeterminate during and after reset.

Design Guide 111 Intel® Pentium® III Processor – Low Power/440BX AGPset

8.2.2.4 82443BX Suspend/Resume Sequences and Timing

Table 76 indicates the suspend/resume timing tolerances for Figure 53 through Figure 56.

Table 76. Suspend/Resume Timing Tolerances

Sym Parameter Min Max Unit

t1 BX_VCC stable to BXPWROK asserted. † 1ms t2 BXPWROK asserted to SUS_STAT# inactive 1 ms Clocks running to SUS_STAT# inactive, t3 1ms ensure BX_VCC active and BXPWROK inactive to t4 10 ns CPURST# active SUS_STAT# deasserted to PCIRST# t5 32 µs de-asserted, ensure PCIRST# deasserted to CPURST# t6 1ms deasserted t7 SUS_STAT# deasserted to buffers valid 2 HCLK SUS_STAT# asserted to clocks stopped, t8 32 µs ensure t9 SUS_STAT# asserted to suspend refresh 32 µs t10 SUS_STAT# asserted to buffers isolated 32 µs t11 PCIRST# asserted to CPURST# asserted 10 ns PCIRST# asserted to SUS_STAT# t12 1ms de-asserted, ensure t13 SUS_STAT# de-asserted to normal refresh 32 µs SUS_STAT# de-asserted to CPURST# t14 04HCLK asserted t15 CPURST# pulse width 1 ms † “BX_VCC stable” means BX_VCC is within the specified Functional Operating Range.

112 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

8.2.2.5 Suspend/Resume with PCIRST# Active

The following resume sequence is typically used when resuming from STR. It includes the following components: • BXPWROK must transition from inactive (low) to active (high) a minimum of 1 ms after BX_VCC is within the specified Functional Operating Range. • When 15 ms or more may elapse from the time that the PIIX4E deasserts SUS[C:A]# until BXPWROK is asserted, BXPWROK must be asserted before or simultaneous to PWROK being asserted to the PIIX4E. • Upon resume, the 82443BX detects that the PCIRST# signal is active (low) and drives CPURST# to the processor. Note that CPURST# is driven active based on PCIRST# timing, independent of SUS_STAT# timing. • Based on the assertion of SUS_STAT#, the 82443BX isolates its I/O buffer within 32 µs. • Based on the deassertion of SUS_STAT#, the 82443BX enables its I/O buffer to normal operation within 32 µs. Clock inputs and PCIRST# are never gated by the 82443BX and thus affect it before the deassertion of SUS_STAT#. • Software must release the memory controller from its suspend refresh state to its normal refresh state. • The 82443BX clears its internal state, with the exception of resume/refresh logic, since it sampled PCIRST# asserted.

Figure 53 shows the suspend resume sequence with PCIRST# active. Figure 53. Suspend/Resume with PCIRST# Active

OFF RESET ONSUSPEND ON

BX_VCC 1 BXPWROK 2 8 3

SUS_STAT# 3 CLOCKS Running Running

12 12 5 PCIRST#

4 5 6 6 CPURST# 11 9 13 Refresh Normal Refresh Suspend Refresh Normal Refresh

Buffers Buffers valid Buffers valid

7 10 7

Design Guide 113 Intel® Pentium® III Processor – Low Power/440BX AGPset

8.2.2.6 Suspend/Resume with CPURST#, PCIRST# Inactive

The following resume sequence is typically used when resuming from POS. It includes the following components: • Since PCIRST# signal is inactive, per resume the 82443BX does not drive CPURST# to the processor, since CrstEn is ‘0’. • Based on the assertion of SUS_STAT#, the 82443BX isolates its I/O buffer within 32 µs. • Based on the deassertion of SUS_STAT#, the 82443BX enables its I/O buffer to normal operation within 32 µs. • The 82443BX switches from suspend refresh to normal DRAM operation mode. • The processor starts execution from the instruction just prior to the stop grant request being recognized. The 82443BX switches to normal DRAM operation before the deassertion of STPCLK#. • The 82443BX state is not reset.

Figure 54 shows the suspend/resume sequence with CPURST#, PCIRST# inactive. Figure 54. Suspend/Resume with CPURST#, PCIRST# Inactive

OFF RESET ON SUSPEND ON

BX_VCC 1 BXPWROK 2 8 3

SUS_STAT# 3 CLOCKS Running Running

12 PCIRST# 6 4 5 CPURST# 9 13 Refresh Normal Refresh Suspend Refresh Normal Refresh

Buffers Buffers valid Buffers valid

7 10 7

114 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

8.2.2.7 Suspend/Resume with CPURST Active, PCIRST# Inactive

The following resume sequence is typically used when resuming from POS. It includes the following components: • The PCIRST# signal is inactive, upon resume the 82443BX drives CPURST# to the processor since CrstEn is ‘1’. CPURST# is active for 1 ms. • Based on the assertion of SUS_STAT#, the 82443BX isolates its I/O buffer within 32 µs. • Based on the deassertion of SUS_STAT#, the 82443BX enables its I/O buffer to normal operation within 32 µs. • The 82443BX automatically switches from suspend refresh to normal DRAM operation mode when SUS_STAT# deassertion is detected. • The 82443BX state is not reset.

Figure 55 shows the suspend/resume sequence with CPURST# active, PCIRST# inactive. Figure 55. Suspend/Resume with CPURST# Active, PCIRST# Inactive

OFF RESET ONSUSPEND ON

BX_VCC 1 BXPWROK 2 8 3

SUS_STAT# 3 CLOCKS Running Running

12 PCIRST# 14 15 5 6 4 CPURST# 9 13 Refresh Normal Refresh Suspend Refresh Normal Refresh

Buffers Buffers valid Buffers valid

7 10 7

Design Guide 115 Intel® Pentium® III Processor – Low Power/440BX AGPset

8.2.2.8 Suspend/Resume from STD

The following resume sequence is typically used when resuming from STD. It includes the following components: • When BXPWROK is sampled low ‘0’, the 82443BX undergoes a complete reset and asserts CPURST#. • Based on the deassertion of SUS_STAT#, the 82443BX enables its buffer to normal operation within less than 32 µs. Clock inputs and PCIRST# are never gated by the 82443BX and thus affect it before the deassertion of SUS_STAT#. • Software must release the memory controller from its suspend refresh state to its normal refresh state, and enable refresh with the appropriate refresh rate.

Figure 56 shows the suspend/resume sequence from STD. Figure 56. Suspend/Resume from STD

OFF RESET ONSUSPEND RESET ON

BX_VCC 1 1 BXPWROK 2 8 2

SUS_STAT# 3 3 CLOCKS Running Running

12 12 PCIRST# 4 5 6 4 CPURST# 9

Refresh Normal Refresh Norm

Buffers Buffers valid Valid

7 10 7

116 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

Appendix A Bill of Materials

Table 77 is the bill of materials for the Intel® Pentium® III processor — Low Power/440BX AGPset Reference Design.

Table 77. Bill of Materials (Sheet 1 of 8) Rev. A0 Reference Manufacturer Alternate Description Manufacturer Comments Designator P/N Manufacturing Info Conn, Jumper2,1X2 25-mil sq/ J14, J15 3M 929647-09-02 100-mil space, HDR2 Conn, Jumper3,1X3 25-mil sq/ J20-24 3M 929647-09-03 100-mil space, HDR3 J12 Conn, Fan AMP 173981-3 XU9 PLCC, Socket 28 AMP 822271-1 IC, Clock Generator, CK100, U6 Cypress CY2280PVC-11S SSOP300-48(PIN) IC, Clock Buffer, 18 Output low U16 Cypress CY2318ANZPVC-1 skew, SSOP300-48(PIN) Crystal, 32.768KHz, Y2 Epson MC-405 XTAL/MC-405 J4 Conn, Serial Stack, DB9MX2 FOXCONN DM10156-73 J3 Conn, DB25, DB25FM1 FOXCONN DT11323-R5T Conn, PCI Edge Recept., J7, J8, J9 FOXCONN EH06001-PC-W 145154-120 J5, J6 Conn, ISA Edge Recept., isa-98 FOXCONN EQ04901-S6 JP1 Conn, Floppy, 17X2 Header FOXCONN HL07173-P4 JP3, JP4 Conn, IDE, 20X2 Header FOXCONN HL07206-D2 J11 Conn, Power, 5566DP-20/ATX FOXCONN HM20100-P2 Conn, PS2 Keyboard / Mouse J1 FOXCONN MH11067-D2 Connector Conn, AGP Edge Recept., 120 J13 FOXCONN PC1243K-10 pins, AGP-124 J2 2 USB Stack Connectors FOXCONN UB1112C-D3 BIOS FLASH Memory, U11 INTEL E28F004B5T60 TSOP12X20/40S VLSI, PIIX4, PCI to IDE and ISA U8 Bridge, 324 mBGA, Intel FW82371EB BGA20x20-324 C99, C100, Chip Capacitor, 10pF, 50 V, Kemet C0603C100J5GAC C132, C133, CC0603

Design Guide 117 Intel® Pentium® III Processor – Low Power/440BX AGPset

Table 77. Bill of Materials (Sheet 2 of 8) Rev. A0 Reference Manufacturer Alternate Description Manufacturer Comments Designator P/N Manufacturing Info C22, C42-43, C48-49, C54, C59-65, C70-71, C73, C75-76, C85-87, C90-92, C96-97, C102, C106-108, C111-112, DO NOT C114, POPULATE Chip Capacitor, 0.1 uF, 16 V, C116-118, Kemet C0603C104K4RAC C143, C146, CC0603 C126-127, C203, C210, C129-131, C215 C142, C147, C157, C159-162, C174-176, C181-183, C187-200, C205-206, C208, C226-228 C27-C41, Chip Capacitor, 470 pF, 50 V, C44-C47, Kemet C0603C471K5RAC CC0603 C50-C53 C3-5, C8, C55-57, C94, Cap, Tant, 10 uF, 15 V, C Case, C119-121, Kemet T491C106K016AS 6032 C134, C138, C145, C153 C93, C103-105, Cap, Tant, 47 uF, 20 V, D Case, Kemet T491D476M020AS C128, C152, 7343 C154-156 C2, C6, C58, C72, C84, Cap, Tant, 100 uF, 10 V, D Case, Kemet T495D107M010AS C88, C89, 7343 C95, C109 C1, C7, C23, C66-C68, C74, C77-C82, C101, C113, C115, C141, C158, C163-173, Chip Capacitor, 0.01 uF 50 V, Kemet C0603C103J5RAC C177-180, CC0603 C184-186, C201-202, C204,C207, C211-213, C216-217, C220-C225 U9 IC, PLD, PLCC28, Socket28 LATTICE GAL22V10B-7LJ IC, Linear Voltage Regulator, U23 Linear Tech. LT1117-3.3cst SOT-223

118 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

Table 77. Bill of Materials (Sheet 3 of 8) Rev. A0 Reference Manufacturer Alternate Description Manufacturer Comments Designator P/N Manufacturing Info IC, Linear Voltage Regulator, U5 Linear Tech. LT1117CST SOT-223 40TSOP BIOS Socket, XU11 Meritec 980020-40-01 TSOP12X20/40S XU12, XU13 TIL311 SOCKET, DIP14 MILLMAX 110-99-314-41-001 U25 IC, Logic, 74ACT05, SO14 Motorola MC74ACT05DR FB1-FB-4, FB9 Ferrite Bead, SM1806, Z-Bead Murata BLM41P750S FB5, FB6, Ferrite Bead, SM1806, Z-Bead Murata BLM41A800S FB7, FB8 U22 IC, Logic, 74ALS00, SOIC14 National DM74ALS00M IC, Transceiver, 8-Bit U7 Bidirectional Buffer, SOIC20, National DM74ALS245AWM SO20W Cap, Electrolytic, 220 uF, 25 V, C69, C83, 6.3 mm x 11.2 mm, Panasonic ECE-A1EU221 C98, C110 PCAPR200-300 R48, R52, R98-R100, Chip Resistor, 0 Ohm Shunt, R106, Panasonic ERJ6GEY0R00V 5%, CR0805 R108-R116, R118-R122 R25, R42, R45, R49, Chip Resistor, 1 K, 5%, CR0805 Panasonic ERJ6GEYJ102V R63, R101, R102 R2, R4, R5, R11, R40, R41, R43, R53-R56, Chip Resistor, 10 K, 5%, Panasonic ERJ6GEYJ103V R105, R117, CR0805 R123-124, R127 R1, R3, R88, Chip Resistor, 15 K, 5%, Panasonic ERJ6GEYJ153V R89, R90, R91 CR0805 R9, R24 Chip Resistor, 22, 5%, CR0805 Panasonic ERJ6GEYJ220V R10, R12, R13, R14, Chip Resistor, 220, 5%, CR0805 Panasonic ERJ6GEYJ221V R39, R58, R70 R92-R95 Chip Resistor, 27, 5%, CR0805 Panasonic ERJ6GEYJ270V R20, R44, Chip Resistor, 2.7 K, 5%, Panasonic ERJ6GEYJ272V R57, R71 CR0805 R17-R19, R21, R23, R26, R28, R30, Chip Resistor, 33, 5%, CR0805 Panasonic ERJ6GEYJ330V R32, R34, R36, R38 R103,R104 Chip Resistor, 470, 5%, CR0805 Panasonic ERJ6GEYJ471V R7, R64-R69, Chip Resistor, 4.7 K, 5%, R125, R126, Panasonic ERJ6GEYJ472V CR0805 R128 R72-R87, R96, Chip Resistor, 8.2 K, 5%, Panasonic ERJ6GEYJ822V R107 CR0805

Design Guide 119 Intel® Pentium® III Processor – Low Power/440BX AGPset

Table 77. Bill of Materials (Sheet 4 of 8) Rev. A0 Reference Manufacturer Alternate Description Manufacturer Comments Designator P/N Manufacturing Info Switch-Push Button, S1, S2 Panasonic EVQ-PHP03T PBSW / PNASNC2 RP2, RP3, RP41-RP47, RP54-RP56, Res, Array, SMT, 33, 5%, EXB-V Panasonic EXB33V330JV RP58, RP60, RP61 RP10, RP18, Res, Array, SMT, 1 K, 5%, Panasonic EXB38V102JV RP23 EXB-V RP8-9, RP11, RP13-17, RP19-RP22, RP24, Res, Array, SMT, 10 K, 5%, RP26-33, Panasonic EXB38V103JV EXB-V RP35-36, RP39, RP51-52, RP59 RP1, RP4 Res, Array, SMT, 22, 5%, EXB-V Panasonic EXB38V220JV RP25, RP37, Res, Array, SMT, 2.7 K, 5%, RP49, RP50, Panasonic EXB38V272JV EXB-V RP53 RP57 Res, Array, SMT, 47, 5%, EXB-V Panasonic EXB38V470JV RP5, RP6, Res, Array, SMT, 4.7 K, 5%, Panasonic EXB38V472JV RP7, RP48 EXB-V Res, Array, SMT, 5.6 K, 5%, RP12, RP34 Panasonic EXB-V IC, Logic, Inverter, Schmitt U24 Philips 74LVC14AD Trigger, SOIC14 IC, Logic, 10 Bit Bus Switch, U10 Quality Semi QS3384SO QSOP, SO24W Crystal,14.318 MHz, XTAL, Y1 Raltron AS-14.31818-20 FOX-HC495D F1-F3 Fuse, Drawing, SM250 RayChem SMD250-2 XBT1 Battery Holder Socket Renata HU-2032-1 BT1 Battery Reneta CR2032 D1, D2, D5 Diode, LED, SOT23-A Siemens LGS260-DO U1 VLSI, Super I/O, QFP128 SMSC FDC37B787 C1608C0G1H470JT C122-C125 Chip Capacitor, 47 pF, CC0603 TDK $ C9-C21, C1608X7R1H221KT Chip Capacitor, 220 pF, CC0603 TDK C24-C26 009A U15 IC, Logic, 3-state buffer, SOP-14 TI 74LVC125A U21 IC, Logic, SOP-14 TI 74LVC14A IC, RS232 Transceiver, SOIC20, U3, U4 TI GD75232DW SO20W IC, Logic, Open Drain Buffer, U2 TI SN7407D SOP-14 U12, U13 7 Segment LED display, DIP14 TI TIL311 D3-D4, D6-D7 Schottky Diode, SOT23-E ZETEX BAT54

120 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

Table 77. Bill of Materials (Sheet 5 of 8) Rev. A0 Reference Manufacturer Alternate Description Manufacturer Comments Designator P/N Manufacturing Info R8, R15, R16, Chip Resistor, 124, 1%, CR0805 Panasonic ERJ-6ENF1240V R46, R47 Res, Array, SMT, 270, 5%, RP38, RP40 Panasonic EXB38V271JV EXB-V R300-R307 Chip Resistor, 0, 5%, CR0805 Panasonic ERJ6GEY0R00V R50 Chip Resistor, 680, 5%, CR0805 Panasonic ERJ6GEYJ681V R308 Chip Resistor, 33, 5%, CR0805 Panasonic ERJ6GEYJ330V Chip Resistor, 0 Ohm Shunt, R309 Panasonic ERJ6GEY0R00V 5%, CR0805 Conn, ITP, Vertical Recept., J25 AMP 104078-4 30 pins XU28 SPDIP, Socket 28 AMP 345724-1 C331, C332, Chip Capacitor, 10 uF,16 V, Y5V, C333, C334, AVX Corp 1210YG106ZAT4A CC1210 C335 Central D9, D11 Schottky Diode, SOD-323 CMDSH-3TR Semiconductor Inductor, 1uH, IRMS = 12.5 A, ISAT = 15.3 A, L2 Coiltronics UP3B-1R0 DCRmax = .0034 ohm, UNI-PAC 3B Inductor, 2.2 uH, IRMS = 3.1 A, ISAT = 3.5 A, L3 Coiltronics UP1B-2R2 DCRmax = .0363 ohm, UNI-PAC 1B Chip Resistor, 15 milliohms, 5%, R402 Dale/Vishay WSL-2512 0.015 5% CR2512 Chip Resistor, 3 milliohms, 5%, R329, R403 Dale/Vishay WSL-2512 0.003 5% CR2512 Q2, Q3, Q4 N-Channel FET, 25 V, SOT-23 Fairchild FDV301N U33 Dual N Channel MOSFET, SO8 Fairchild FDS6982 82443BX Host Bridge/ U27 Intel FW82443BX Controller, 492 BGA Pentium® III Processor – Low U26 Power at 500 MHz with 256 Intel KC80526LY500256 Kbyte L2 cache, 495 BGA2 International U34, U35 N Channel MOSFET, SO8 IRF7809A Rectifier International U31 N Channel MOSFET, SO8 IRF7811A Rectifier C230 Cap, Tant., 33 uF, 16 V, 7343 Kemet T495D336M016AS Dual Regulator Controller, LT1708PG#TRSL25 U32 Linear Tech SSOP36 026 Remote/Local Temp Sensor, U30 Maxim MAX1617MEE QSOP16 8-bit CMOS FLASH U28 Microchip PIC16LF873-04I/SP Microcontroller, SPDIP28 Chip Inductor, 4.7 uH, 10%, L1 Murata LQG21N4R7K10 30 mA, .7ohm, CR0805

Design Guide 121 Intel® Pentium® III Processor – Low Power/440BX AGPset

Table 77. Bill of Materials (Sheet 6 of 8) Rev. A0 Reference Manufacturer Alternate Description Manufacturer Comments Designator P/N Manufacturing Info Y3 Crystal, 4 MHz, +/-0.5% Murata CSA4.00MG Schottky Barrier Rectifier, 1 A, On D12 MBRM140T3 40V, 457-04 Semiconductor Schottky Barrier Rectifier, 3 V, On D10 MBRS340T3 40 V, 403-03 Semiconductor C350 Cap, SP, 180 uF, 4 V, UE Panasonic EEFUE0G181R C353, C354, Cap, SP, 270 uF, 2 V, UE Panasonic EEFUE0D271R C355, C356 C343 Cap, Tant., 4.7 uF, 6.3 V, Y Panasonic ECST0JY475R C232, C233, C234, C235, C236, C237, C238, C239, C240, C241, C242, C243, C244, C245, C246, C247, C248, C249, C277, C278, For 700MHz C279, C280, processor, C281, C282, populate C283, C284, C238-C245, C285, C286, C297-C299 C287, C288, Chip Capacitor, 0.1 uF, 16 V, Panasonic ECJ1VB1C104K with .22 uF, C289, C290, X7R, CC0603 X7R, C291, C292, CC 0603: C293, C294, Panasonic C295, C296, ECJ1VB1A22 C305, C306, 4K C307, C308, C309, C310, C312, C313, C314, C315, C316, C317, C318, C319, C323, C327, C328, C336, C338, C358, C359 C250, C251, C252, C253, C254, C255, For 700MHz C256, C257, processor, C258, C259, populate C260, C261, C250-C276 C262, C263, Chip Capacitor, 0.1 uF, 16 V, with 2.2 uF, Panasonic ECJ2VB1C104K C264, C265, X7R, CC0805 X5R, C266, C267, CC 0805: C268, C269, Panasonic C270, C271, ECJ2YB0J225 C272, C273, K C274, C275, C276 Chip Capacitor, 0.1 uF, 25 V, C329, C330 Panasonic ECJ1VB1E104K X7R, CC0603

122 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

Table 77. Bill of Materials (Sheet 7 of 8) Rev. A0 Reference Manufacturer Alternate Description Manufacturer Comments Designator P/N Manufacturing Info Chip Capacitor, 0.47 uF, 16 V, C337 Panasonic ECJ2YB1C474K X7R, CC0805 C339, C342, Chip Capacitor, 1000 pF, 50 V, Panasonic ECJ1VB1H102K C345, C348 X7R,CC0603 Chip Capacitor, 100 pF, 50 V, C347 Panasonic ECUV1H101JCV NPO, CC0603 Chip Capacitor, 10 uF, 10 V, C357 Panasonic ECJ4YB1A106K X5R, CC1210 Chip Capacitor, 15 pF, 50 V C325, C326 Panasonic ECUV1C150JCV NP0, CC0603 Chip Capacitor, 180 pF, 50 V, C341 Panasonic ECUV1H181JCV NPO, CC0603 Chip Capacitor, 1 uF, 10 V, X7R, C344 Panasonic ECJ2YB1A105K CC0805 Chip Capacitor, 20 pF, 16 V, C322 Panasonic ECUV1C200JCV NP0, CC0603 Chip Capacitor, 330 pF, 50 V, C346 Panasonic ECUV1H331JCV NPO, CC0603 Chip Capacitor, 33 pF, 50 V, C349 Panasonic ECUV1H330JCV NPO, CC0603 R334, R391 Chip Resistor, 0, 5%, CR0805 Panasonic ERJ6GEY0R00V R327, R333, Chip Resistor, 1.5K, 5%, R359, R360, Panasonic ERJ6GEYJ152V CR0805 R383 R393, R396, Chip Resistor, 10, 5%, CR0805 Panasonic ERJ6GEYJ100V R399 R332, R342 Chip Resistor, 100, 1%, CR0805 Panasonic ERJ6ENF1000V Chip Resistor, 100K, 5%, R395 Panasonic ERJ6GEYJ015V CR0805 R400, R407, Chip Resistor, 10K, 1%, Panasonic ERJ6ENF0014V R411 CR0805 R323, R336, R350, R347, R361, R397, Chip Resistor, 10k, 5%, CR0805 Panasonic ERJ6GEYJ103V R398, R335, R345 R315 Chip Resistor, 110, 1%, CR0805 Panasonic ERJ6ENF1100V R325, R339, Chip Resistor, 150, 1%, CR0805 Panasonic ERJ6ENF1500V R338 R381, R382, R388, R389, Chip Resistor, 150, 5%, CR0805 Panasonic ERJ6GEYJ151V R390 Chip Resistor, 15K, 5%, R405 Panasonic ERJ6GEYJ153V CR0805 Chip Resistor, 160K, 5%, R401 Panasonic ERJ6GEYJ164V CR0805 R324, R326, Chip Resistor, 1K, 1%, CR0805 Panasonic ERJ6ENF1001V R331

Design Guide 123 Intel® Pentium® III Processor – Low Power/440BX AGPset

Table 77. Bill of Materials (Sheet 8 of 8) Rev. A0 Reference Manufacturer Alternate Description Manufacturer Comments Designator P/N Manufacturing Info R311, R312, R313, R341, R353, R372, R373, R376, Chip Resistor, 1K, 5%, CR0805 Panasonic ERJ6GEYJ102V R377, R379, R392, R316, R317, R318, R319 R394, R409, Chip Resistor, 1M, 5%, CR0805 Panasonic ERJ6GEYJ016V R410 R344, R340, Chip Resistor, 22, 5%, CR0805 Panasonic ERJ6GEYJ220V R343 R380, R387 Chip Resistor, 240, 5%, CR0805 Panasonic ERJ6GEYJ241V R369, R374 Chip Resistor, 270, 5%, CR0805 Panasonic ERJ6GEYJ271V R330 Chip Resistor, 2K, 1%, CR0805 Panasonic ERJ6ENF2001V Chip Resistor, 3.3K, 5%, R375, R378 Panasonic ERJ6GEYJ332V CR0805 R320 Chip Resistor, 330, 5%, CR0805 Panasonic ERJ6GEYJ331V Chip Resistor, 33K, 5%, R408 Panasonic ERJ6GEYJ333V CR0805 R385, R386 Chip Resistor, 47, 5%, CR0805 Panasonic ERJ6GEYJ470V R314, R328, Chip Resistor, 56.2, 1%, Panasonic ERJ6ENF56R2V R384 CR0805 Chip Resistor, 68K, 5%, R406 Panasonic ERJ6GEYJ683V CR0805 Chip Resistor, 7.5K, 1%, R404 Panasonic ERJ6ENF0752V CR0805 R337 Chip Resistor, 75, 1%, CR0805 Panasonic ERJ6ENF0750V D8 Schottky Diode, SOT23-E Zetex BAT54

124 Design Guide Intel® Pentium® III Processor – Low Power/440BX AGPset

Appendix B Schematics

Schematics are provided for the following items listed below. Schematics are available from the Intel Developer’s web site in OrCAD* (version 9.0 or later) and PDF format. • Table of Contents • Block Diagram • Routing Requirements • Pentium® III Processor – Low Power Part 1 — This design will support either the Pentium® III processor – Low Power or the Intel® Celeron™ processor – Low Power in a 495 BGA2 package. • Pentium® III Processor – Low Power Part 2 — When using a processor running at 700 MHz or above, larger value capacitors for high and mid frequency decoupling will be required. A table is provided on this page with the proper stuffing. • 82443BX Part 1 Host, PCI, and AGP • 82443BX Part 2 Memory, Power, and GND • ITP, Thermal Sensor, and Clock Throttling — The ITP, thermal sensor chip, and microcontroller are optional. More information on using a microcontroller to throttle the processor may be found in the Pentium® III Processor Active Thermal Management Technology Application Note (order number 273405). This application note also contains sample microcontroller code. • Processor Voltage Regulator • Mini-PCI Connector (Not Populated) • DIMM0 — This design uses DIMMs instead of SO-DIMMs. For DIMM design guidelines, please see the Intel® 440BX AGPset Design Guide (order number 290634). Note also that Suspend To RAM is not supported as the DIMMs are powered with 3.3 V and not 3.3 VSB. • DIMM1 • DIMM2 (Not Populated) • System Clocks — This design uses a CK100 compatible clock synthesizer instead of a CK100-M or CK100-SM. Because this design uses DIMMs, a CKBF SDRAM buffer is used instead of a CKBF-M. • PCI/ISA Pullups • PCI Connectors 0 and 1 • PCI Connector 2 • AGP Connector • PIIX4E Part 1 • PIIX4E Part 2

Design Guide 125 Intel® Pentium® III Processor – Low Power/440BX AGPset

• IDE Connectors • Super I/O • USB Connectors • ISA Connectors • Serial / Parallel / Floppy • Flash BIOS / Port 80 — The code for the PLD is in Appendix C. • ATX Power Connector • Unused Devices

126 Design Guide 5 4 3 2 1

Intel® Pentium® III Processor - Low Power / 440BX AGPset Reference Design

D D Revision A0

Table of Contents Revision History Aug-24-2001 Table of Contents Page 21 Block Diagram Page 3 - Moved location of pull-up resistor on STPCLK# closer to the PIIX4E. Routing Guidelines Page 4 Pentium® III Processor - Low Power Part 1 Page 5 Pentium® III Processor - Low Power Part 2 Page 6 82443BX Part 1 Host, PCI, and AGP Page 7 82443BX Part 2 Memory, Power, and GND Page 8 C C ITP, Thermal Sensor, and Clock Throttling Page 9 Processor Voltage Regulator Page 10 Mini PCI Connector Page 11 DIMM0 Page 12 DIMM1 Page 13 DIMM2 Page 14 System Clocks Page 15 PCI / ISA Pullups Page 16 PCI Connectors 0 and 1 Page 17 PCI Connector 2 Page 18 AGP Connector Page 19 PIIX4E Part 1 Page 20 B B IDEPIIX4E Conne Partctors 2 Page 21 Super I/O Page 22 USB Connectors Page 23 ISA Connectors Page 24 Serial / Parallel / Floppy Page 25 Flash BIOS / Port 80 Page 26 ATX Power Connector Page 27 Unused Devices Page 28

THIS SCHEMATIC IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER, INCLUDING A ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY A WARRANTY OTHERWISE ARISING OUT OF PROPOSAL, SPECIFICATION OR SAMPLE. No license, express or implied, by estoppel or otherwise, to any Intel Corporation Embedded Intel Architecture Division intellectual property rights is granted herein. 5000 W. Chandler Blvd. Chandler, AZ 85226-3699 Intel disclaims all liability, including liability for infringement of THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT Designed By: Application Design-In Center (Folsom, CA) any proprietary rights, relating to use of information in this BEEN VERIFIED FOR MANUFACTURING AS AN END USER Title Intel® Pentium® III - Low Power / 440BX AGPset Reference Design

specification. Intel does not warrant or represent that such use will PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE Size Document Number Rev not infringe such rights. MISUSE OF THIS INFORMATION. C A0 Date:Monday, August 27, 2001 Sheet 128of 5 4 3 2 1 A B C D E Block Diagram Optional ITP Connector Thermal Sensor Clock Throttle Controller Processor Intel® Pentium® III 4 Page 8 4 Voltage Regulator Processor - Low Power Page 9 Page 4, 5

AGP Connector APIC 82443BX Page 18 Page Host Bus 19 Controller DRAM (DIMM) Page 6, 7 Page 11, 12, 13

3 3 PCI BUS

IDE PCI Mini PCI Connector Page PIIX4E Connectors (not populated) 21 Page Page 16,17 Page 10 19, 20 USB Page 23 ISA BUS

2 2 Flash Bios ISA Super I/O Connectors Port 80 Page 22 System Clocks Page 26 Page 24 Page 14

ATX Power Connector Page 27 PS2 Keyboard / Serial Parallel Floppy Mouse Port Port Connector Page Page 25 Page 25 PCI / ISA Connector Page 22 25 1 Pullups 1 Page 15 Intel Corporation

Embedded Intel Architecture Division 5000 W. Chandler Blvd. Chandler, AZ 85226-3699 Unused Devices THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT Designed By: Application Design-In Center (Folsom, CA) Title Page 28 BEEN VERIFIED FOR MANUFACTURING AS AN END USER Intel® Pentium® III - Low Power / 440BX AGPset Reference Design Size Document Number Rev PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE C A0

MISUSE OF THIS INFORMATION. Date:Monday, August 27, 2001 Sheet 228of A B C D E 5 4 3 2 1 Routing Requirements

General Board Design Requirements >> Right angle traces must not be used. Power Supply Specific Routing Requirements >> Vias for decoupling capacitors must be kept as close as possible to the capacitor pad. >> All traces associated with the input power/ground connectors, and the >> Trace impedance must be 65 ohms, +/- 10% unless otherwise noted. capacitors connected to these connectors, must be routed with minimum D >> GND layers must not be split. length and maximum width. D >> Series terminating resistors must be kept as close to the driving pin as possible. >> All unrelated signals and power planes must be kept away from the >> Daisy chain signals going to more than one point, do not use stubs. switching circuitry. >> Specific routing requirements are included throughout schematic sheets. >> Consult the Voltage Regulator Datasheet for specific routing requirements CPU Routing Requirements >> Consult the Intel® Pentium® III Processor - Low Power/ 440BX AGPset Design Guide for routing Memory Bus Specific Routing Requirements requirements for the following GTL+ signals: >> Consult the 440BX Design Guide for DIMM BPRI#, DEFER#, HRESET#, RS#[2:0], HTRDY#, H_PRDY#, HA#[31:3], ADS#, BNR#, BREQ0#, HD#[63:0], DBSY#, routing guidelines. DRDY#, HIT#, HITM#, HLOCK#, HREQ#[4:0] >> The capacitor C230 should be close to the PLL1 and PLL2 pins, with less than 0.1ohm per route. The inductor L1 should be close to the capacitor. The PLL2 route should be parallel and next to PCI Bus Specific Routing Requirements. the PLL1 route (minimize loop area). Any routing resistance should be inserted between VCCT and >> The PIIX4E must be the last device on the the inductor. Consult the PLL RLC Filter Specification in the Pentium® III processor - Low Power PCI bus. datasheet to determine if routing resistance is required. >> Route THERMDP and THERMDN close together as a pair (no more than 250 mil difference in length), on same layer, in parallel, and 25 mils min from any other trace. >> Route VREF using 24 mil minimum width trace, and separate from all other traces by 25 mils minimum.

C >> Place ITP port near the processor. ITP port must be at end of following traces: HRESET#, C H_PRDY#, H_TCK, H_TMS. Series termination resistors for HRESET#, H_PRDY#, H_TCK, H_TMS must be placed less than 1" from port. >> Consult the Decoupling Recommendations in the Intel® Pentium® III Processor - Low Power/ 440BX AGPset Design Guide for processor decoupling capacitor layout recommendations.

Clock Specific Routing Requirements Note: This design uses a CK100 clock synthesizer. >> Clocks must be routed on the same layer internally to contain EMI. Space all other signals at least 2W from clock traces. >> Intel recommends that the clock series resistors not be placed in the R-packs to allow individual tunability if necessary. >> Minimize via’s on all clock traces. >> Do not allow the clock traces to cross a plane split. >> CPUCLK0 - Follow host clock layout guidelines in Pentium III processor - Low Power/ 440BX AGPset design guide >> PCICLK7 should be 0" to 4" greater than the length of CPUCLK0 (from CK100 to 82443BX). PCICLK7 should be the same length as PCICLKF. PCI Clocks PCICLK[4:1] must be matched in length and should equal the length of PCICLK7 - 2.5". >> GCLKOUT should be less than or equal to 1". GCLK should equal GCLKIN + 3.3" B >> BXDCLKO must be between 1" to 6" in length. All SDRAM clocks SDCLK[11:0] must be matched in B length; this length should be between 1" and 3". BxFBCLK must be 2.5" longer that SDCLKx.

IDE Specific Routing Requirements >> Place IDE series terminating resistors within 1" of PIIX4E. >> Place IDE connector within 4" of PIIX4E.

A A

Intel Corporation

Embedded Intel Architecture Division 5000 W. Chandler Blvd. Chandler, AZ 85226-3699 Designed By: Application Design-In Center (Folsom, CA)

Title THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR Intel® Pentium® III - Low Power / 440BX AGPset Reference Design MANUFACTURING AS AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR Size Document Number Rev C A0

THE MISUSE OF THIS INFORMATION. Date:Monday, August 27, 2001 Sheet 328of 5 4 3 2 1 5 4 3 2 1 Pentium® III Processor - Low Power Part 1

U26A

6 HA#[31:3] L3 D10 HA#3 K3 A#3 D#0 D11 HD#0 HA#4 J2 A#4 D#1 C7 HD#1 HA#5 L4 A#5 D#2 C8 HD#2 HA#6 A#6 D#3 HD#3 L1 B9 U26C HA#7 K5 A#7 Intel® Pentium® III Processor D#4 A9 HD#4 HA#8 K1 A#8 D#5 C10 HD#5 HA#9 J1 A#9 Low Power D#6 B11 HD#6 HA#10 J3 A#10 D#7 C12 HD#7 HA#11 A#11 D#8 HD#8 D K4 B13 D HA#12 G1 A#12 D#9 A14 HD#9 BGA2 HA#13 H1 A#13 D#10 B12 HD#10 HA#14 E4 A#14 D#11 E12 HD#11 A15 HA#15 A#15 D#12 HD#12 NC1 F1 B16 A16 AA11 H_TCK 8 HA#16 F4 A#16 D#13 A13 HD#13 A17 NC2 TCLK AD13 HA#17 A#17 D#14 HD#14 NC3 VREF, VID TDI H_TDI 8 F2 D13 C14 AC15 H_TDO 8 HA#18 E1 A#18 D#15 D15 HD#15 D8 NC4 TDO AD14 HA#19 A#19 D#16 HD#16 NC5 Test/ Debug & Unused TMS H_TMS 8 C4 D12 D14 AA14 H_TRST# 8 HA#20 D3 A#20 D#17 B14 HD#17 D16 NC6 TRST# AB20 HA#21 A#21 D#18 HD#18 NC7 PREQ# H_PREQ# 8 D1 E14 E15 W20 H_PRDY# 8 HA#22 E2 A#22 D#19 C13 HD#19 G2 NC8 PRDY# HA#23 D5 A#23 Host Interface D#20 A19 HD#20 G5 NC9 W19 HA#24 D4 A#24 D#21 B17 HD#21 G18 NC10 BPM1# W21 HA#25 C3 A#25 D#22 A18 HD#22 H3 NC11 BPMO# Y21 HA#26 C1 A#26 D#23 C17 HD#23 H5 NC12 BP3# AA21 HA#27 B3 A#27 D#24 D17 HD#24 J5 NC13 BP2# HA#28 HD#25 A3 A#28 D#25 C18 M4 NC14 HA#29 B2 A#29 D#26 B19 HD#26 M5 NC15 AD20 HA#30 C2 A#30 D#27 D18 HD#27 P3 NC16 TP1 H4 HA#31 HD#28 A4 A#31 D#28 B20 P4 NC17 TP2 AA17 HD#29 A5 A#32 D#29 A20 AA5 NC18 TP3 G4 VCCT HD#30 B4 A#33 D#30 B21 AA19 NC19 TP4 HD#31 C5 A#34 D#31 D19 AC3 NC20 HD#32 NC21 A#35 D#32 C21 AC17 AD17 R311 1K 6 HREQ#[4:0] HD#33 NC22 TESTHI T2 D#33 E18 AC20 Y5 R312 1K HREQ#0 HD#34 NC23 TESTLO1 V4 REQ#0 D#34 C20 AD15 N5 R313 1K HREQ#1 HD#35 NC24 TESTLO2 V2 REQ#1 D#35 F19 HREQ#2 HD#36 W3 REQ#2 D#36 D20 VCCT HREQ#3 HD#37 W5 REQ#3 D#37 D21 AB19 R2 HREQ#4 HD#38 Res GHI# REQ#4 D#38 H18 HD#39 W2 D#39 F18 HD#40 AB2 RP# D#40 J18 AD19 R314 56 1% 6 ADS# HD#41 RTTIMPEDP ADS# D#41 F21 L1 AA16 R315 110 1% D#42 HD#42 EDGECTRLP AA1 E20 4.7uH L2 AERR# D#43 HD#43 PLL1 AD9 H19 C230 M2 IERR# D#44 HD#44 PLL2 AB1 E21 33uF P2 AP0# D#45 HD#45 CLKREF H_CLKREF Y2 J20 AA9 AP1# D#46 HD#46 CMOSREF1 H_CMOSREF C E6 H21 AD18 C BERR# D#47 HD#47 CMOSREF2 V21 L18 E5 BINIT# D#48 HD#48 VREF1 G20 E16 VCCT D#49 HD#49 VREF2 C6 P18 E17 6 BREQ0# BRQ0# D#50 HD#50 VREF3 U4 G21 F5 AA12 R316 1K 6 BPRI# BPRI# D#51 HD#51 VREF4 BSEL0 T4 K18 F17 AB15 R317 1K 6 BNR# BNR# D#52 HD#52 VREF5 BSEL1 R1 K21 U5 R318 1K 6 HLOCK# LOCK# D#53 HD#53 VREF6 H_PIC M18 Y17 R319 1K D#54 HD#54 VREF7 FLUSH# V1 L21 Y18 6 HIT# HIT# D#55 HD#55 VREF VREF8 Y4 R19 6 HITM# HITM# D#56 HD#56 U3 K19 6 DEFER# DEFER# D#57 HD#57 9 VID[4:0] T20 6 RS#[2:0] D#58 HD#58 RS#0 U1 RS#0 D#59 J21 HD#59 VID0 AD2 VID0 RS#1 AA2 RS#1 D#60 L20 HD#60 VID1 AD3 VID1 RS#2 W1 RS#2 D#61 M19 HD#61 VID2 AD4 VID2 Y1 RSP# D#62 U18 HD#62 VID3 AC4 VID3 6 HTRDY# U2 TRDY# D#63 R18 HD#63 VID4 AB4 VID4

6 DBSY# AA3 DBSY# DEP0# V20 HD#[63:0] 6 6 DRDY# T1 DRDY# DEP1# T21 DEP2# U21 AB12 R21 15,20 SLP# SLP# DEP3# BGA2_10 8,20 STPCLK# AC11 STPCLK# DEP4# V18 DEP5# P21 15,20 A20M# AD10 A20M# DEP6# P20 19 SMI# AB10 SMI# DEP7# U19 H_FERR# AC12 FERR# FLUSH# AC9 FLUSH# 15,20 IGNNE# AC13 IGNNE# 27 H_PWROK H_PWROK V5 PWRGOOD THERMDA AA15 THERMDP 8 THERMDC AB16 THERMDN 8

15,20 NMI AC19 LINT1/NMI AB18 LINT0/INTR BCLK M3 CPUCLK0 CPUCLK0 6,14 15,19,20 INTR >> LAYOUT: Place as close as possible to CPU PICD0 AB21 H_PIC AA10 Y20 V2_5 B 15,20 INIT INIT# PICD1 B 6,8 HRESET# H_RST# A6 RESET# PICCLK AA18 CPUCLK0

BGA2_10 Note: APIC is disabled. R320 20pF 330 C231 EMPTY

H_PWROK Do Not Populate

CPU PWROK Level Pull-up CPU Clock Decoupling

V2_5 * Reference voltage for processor. There are 8 VCCT V2_5 V2_5 Fairchild: VREF pins. Place 1 capacitor near every 2 VREF VCCT 25V pins. Id=250uA @ Vgs=0.85V typ R323 ** Make VREF as short and fat as possible. Use R324 R325 VCCT 10K Max = 1.5V R326 1K 150 at least 24 mil line. 1K 1% 1% 1% R327 R329 R328 FERR# 20 1.5K VREF H_CLKREF H_CMOSREF 56 VCCT 1% 3 3m Q2 5% R330 H_RST# FDV301N 3 mOhm resistor C232 C233 C234 C235 2K C236 R331 C237 R332 A 1% 0.1uF 1K 0.1uF 100 A 1 R333 for current 0.1uF 0.1uF 0.1uF 0.1uF 16V 1% 16V 1% 1.5K measurement of 16V 16V 16V 16V X7R X7R X7R X7R X7R X7R VCCT supply. 2 H_FERR# Intel Corporation System Bus Clock Reference CMOS Reference Voltage Embedded Intel Architecture Division GTL+ Reference Voltage Divider Network CPU Reset GTL+ Pull-up 5000 W. Chandler Blvd. FERR# Level Shifter Divider Network (1.25V) Divider Network (1V) Chandler, AZ 85226-3699 Designed By: Application Design-In Center (Folsom, CA) THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR Title MANUFACTURING AS AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR Intel® Pentium® III - Low Power / 440BX AGPset Reference Design Size Document Number Rev THE MISUSE OF THIS INFORMATION. C A0 Date:Monday, August 27, 2001 Sheet 428of 5 4 3 2 1 5 4 3 2 1

Pentium® III Processor - Low Power Part 2 VCCCORE

C238 C239 C240 C241 C242 C243 C244 C245 C246 C247 C248 C249 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R

U26B A2 A7 A8 A12 A21 B1 B5 B6 B7 B8 B10 B15 B18 C9 C11 C15 C16 C19 D2 D6 D7 D9 E3 E7 E8 E9 E10 E11 E13 E19 F3 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F20 G3 G19 VCCCORE H8

VCC_CORE GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND H10 D VCC_CORE D H12 VCC_CORE < LAYOUT > H14 VCC_CORE GND H2 Place homogeneously underneath the die. Processor Core Voltage (VCCCORE) H16 VCC_CORE GND H7 High-Frequency Decoupling Capacitors J7 VCC_CORE GND H9 J9 VCC_CORE GND H11 J11 VCC_CORE GND H13 J13 H15 VCC_CORE GND VCCCORE J15 VCC_CORE GND H20 K8 VCC_CORE BGA2 GND J4 K10 VCC_CORE GND J8 K12 VCC_CORE Power Supply GND J10 K14 VCC_CORE GND J12 K16 VCC_CORE GND J14 L7 VCC_CORE GND J16 L9 J19 C250 C251 C252 C253 C254 C255 C256 C257 C258 C259 C260 C261 C262 C263 VCC_CORE GND 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF L11 VCC_CORE GND K2 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V L13 VCC_CORE GND K7 X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R L15 VCC_CORE GND K9 M8 VCC_CORE GND K11 M10 VCC_CORE GND K13 M12 VCC_CORE GND K15 M14 VCC_CORE GND K20 M16 VCC_CORE GND L5 N7 VCC_CORE GND L8 N9 VCC_CORE GND L10 VCCCORE N11 VCC_CORE GND L12 N13 VCC_CORE GND L14 N15 VCC_CORE GND L16 P8 VCC_CORE GND L19 P10 VCC_CORE GND M7 P12 VCC_CORE GND M9 P14 VCC_CORE GND M11 C264 C265 C266 C267 C268 C269 C270 C271 C272 C273 C274 C275 C276 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF P16 VCC_CORE GND M13 R7 VCC_CORE GND M15 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V R9 VCC_CORE GND M20 X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R R11 VCC_CORE GND N2 R13 VCC_CORE GND N3 C R15 VCC_CORE GND N4 C T8 VCC_CORE GND N8 T10 VCC_CORE GND N10 T12 VCC_CORE GND N12 T14 VCC_CORE GND N14 T16 VCC_CORE GND N16 U7 VCC_CORE GND N18 < LAYOUT > U9 VCC_CORE GND N19 VCCT U11 VCC_CORE N20 Place around die as close to the die as flex GND Processor Core Voltage (VCCCORE) U13 VCC_CORE GND P5 solution allows. Less than 0.8 inches away. U15 VCC_CORE GND P7 Mid-Frequency Decoupling Capacitors G6 VCCT GND P9 G7 VCCT GND P11 G8 VCCT GND P13 VCCT G9 VCCT GND P15 G10 VCCT GND P19 G11 VCCT GND R3 G12 VCCT GND R4 G13 VCCT GND R5 G14 VCCT GND R8 G15 VCCT GND R10 C277 C278 C279 C280 C281 C282 C283 C284 C285 C286 G16 VCCT GND R12 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF G17 VCCT GND R14 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V H6 VCCT GND R16 X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R H17 VCCT GND R20 J6 VCCT GND T3 J17 VCCT GND T5 K6 VCCT GND T7 K17 VCCT GND T9 L6 VCCT GND T11 L17 VCCT GND T13 VCCT M6 VCCT GND T15 M17 VCCT GND T18 N6 VCCT GND T19 N17 VCCT GND U8 P1 VCC_CORE GND U10 P6 VCCT GND U12 VCCT GND C287 C288 C289 C290 C291 C292 C293 C294 C295 C296 B P17 U14 B R6 VCCT GND U16 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF R17 VCCT GND U20 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V GND X7R X7R X7R X7R X7R X7R X7R X7R X7R X7R T6 VCCT V3 GND T17 VCCT V19 U6 VCCT GND W4 U17 VCCT GND W18 V6 VCCT GND Y3 V7 VCCT GND Y9 V8 VCCT GND Y10 V9 VCCT GND Y11 V10 VCCT GND Y12 V11 VCCT GND Y13 V12 VCCT GND Y14 V13 VCCT GND Y15 < LAYOUT > V14 VCCT GND Y16 V15 VCCT GND Y19 Place around die. Less than 0.25 inches away System Bus Buffer Voltage (VCCT) V16 VCCT GND AA4 from VCCT vias (balls). V17 VCCT GND AA13 High-Frequency Decoupling W6 VCCT GND AA20 Capacitors W7 VCCT GND AB3 VCCCORE W8 VCCT GND AB5 W9 VCCT GND AB9 W10 VCCT GND AB11 W11 VCCT GND AB13 W12 VCCT GND AB14 Decoupling Capacitor Ref Des < 700MHz 700MHz W13 VCCT GND AB17 C297 C298 C299 W14 VCCT GND AC1 0.1uF 0.1uF 0.1uF VCCCORE High Freqency C238-C249 0.1uF 0.22uF W15 VCCT GND AC2 16V 16V 16V VCCT W16 VCCT GND AC5 X7R X7R X7R VCCCORE High Freqency C297-C299 No Pop 0.22uF W17 VCCT GND AC10 Y6 VCCT GND AC14 VCCCORE Mid Freqency C250-C276 0.1uF 2.2uF Y7 VCCT GND AC16 Y8 VCCT GND AC18 VCCT High Freqency C277-C296 0.1uF 0.1uF AA6 VCCT GND AC21 C300 C301 C302 C303 C304 AA7 VCCT GND AD1 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF VCCT High Freqency C300-C304 No Pop No Pop AA8 VCCT GND AD5 16V 16V 16V 16V 16V AB6 VCCT GND AD16 X7R X7R X7R X7R X7R A AB7 VCCT GND AD21 A AB8 VCCT AC6 VCCT VCCT VCCT VCCT VCCT VCCT BGA2_10

AC7 AC8 AD6 AD7 AD8 Intel Corporation

Embedded Intel Architecture Division 5000 W. Chandler Blvd. Chandler, AZ 85226-3699 THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT Designed By: Application Design-In Center (Folsom, CA) BEEN VERIFIED FOR MANUFACTURING AS AN END USER Title Intel® Pentium® III - Low Power / 440BX AGPset Reference Design

PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE Size Document Number Rev MISUSE OF THIS INFORMATION. C A0 Date:Monday, August 27, 2001 Sheet 528of 5 4 3 2 1 5 < LAYOUT > Silkscreen 4 3 2 1 Put 82443BX pin numbers on both 82443BX Part 1 top and bottom layers. Host, PCI, and HD#[63:0] 4 GAD[31:0] 18 AGP U27-1 U27-2 4 HA#[31:3] 10,16,17,19 AD[31:0] G25 B22 K6 AB5 HA#3 H22 HA3# HD0# D22 HD#0 AD0 K2 AD0 GAD0 AE2 GAD0 HA#4 G23 HA4# HD1# E21 HD#1 AD1 K4 AD1 GAD1 AD3 GAD1 HA#5 H23 HA5# HD2# A22 HD#2 AD2 K3 AD2 GAD2 AD2 GAD2 HA#6 G24 HA6# HD3# D21 HD#3 AD3 K5 AD3 GAD3 AD1 GAD3 HA#7 F26 HA7# HD4# C21 HD#4 AD4 J1 AD4 GAD4 AC3 GAD4 HA#8 G26 HA8# HD5# A21 HD#5 AD5 J2 AD5 GAD5 AC1 GAD5 HA#9 G22 HA9# HD6# C20 HD#6 AD6 H2 AD6 GAD6 AB4 GAD6 HA#10 HA10# HD7# HD#7 AD7 AD7 GAD7 GAD7 D F22 B21 H1 AB1 D HA#11 F23 HA11# HD8# E20 HD#8 AD8 J5 AD8 GAD8 AA5 GAD8 HA#12 F24 HA12# HD9# A20 HD#9 AD9 H3 AD9 GAD9 AA3 GAD9 HA#13 F25 HA13# HD10# E19 HD#10 AD10 H5 AD10 GAD10 AA4 GAD10 HA#14 E23 HA14# HD11# B20 HD#11 AD11 H4 AD11 GAD11 AA2 GAD11 HA#15 E26 HA15# HD12# E18 HD#12 AD12 G1 AD12 GAD12 AA1 GAD12 HA#16 E25 HA16# HD13# D20 HD#13 AD13 G2 AD13 82443BX GAD13 Y5 GAD13 HA#17 D25 HA17# HD14# D19 HD#14 AD14 G4 AD14 492 BGA GAD14 Y3 GAD14 HA#18 D26 HA18# 82443BX HD15# D18 HD#15 AD15 D1 AD15 GAD15 W1 GAD15 HA#19 B25 HA19# HD16# C19 HD#16 AD16 D3 AD16 GAD16 V2 GAD16 HA#20 C26 HA20# 492 BGA HD17# B19 HD#17 AD17 D2 AD17 GAD17 W2 GAD17 HA#21 A25 HA21# HD18# A18 HD#18 AD18 C1 AD18 GAD18 U5 GAD18 HA#22 C25 HA22# HD19# A19 HD#19 AD19 A2 AD19 GAD19 V1 GAD19 HA#23 HA23# HD20# HD#20 AD20 AD20 GAD20 GAD20 A24 HOST INTERFACE B18 C3 INTERFACE PCI U4 HA#24 D24 HA24# HD21# C17 HD#21 AD21 B3 AD21 GAD21 U3 GAD21 HA#25 C23 HA25# HD22# E17 HD#22 AD22 D4 AD22 GAD22 U1 GAD22 HA#26 B24 HA26# HD23# D17 HD#23 AD23 E5 AD23 GAD23 T3 GAD23 HA#27 HD#24 AD24 GAD24 C24 HA27# HD24# B17 A4 AD24 GAD24 T4 HA#28 A23 HA28# HD25# C16 HD#25 AD25 D5 AD25 GAD25 T2 GAD25 HA#29 E22 HA29# HD26# A17 HD#26 AD26 B4 AD26 GAD26 T1 GAD26 HA#30 HD#27 AD27 GAD27 D23 HA30# HD27# C15 B5 AD27 GAD27 U6 HA#31 HD#28 AD28 AD28 GAD28 GAD28 HA31# HD28# B16 A5 R3 HD#29 AD29 AD29 GAD29 GAD29 B23 HD29# D16 E6 R4 4,8 HRESET# HD#30 AD30 AD30 GAD30 GAD30 K21 CPURST# HD30# A16 C6 R2 4 ADS# HD#31 AD31 AD31 GAD31 GAD31 H24 ADS# HD31# B15 4 BNR# HD#32 10,16,17,19 -C/BE[3:0] GC/BE#[3:0] 18 H26 BNR# HD32# A15 J4 AB2 4 BPRI# HD#33 -C/BE0 C/BE0# GC/BE0# GC/BE#0 BPRI# HD33# D14 G3 Y4 HD#34 -C/BE1 C/BE1# GC/BE1# GC/BE#1 L23 HD34# D15 E4 V4 4 DBSY# HD#35 -C/BE2 C/BE2# GC/BE2# GC/BE#2 J26 DBSY# HD35# B13 C4 U2 4 DEFER# HD#36 -C/BE3 C/BE3# GC/BE3# GC/BE#3 K23 DEFER# HD36# C14 4 DRDY# HD#37 L24 DRDY# HD37# E14 E2 W3 4 HIT# HD#38 10,15,16,17,19 -FRAME FRAME# GFRAME# GFRAME# 18 L22 HIT# HD38# D13 F3 W5 4 HITM# HITM# HD39# HD#39 10,15,16,17,19 -DEVSEL DEVSEL# GDEVSEL# GDEVSEL# 18

K22 A13 E1 AGP INTERFACE V5 4 HLOCK# HD#40 10,15,16,17,19 -IRDY IRDY# GIRDY# GIRDY# 18 H25 HLOCK# HD40# D12 F5 W4 4 HTRDY# HD#41 10,15,16,17,19 -TRDY TRDY# GTRDY# GTRDY# 18 B26 HTRDY# HD41# B12 F4 Y1 4 BREQ0# HD#42 10,15,16,17,19 -STOP STOP# GSTOP# GSTOP# 18 BREQ0# HD42# B14 G5 Y2 4 RS#[2:0] HD#43 10,15,16,17,19 PAR PAR GPAR GPAR 18 K26 HD43# C13 F1 RS#0 HD#44 10,15,16,17,19 -SERR SERR# L26 RS#0 HD44# E13 F2 L5 RS#1 HD#45 10,15,16,17 -PLOCK PLOCK# GREQ# GREQ# 18 C RS#1 HD45# C RS#2 L25 D11 HD#46 GGNT# L3 GGNT# 18 RS#2 HD46# A12 B6 4 HREQ#[4:0] HD47# HD#47 15,19 -PHOLD PHOLD# HREQ#0 J22 B11 HD#48 15,19 -PHOLDA D6 PHLDA# GCLKOUT P5 GCLKOUT J23 HREQ#0 HD48# A11 AE3 N5 HREQ#1 HREQ#1 HD49# HD#49 19 WSC# WSC# GCLKIN GCLKIN HREQ#2 K24 B7 HD#50 MGT ARB&PWR PCI K25 HREQ#2 HD50# C12 HREQ#3 HREQ#3 HD51# HD#51 J25 C8 A6 N3 HREQ#4 HREQ#4 HD52# HD#52 15,16,19 -PREQ0 PREQ0#/IOREQ# SB-STB GSB_STB 18 B10 C7 K1 HD53# HD#53 15,16,19 -PREQ1 PREQ1# SBA0 SBA0 SBA[7:0] 18 V3_3 A10 F10 M2 HD54# HD#54 15,17,19 -PREQ2 PREQ2# SBA1 SBA1 N23 A9 D8 M1 4,14 CPUCLK0 CPUCLK0 HCLKIN HD55# HD#55 10,15,19 -PREQ3 PREQ3# SBA2 SBA2 M25 A7 D10 N2 TESTIN# HD56# HD#56 15 -PREQ4 PREQ4# SBA3 SBA3 E11 P2 HD57# HD#57 SBA4 SBA4 R334 M26 D9 V3_3 E7 P4 CRESET# HD58# HD#58 15,16 -PGNT0 PGNT0#/IOGNT# SBA5 SBA5 0 A3 C11 D7 P3 10,16,17,18,19 -PCIRST PCIRST# HD59# HD#59 15,16 -PGNT1 PGNT1# SBA6 SBA6 C10 E10 R1 HD60# HD#60 15,17 -PGNT2 PGNT2# SBA7 SBA7 B8 E8 HD61# HD#61 10,15 -PGNT3 PGNT3# VGTLREF_BX M23 A8 R335 E9 M4 GTLREFA HD62# HD#62 15 -PGNT4 PGNT4# RBF# GRBF# 18 E16 B9 10K M3 GTLREFB HD63# HD#63 PIPE# GPIPE# 18 20,27 PWROK AF3 BX-PWROK GST[2:0] 18 VCCT M24 AC4 L4 VTTA 10,19 CLKRUN# CLKRUN# ST0 GST0 F17 L2 VTTB ST1 GST1 14 PCICLK7 B2 PCLKIN ST2 L1 GST2 P22 RESVA V3_3 AE22 AD4 SUSTAT# GADSTB-A AC2 GAD_STB0 18 RESVB VAGPREF AE23 RESVC GADSTB-B T5 GAD_STB1 18 AB22 RESVD REFVCC C2 REFVCC AGPREFV N4 R336 VCCT 10K C305 0.1uF 20 SUS_STAT1# R337 443BX_10 443BX_10 >> LAYOUT: Place as 75 1% close as possible to VGTLREF_BX 82443BX.

B B R338 150 1% THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AS AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE BX GTL+ Reference Voltage MISUSE OF THIS INFORMATION. ( 2/3 VCCT +/- 2%)

V3_3 >> LAYOUT: Place at corners of 82443BX >> LAYOUT: Place as close >>LAYOUT: GROUND PADS CPUCLK0 as possible to BX. within inner ring of balls

of BX on bottom layer V3_3 >>LAYOUT: Place cap 0.1uF VGTLREF_BX C306 C307 C308 C309 C310 within 1/2 inch of 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF BX. C311 R339 16V 16V 16V 16V 16V EMPTY TP 150 V3_3 V5_0 TP19 1%

C312 C313 1 VAGPREF Do Not Populate 0.1uF 0.1uF GCLKIN TP TP

3 TP20 TP21 R340 1 D8 R341 1 22 R342 V3_3 TP 100 2 1K GCLKOUT BX Host Clock Decoupling GTLREF Decoupling BAT54 TP22 1% 1

1 REFVCC PCICLK7 >>LAYOUT: place cap within 18 GCLK C314 C315 C316 C317 C318 >>LAYOUT: Place cap 1/2 inch of BX. C319 R343 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF GCLKIN 0.1uF 22 A 16V 16V 16V 16V 16V within 1/2 inch of A BX. C320 AGP clock signals BX AGP Reference Voltage EMPTY 0.1uF (1.18V < AGPREF < 1.45V) C321 Do Not Populate EMPTY Intel Corporation Do Not Populate 82443BX Bottom View Embedded Intel Architecture Division 5000 W. Chandler Blvd. BX 5V Tolerant Sequencing Chandler, AZ 85226-3699 82443BX Power Decoupling Caps BX PCI Clock Decoupling AGP Clock Decoupling Circuit Designed By: Application Design-In Center (Folsom, CA) Title Intel® Pentium® III - Low Power / 440BX AGPset Reference Design

Size Document Number Rev C A0

Date:Monday, August 27, 2001 Sheet 628of 5 4 3 2 1 5 4 3 2 1 82443BX Part 2 Memory, Power, and GND

11,12,13 MD[63:0] U27-3 MAA[13:0] 11,12 AF4 AF17 V3_3 MD0 MAA0 MD0 AE4 AB16 MAA0 MD1 MAA1 MD1 AF5 AE17 MAA1 MD2 MAA2 U27-4 MD2 AD6 AC17 MAA2 MD3 MAA3 MD3 AE6 AF18 MAA3 MD4 MAA4 MD4 AB7 AE19 MAA4 MD5 MAA5 MD5 AC7 AF19 MAA5 B1 A1 D MD6 MAA6 D MD6 AF7 AC18 MAA6 F7 VCC VSS A14 MD7 MAA7 MD7 AB8 AC19 MAA7 F9 VCC VSS A26 MD8 MD8 MAA8 MAA8 VCC VSS AB9 MD9 MAA9 AE20 F18 C5 MD9 AC9 AD20 MAA9 F20 VCC VSS C9 MD10 MD10 MAA10 MAA10 VCC VSS AE9 MD11 MAA11 AF21 G6 C18 MD11 AB10 AC21 MAA11 G21 VCC VSS C22 MD12 MD12 MAA12 MAA12 VCC VSS AC10 MD13 MAA13 AF25 J6 E3 MD13 AF10 MAA13 J21 VCC VSS E12 MD14 MD14 VCC 82443BX VSS AD11 MD15 MAB#[13:0] 13 L11 E15 MD15 Y24 AD16 L13 VCC VSS E24 MD16 MD16 MAB0# MAB#0 VCC 492 BGA VSS Y25 MD17 MAB1# AC16 L14 F6 MD17 W23 82443BX AD17 MAB#1 L16 VCC VSS F8 MD18 MD18 MAB2# MAB#2 VCC VSS W24 MD19 492 BGA MAB3# AB17 M12 F19 MD19 W26 AE18 MAB#3 M15 VCC VSS F21 MD20 MD20 MAB4# MAB#4 VCC VSS W25 MD21 MAB5# AD19 N11 H6 MD21 V26 AB18 MAB#5 N16 VCC VSS H21 MD22 MD22 MAB6# MAB#6 U24 MEMORY INTERFACE AB19 N22 VCC VSS J3 MD23 MD23 MAB7# MAB#7 VCC VSS U23 MD24 MAB8# AF20 N26 J24 MD24 T22 AC20 MAB#8 P1 VCC VSS L12 MD25 MD25 MAB9# MAB#9 T23 AB20 P11 VCC VSS L15 MD26 MD26 MAB10 MAB10 T26 AE21 P16 VCC VSS M5 MD27 MD27 MAB11# MAB#11 R24 AD21 R12 VCC VSS M11 MD28 MD28 MAB12# MAB#12 R25 AF22 R15 VCC VSS M13 MD29 MD29 MAB13 MAB#13 P23 T11 VCC VSS M14 MD30 MD30 N25 T13 VCC VSS M16 MD31 MD31 AC5 AB14 T14 VCC VSS M22 MD32 MD32 CSA0#/RASA0# CS_A0# 11 AE5 AF15 T16 VCC VSS N1 MD33 MD33 CSA1#/RASA1# CS_A1# 11 AB6 AE15 V6 VCC VSS N12 MD34 MD34 CSA2#/RASA2# CS_A2# 12 AC6 AC15 V21 VCC VSS N13 MD35 MD35 CSA3#/RASA3# CS_A3# 12 AF6 AD15 Y6 VCC VSS N14 MD36 MD36 CSA4#/RASA4# CS_A4# 13 AD7 AE16 Y21 VCC VSS N15 MD37 MD37 CSA5#/RASA5# CS_A5# 13 AE7 AA7 VCC VSS N24 MD38 MD38 AC8 AE25 AA9 VCC VSS P12 MD39 MD39 CSB0#/RASB0# AD8 AD24 AA18 VCC VSS P13 MD40 MD40 CSB1#/RASB1# AF8 AD26 AA20 VCC VSS P14 MD41 MD41 CSB2#/RASB2# AE8 AC24 AE1 VCC VSS P15 MD42 MD42 CSB3#/RASB3# VCC VSS MD43 AF9 MD43 CSB4#/RASB4# AC26 AE26 P26 C VCC VSS C MD44 AD10 MD44 CSB5#/RASB5# AB23 AF2 R5 AE10 AF14 VCC VSS R11 MD45 MD45 DQMA[7:0] 11,12,13 VCC VSS MD46 AB11 MD46 R13 AC11 AD13 VSS R14 MD47 MD47 DQMA0/CASA0# DQMA0 VSS MD48 Y23 MD48 DQMA1/CASA1# AC13 DQMA1 R16 Y26 AC25 VSS R22 MD49 MD49 DQMA2/CASA2# DQMA2 VSS MD50 W22 MD50 DQMA3/CASA3# AB26 DQMA3 T12 V22 AE14 VSS T15 MD51 MD51 DQMA4/CASA4# DQMA4 VSS V23 AC14 V3 MD52 MD52 DQMA5/CASA5# DQMA5 VSS V25 AA22 V24 MD53 MD53 DQMA6/CASA6# DQMA6 VSS U22 AA24 W6 MD54 MD54 DQMA7/CASA7# DQMA7 VSS U25 AE13 W21 MD55 MD55 DQMB1/CASB1# DQMB1 13 VSS U26 AD14 AA6 MD56 MD56 DQMB5/CASB5# DQMB5 13 VSS T24 AA8 MD57 MD57 VSS T25 AC22 AA19 MD58 MD58 CKE0/FENA CKE0 11 VSS U21 AF23 AA21 MD59 MD59 CKE1/GCKE CKE1 11 VSS R23 AE24 AB3 MD60 MD60 CKE2/CSA6 CKE2 12 VSS R26 AD23 AB12 MD61 MD61 CKE3/CSA7 CKE3 12 VSS P24 AC23 AB15 MD62 MD62 CKE4/CSB6 CKE4 13 VSS P25 AF24 AB24 MD63 MD63 CKE5/CSB7 CKE5 13 VSS AF12 AB25 11,12,13 MECC[7:0] SCASA# SCASA# 11,12 VSS AE11 AB13 AD5 MECC0 MECC0 SCASB# SCASB# 13 VSS AA10 AF16 AD9 MECC1 MECC1 SRASA# SRASA# 11,12 VSS AA23 AA17 AD18 MECC2 MECC2 SRASB# SRASB# 13 VSS MECC3 AA26 MECC3 WEA# AE12 WE_A# 11,12 VSS AD22 MECC4 AF11 MECC4 WEB# AC12 WE_B# 13 VSS AF1 MECC5 AD12 MECC5 DCLKWR AD25 BxFBCLK 14 VSS AF13 MECC6 AA25 MECC6 DCLK0 AB21 BXDCLKO 14 VSS AF26 MECC7 Y22 MECC7 R344 22

443BX_10 443BX_10

B B

V3_3 V3_3 See Table for Stuffing

R345 10K R346 EMPTY R347 MAB10 10K MAB#12 FREQ_SEL 14 10K Board Default Function Resistor Setting Signal Frequency Select BX Strapping R25 R348 EMPTY Quick Start SelectDo Not Stuff MAB10# MAB#9 Option AGP Disable Do Not Stuff MAB9# R26 10K Memory Module R27 Do Not Stuff MAB7# A Configuration R349 EMPTY A Host Bus Buffer Mode BxFBCLK R28 Stuff MAB6# MAB#7 Select 10K In-Order Queue Depth MAB11# Do Not Stuff >> LAYOUT R29 Enable. R350 MAB#6 Place cap as close Intel Corporation 10K to BX as possible C322 Embedded Intel Architecture Division 20pF 5000 W. Chandler Blvd. R351 EMPTY Chandler, AZ 85226-3699 MAB#11 10K THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT Designed By: Application Design-In Center (Folsom, CA) BEEN VERIFIED FOR MANUFACTURING AS AN END USER Title BX Strapping Options DCLKWR Decoupling Intel® Pentium® III - Low Power / 440BX AGPset Reference Design PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE Size Document Number Rev MISUSE OF THIS INFORMATION. C A0 Date:Monday, August 27, 2001 Sheet 728of 5 4 3 2 1 5 4 3 2 1 ITP, Thermal Sensor, and Clock Throttling

Populate R366 and U28 will mount V3_3 VCCT V3_3 remove R306 if V3_3 Place VDD onto a 28-pin STPCLK controlled bypass as by microcontroller PDIP socket Do Not C323 close to pin and not by PIIX4E. Populate 0.1uF (XU28). as possible. R352 R353 R354 EMPTY 1K EMPTY R359 R360 R361 1K 1K Microcontroller Bypass Cap Routing Guidelines: 1.5K 1.5K 10K V3_3 U28 D Route THERMDP & D C325 1 28 TP TERMDN as a MCLR# RB7 STPCLK_MICRO 15pf 2 27 TP23 RA0 RB6 Make RX and TX through differential pair R369 3 26 1 3 RA1 RB5 270 4 25 TP24 hole so a test post can be RA2 RB4 Q3 CSA4_00MG Do Not 5 24 soldered in. This will

RA3 RB3 TP V3_3 10K R370 R371 Populate 6 23 RA4 RB2 allow the connection of an 10K FDV301N 7 22 RA5 RB1 1 Fairchild: 25V, C326 Y3 8 21 1 external board with a C327 U30 VSS RB0 EMPTY EMPTY ID=250uA@VGS=0.85V typ 15pf 9 20 0.1uF OSC1 VDD MAX232 for connecting to a 2 15 Do Not Populate 10 19 VCC STBY# 1.5V max OSC2 VSS 2 terminal for debug. 4 THERMDP 11 RC0 RC7/RX 18 R372 R373 3 12 12 17 C328 DXP SMBDATA SMBDATA 11,12,13,14,15,20 RC1/CCP2 RC6/TX 1K 1K 4 14 R366 13 16 0.1uF DXN SMBCLK SMBCLK 11,12,13,14,15,20 STPCLK_MICRO RC2/CCP1 RC5 11 270 14 15 4 THERMDN ALERT# 11,12,13,14,15,20 SMBCLK RC3/SCL RC4/SDA SMBDATA 11,12,13,14,15,20 1 2 STPCLK# 4,20 10 1 ADD0 NC1 PIC16LF873 6 ADD1 NC2 5 NC3 9 7 GND NC4 13 Address Select Straps 8 GND NC5 16 Processor Current Address: 1001 STPCLK CMOS VoltageDo Not Level Populate Shifter Clock Throttling Circuit MAX1617 110

THERMAL SENSOR

C C

V3_3 1 1 R374 R375 270 3.3K 2 2 DBRESET 27 3 VCCT VCCT Q4 0.449 FDV301N >>> LAYOUT 1 Fairchild: 0.60 1.5V

25V 0.284 ID=250uA@VGS=0.85V typ connector, AMP 2

1 1 1 1 1.5V max TYP 104078-4 Vertical VCCT VCCT R376 R377 R378 R379 Recepticle, Top View

B 1K 1K 3.3K 1K of ITP connector B 0.100

2 2 2 2 with component J25 R380 keep-out area. PIN 1 240 1 1 1 1 2 2 1 4,6 HRESET# RESET# GND R381 R382 R383 R384 RESET# 4 3 150 150 1.5K 56 R385 DBRESET# GND 1% 47 4 4 H_TCK 1 2 6 5

TCK GND 2 2 2 1 2 8 7 4 H_TMS TMS TDI H_TDI 4 1 R386 10 9 47 POWERON TDO H_TDO 4 2 3 12 11 DBINST# TRST# H_TRST# 4 14 13 GND BSEN# 16 15 GND PREQ0# H_PREQ# 4 18 17 1 2 GND PRDY0# H_PRDY# 4 20 19 240 R387 GND PREQ1# 22 21 GND PRDY1# VCCT 24 23 150 R388 0.794 1.004 GND PREQ2# 0.700 THIS DRAWING CONTAINS 26 25 GND PRDY2# V3_3 INFORMATION WHICH HAS NOT 150 R389 28 GND PREQ3# 27 30 BEEN VERIFIED FOR 30 BCLK PRDY3# 29 MANUFACTURING AS AN END 150 R390 1 1 USER PRODUCT. INTEL IS NOT R391 ITP R392 A 0 1K RESPONSIBLE FOR THE MISUSE A 29

2 2 OF THIS INFORMATION.

Intel Corporation

Embedded Intel Architecture Division ITP/JTAG INTERFACE 5000 W. Chandler Blvd. Chandler, AZ 85226-3699 ITP/JTAG CONNECTOR Designed By: Application Design-In Center (Folsom, CA) OPTIONAL Title Intel® Pentium® III - Low Power / 440BX AGPset Reference Design

Size Document Number Rev C A0

Date:Monday, August 27, 2001 Sheet 8 of 28 5 4 3 2 1 A B C D E Processor Voltage Regulator

VCCCORE

C329 C330 V3_3 0.1uF 0.1uF 25V 25V

4 4

Hi Frequency Decoupling Caps

V5_0

C331 C332 C333 C334 C335 R393 10uF 10uF 10uF 10uF 10uF 10 16V 16V 16V 16V 16V

D9 5 6 7 8 C336 CMDSH-3 U31 0.1uF IRF7811A U32 27 CPUPWROK 3 R394 3 32 30 1M 5 6 R395 Vin EXTVcc U33A 100K FDS6982 4 36 PGOOD STBYMD 6

35 TG1 TG2 24 4 L2 L3 33 BOOST1 BOOST2 26 3 2 1 3 C337 34 25 C338 1uH 5 6 7 8 5 6 7 8 0.47uF SW1 SW2 0.1uF 2.2uH 31 27 BG1 BG2 7 8 U34 U35 R396 U33B D10 D11 10 FDS6982 D12 5 FREQSET PGND 28 MBRS340T3 CMDSH-3 MBRM140T3 4 4 7 FCB SENSE2+ 14 2 R398 10K R397 C339 2 SENSE1+ SENSE2- 13 C340 10K R399 1000pF 1 0.01uF 10 3 SENSE1- EAIN2 12 3 2 1 3 2 1 Do Not Populate 29 INTVcc 3 milliohm IRF7809A R400 IRF7809A 10K 22 VIDVcc VID0 17 VID0 Sense Resistor 1% 15 milliohm R401 C341 8 ITH1 VID1 18 VID1 Sense Resistor 160K 180pF R402 R403 C342 C343 C344 4 EAIN1 VID2 19 VID2 R404 15m 3m 1000pF 4.7uF 1uF 7.5K SENSE VCCT 5% 10V 15 ATTNOUT VID3 20 VID3 1% SENSE VCCCORE C345 16 ATTNIN VID4 21 VID4 Vout1 1000pF R405 VID[4:0] 4 1.35V @ 14A 15K Vout2 C346 C347 ITH2 11 1.5V @ 2.5A < LAYOUT > R406 330pF 100pF < LAYOUT > 2 2 68K 1 RUN/SS1 SGND 9 C348 C349 R407 Tightly couple these 1000pF 33pF 10K Tightly couple these current sensing 10 3.3Vout RUN/SS2 23 1% current sensing C350 C351 C352 C353 C354 C355 C356 C357 R408 180uF 270uF 270uF 270uF 270uF 270uF 270uF 10uF feedback paths 33K feedback paths 4V 2V 2V 2V 2V 2V 2V 6.3V LTC1708-PG CER R409 R410 R411 1M C358 C359 1M 10K Do Not Populate V5_0 0.1uF 0.1uF V5_0 1%

1 1

Intel Corporation

Embedded Intel Architecture Division 5000 W. Chandler Blvd. Chandler, AZ 85226-3699 THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT Designed By: Application Design-In Center (Folsom, CA) BEEN VERIFIED FOR MANUFACTURING AS AN END USER Title Intel® Pentium® III - Low Power / 440BX AGPset Reference Design

PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE Size Document Number Rev MISUSE OF THIS INFORMATION. C A0 Date:Monday, August 27, 2001 Sheet 928of A B C D E A B C D E Mini PCI Connector

4 4

V5_0

V3_3 V3_3

6,16,17,19 AD[31:0] Do Not Populate

J10

1 71 1 71 14 PCICLK4 2 72 -FRAME 6,15,16,17,19 3 2 72 73 3 73 4 74 -PLOCK 6,15,16,17 5 4 74 75 6 5 75 76 7 6 76 77 8 7 77 78 AD0 -DEVSEL 6,15,16,17,19 9 8 78 79 10 9 79 80 11 10 80 81 AD1 12 11 81 82 13 12 82 83 14 13 83 84 AD2 -IRDY 6,15,16,17,19 15 14 84 85 AD3 16 15 85 86 AD4 16 86 -TRDY 6,15,16,17,19 AD5 17 87 18 17 87 88 3 18 88 3 AD6 19 89 20 19 89 90 21 20 90 91 AD7 21 91 AD8 22 92 -STOP 6,15,16,17,19 23 22 92 93 23 93 AD9 24 94 -PCIRST 6,16,17,18,19 25 24 94 95 26 25 95 96 AD10 26 96 PAR 6,15,16,17,19 AD11 27 97 28 27 97 98 AD12 28 98 -SERR 6,15,16,17,19 AD13 29 99 30 29 99 100 30 100 AD14 31 101 32 31 101 102 33 32 102 103 AD15 33 103 AD16 34 104 -PREQ3 6,15,19 35 34 104 105 35 105 AD17 36 106 -PGNT3 6,15 37 36 106 107 38 37 107 108 AD18 38 108 CLKRUN# 6,19 AD19 39 109 40 39 109 110 AD20 40 110 AD21 41 111 42 41 111 112 42 112 AD22 43 113 44 43 113 114 45 44 114 115 AD23 45 115 AD24 46 116 47 46 116 117 V5_0 47 117 AD25 48 118 49 48 118 119 49 119 AD26 50 120 PIRQD# 15,16,17,19,20 51 50 120 121 AD27 51 121 PIRQC# 15,16,17,18,19,20 52 122 52 122 53 123 AD28 53 123 PIRQB# 15,16,17,18,19,20 54 124 54 124 55 125 AD29 55 125 PIRQA# 15,16,17,19,20 56 126 2 AD30 56 126 -PERR 15,16,17 2 57 127 57 127 58 128 -C/BE0 58 128 59 129 59 129 60 130 -C/BE1 60 130 61 131 AD31 61 131 62 132 62 132 63 133 -C/BE2 63 133 AD31 64 134 64 134 65 135 R70 -C/BE3 65 135 66 136 66 136 220 67 67 137 137 68 68 138 138 IDSELF 69 139 V5_0 69 139 70 70 140 140 6,16,17,19 -C/BE[3:0] 2X70RCPT

1 1

Intel Corporation

Embedded Intel Architecture Division 5000 W. Chandler Blvd. Chandler, AZ 85226-3699 THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT Designed By: Application Design-In Center (Folsom, CA) BEEN VERIFIED FOR MANUFACTURING AS AN END USER Title Intel® Pentium® III - Low Power / 440BX AGPset Reference Design

PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE Size Document Number Rev MISUSE OF THIS INFORMATION. C A0 Date:Monday, August 27, 2001 Sheet 10of 28 A B C D E A B C D E DIMM0 V3_3

C105 C155 C226 C199 C175 C228 C202 C201 C207 C204 47uF 47uF 0.1uF 0.1uF 0.1uF 0.1uF 0.01uF 0.01uF 0.01uF 0.01uF

4 4

Socket 0

7,12,13 MECC[7:0]

7,12 MAA[13:0]

7,12,13 MD[63:0]

J18 A1 B85 A2 GND GND B86 MD0 MD32 A3 DQ0 DQ32 B87 MD1 MD33 A4 DQ1 DQ33 B88 MD2 MD34 A5 DQ2 DQ34 B89 MD3 MD35 A6 DQ3 DQ35 B90 A7 V3_3 V3_3 B91 MD4 MD36 A8 DQ4 DQ36 B92 MD5 MD37 A9 DQ5 DQ37 B93 MD6 MD38 A10 DQ6 DQ38 B94 MD7 DQ7 DQ39 MD39

A11 B95 MD8 DQ40 MD40 A12 DQ8 B96 GND A13 GND B97 MD9 DQ41 MD41 A14 DQ9 B98 MD10 DQ42 MD42 3 A15 DQ10 B99 3 MD11 DQ43 MD43 A16 DQ11 B100 MD12 DQ44 MD44 A17 DQ12 B101 MD13 DQ45 MD45 A18 DQ13 B102 V3_3 A19 V3_3 B103 MD14 DQ46 MD46 A20 DQ14 B104 MD15 DQ47 MD47 A21 DQ15 B105 MECC0 CB4 MECC4 A22 CB0 B106 MECC1 CB5 MECC5 A23 CB1 B107 GND A24 GND B108 NC A25 NC B109 NC NC A26 V3_3 B110 A27 V3_3 B111 7,12 WE_A# WE0 /CAS SCASA# 7,12 7,12,13 DQMA0 A28 DQMB0 DQMB4 B112 DQMA4 7,12,13 7,12 DQMA1 A29 DQMB1 DQMB5 B113 DQMA5 7,12 7 CS_A0# A30 /S0 /S1 B114 CS_A1# 7 A31 DU /RAS B115 SRASA# 7,12 A32 GND GND B116 MAA0 A33 A0 A1 B117 MAA1 MAA2 A34 A2 A3 B118 MAA3 MAA4 A35 A4 A5 B119 MAA5 MAA6 A36 A6 A7 B120 MAA7 MAA8 A37 A8 A9 B121 MAA9 MAA10 A38 A10(AP) BA0 B122 MAA11 MAA12 A39 BA1 A11 B123 MAA13 A40 V3_3 V3_3 B124

A41 B125 V3_3 CK1 SDCLK1 14 A42 B126 14 SDCLK0 CK0 A12 MAA12 A43 B127 GND GND A44 B128 DU CKE0 CKE0 7 A45 B129 /S2 /S3 A46 B130 7,12,13 DQMA2 DQMB2 DQMB6 DQMA6 7,12,13 A47 B131 7,12,13 DQMA3 DQBM3 DQMB7 DQMA7 7,12,13 A48 B132 DU A13 A49 B133 V3_3 V3_3 A50 B134 2 NC NC 2 A51 B135 NC NC MECC2 A52 CB6 B136 MECC6 R48 CB2 V3_3 MECC3 A53 CB3 CB7 B137 MECC7 0 A54 GND GND B138 MD16 A55 DQ48 B139 MD48 DQ16 R52 MD17 A56 DQ17 DQ49 B140 MD49 MD18 A57 DQ18 DQ50 B141 MD50 0 MD19 A58 DQ19 DQ51 B142 MD51 A59 V3_3 V3_3 B143 MD20 A60 DQ20 DQ52 B144 MD52 A61 NC NC B145 A62 VREF (NC) DU B146 7 CKE1 A63 CKE1 REGE B147 A64 GND GND B148 MD21 A65 DQ21 DQ53 B149 MD53 MD22 A66 DQ22 DQ54 B150 MD54 MD23 A67 DQ23 DQ55 B151 MD55 A68 GND GND B152 MD24 A69 DQ24 DQ56 B153 MD56 MD25 A70 DQ25 DQ57 B154 MD57 MD26 A71 DQ26 DQ58 B155 MD58 MD27 A72 DQ27 DQ59 B156 MD59 A73 V3_3 V3_3 B157 MD28 A74 DQ28 DQ60 B158 MD60 MD29 A75 DQ29 DQ61 B159 MD61 MD30 A76 DQ30 DQ62 B160 MD62 MD31 A77 DQ31 DQ63 B161 MD63 A78 GND GND B162 14 SDCLK2 A79 CK2 CK3 B163 SDCLK3 14 A80 NC NC B164 A81 WP SA0 B165 8,12,13,14,15,20 SMBDATA A82 SDA SA1 B166 8,12,13,14,15,20 SMBCLK A83 SCL SA2 B167 A84 V3_3 V3_3 B168 SDRAM DIMM Slave address 10100000b

1 1

Intel Corporation

Embedded Intel Architecture Division 5000 W. Chandler Blvd. Chandler, AZ 85226-3699 THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT Designed By: Application Design-In Center (Folsom, CA) Title BEEN VERIFIED FOR MANUFACTURING AS AN END USER Intel® Pentium® III - Low Power / 440BX AGPset Reference Design Size Document Number Rev PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE C A0

MISUSE OF THIS INFORMATION. Date:Monday, August 27, 2001 Sheet 11of 28 A B C D E A B C D E DIMM1 V3_3

C104 C103 C182 C181 C183 C198 47uF 47uF 0.1uF 0.1uF 0.1uF 0.1uF

4 4

Socket 1

7,11,13 MECC[7:0]

7,11 MAA[13:0]

7,11,13 MD[63:0]

J17 A1 B85 A2 GND GND B86 MD0 MD32 A3 DQ0 DQ32 B87 MD1 MD33 A4 DQ1 DQ33 B88 MD2 MD34 A5 DQ2 DQ34 B89 MD3 MD35 A6 DQ3 DQ35 B90 A7 V3_3 V3_3 B91 MD4 MD36 A8 DQ4 DQ36 B92 MD5 MD37 A9 DQ5 DQ37 B93 MD6 MD38 A10 DQ6 DQ38 B94 MD7 DQ7 DQ39 MD39

A11 B95 MD8 DQ40 MD40 A12 DQ8 B96 GND 3 A13 GND B97 3 MD9 DQ41 MD41 A14 DQ9 B98 MD10 DQ42 MD42 A15 DQ10 B99 MD11 DQ43 MD43 A16 DQ11 B100 MD12 DQ44 MD44 A17 DQ12 B101 MD13 DQ45 MD45 A18 DQ13 B102 V3_3 A19 V3_3 B103 MD14 DQ46 MD46 A20 DQ14 B104 MD15 DQ47 MD47 A21 DQ15 B105 MECC0 CB4 MECC4 A22 CB0 B106 MECC1 CB5 MECC5 A23 CB1 B107 GND A24 GND B108 NC A25 NC B109 NC NC A26 V3_3 B110 A27 V3_3 B111 7,11 WE_A# WE0 /CAS SCASA# 7,11 7,11,13 DQMA0 A28 DQMB0 DQMB4 B112 DQMA4 7,11,13 7,11 DQMA1 A29 DQMB1 DQMB5 B113 DQMA5 7,11 7 CS_A2# A30 /S0 /S1 B114 CS_A3# 7 A31 DU /RAS B115 SRASA# 7,11 A32 GND GND B116 MAA0 A33 A0 A1 B117 MAA1 MAA2 A34 A2 A3 B118 MAA3 MAA4 A35 A4 A5 B119 MAA5 MAA6 A36 A6 A7 B120 MAA7 MAA8 A37 A8 A9 B121 MAA9 MAA10 A38 A10(AP) BA0 B122 MAA11 MAA12 A39 BA1 A11 B123 MAA13 A40 V3_3 V3_3 B124

A41 B125 V3_3 CK1 SDCLK5 14 A42 B126 14 SDCLK4 CK0 A12 MAA12 A43 B127 GND GND A44 B128 DU CKE0 CKE2 7 A45 B129 /S2 /S3 A46 B130 7,11,13 DQMA2 DQMB2 DQMB6 DQMA6 7,11,13 A47 B131 7,11,13 DQMA3 DQBM3 DQMB7 DQMA7 7,11,13 A48 B132 2 DU A13 2 A49 B133 V3_3 V3_3 A50 B134 NC NC A51 B135 NC NC MECC2 A52 CB6 B136 MECC6 R99 CB2 V3_3 MECC3 A53 CB3 CB7 B137 MECC7 0 A54 GND GND B138 MD16 A55 DQ48 B139 MD48 DQ16 R108 MD17 A56 DQ17 DQ49 B140 MD49 MD18 A57 DQ18 DQ50 B141 MD50 0 MD19 A58 DQ19 DQ51 B142 MD51 A59 V3_3 V3_3 B143 MD20 A60 DQ20 DQ52 B144 MD52 A61 NC NC B145 A62 VREF (NC) DU B146 7 CKE3 A63 CKE1 REGE B147 A64 GND GND B148 MD21 A65 DQ21 DQ53 B149 MD53 MD22 A66 DQ22 DQ54 B150 MD54 MD23 A67 DQ23 DQ55 B151 MD55 V3_3 A68 GND GND B152 MD24 A69 DQ24 DQ56 B153 MD56 MD25 A70 DQ25 DQ57 B154 MD57 R125 MD26 A71 DQ26 DQ58 B155 MD58 MD27 A72 DQ27 DQ59 B156 MD59 4.7K A73 V3_3 V3_3 B157 MD28 A74 DQ28 DQ60 B158 MD60 MD29 A75 DQ29 DQ61 B159 MD61 MD30 A76 DQ30 DQ62 B160 MD62 MD31 A77 DQ31 DQ63 B161 MD63 A78 GND GND B162 14 SDCLK6 A79 CK2 CK3 B163 SDCLK7 14 A80 NC NC B164 A81 WP SA0 B165 8,11,13,14,15,20 SMBDATA A82 SDA SA1 B166 8,11,13,14,15,20 SMBCLK A83 SCL SA2 B167 A84 V3_3 V3_3 B168 Slave address 10100001b 1 SDRAM DIMM 1

Intel Corporation

Embedded Intel Architecture Division 5000 W. Chandler Blvd. Chandler, AZ 85226-3699 THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT Designed By: Application Design-In Center (Folsom, CA) Title BEEN VERIFIED FOR MANUFACTURING AS AN END USER Intel® Pentium® III - Low Power / 440BX AGPset Reference Design Size Document Number Rev PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE C A0

MISUSE OF THIS INFORMATION. Date:Monday, August 27, 2001 Sheet 12of 28 A B C D E A B C D E

DIMM2 V3_3

C156 C128 C197 C227 C174 C176 47uf 47uF 0.1uF 0.1uF 0.1uF 0.1uF

4 4 Socket 2

7,11,12 MECC[7:0]

7 MAB#[13:0]

7,11,12 MD[63:0]

J16 A1 B85 A2 GND GND B86 MD0 MD32 A3 DQ0 DQ32 B87 MD1 MD33 A4 DQ1 DQ33 B88 MD2 MD34 A5 DQ2 DQ34 B89 MD3 MD35 A6 DQ3 DQ35 B90 A7 V3_3 V3_3 B91 MD4 MD36 A8 DQ4 DQ36 B92 MD5 MD37 A9 DQ5 DQ37 B93 MD6 MD38 A10 DQ6 DQ38 B94 Note: J16 is not populated MD7 DQ7 DQ39 MD39

A11 B95 MD8 DQ40 MD40 A12 DQ8 B96 GND A13 GND B97 MD9 DQ41 MD41 A14 DQ9 B98 MD10 DQ42 MD42 A15 DQ10 B99 MD11 DQ43 MD43 A16 DQ11 B100 MD12 DQ44 MD44 A17 DQ12 B101 MD13 DQ45 MD45 3 A18 DQ13 B102 3 V3_3 A19 V3_3 B103 MD14 DQ46 MD46 A20 DQ14 B104 MD15 DQ47 MD47 A21 DQ15 B105 MECC0 CB4 MECC4 A22 CB0 B106 MECC1 CB5 MECC5 A23 CB1 B107 GND A24 GND B108 NC A25 NC B109 NC NC A26 V3_3 B110 A27 V3_3 B111 7 WE_B# WE0 /CAS SCASB# 7 7,11,12 DQMA0 A28 DQMB0 DQMB4 B112 DQMA4 7,11,12 7 DQMB1 A29 DQMB1 DQMB5 B113 DQMB5 7 7 CS_A4# A30 /S0 /S1 B114 CS_A5# 7 A31 DU /RAS B115 SRASB# 7 A32 GND GND B116 MAB#0 A33 A0 A1 B117 MAB#1 MAB#2 A34 A2 A3 B118 MAB#3 MAB#4 A35 A4 A5 B119 MAB#5 MAB#6 A36 A6 A7 B120 MAB#7 MAB#8 A37 A8 A9 B121 MAB#9 MAB#10 A38 A10(AP) BA0 B122 MAB#11 MAB#12 A39 BA1 A11 B123 MAB#13 A40 V3_3 V3_3 B124

A41 B125 V3_3 CK1 SDCLK9 14 A42 B126 14 SDCLK8 CK0 A12 MAB#12 A43 B127 GND GND A44 B128 DU CKE0 CKE4 7 A45 B129 /S2 /S3 A46 B130 7,11,12 DQMA2 DQMB2 DQMB6 DQMA6 7,11,12 A47 B131 7,11,12 DQMA3 DQBM3 DQMB7 DQMA7 7,11,12 A48 B132 DU A13 A49 B133 V3_3 V3_3 A50 B134 NC NC A51 B135 NC NC MECC2 A52 CB2 CB6 B136 MECC6 A53 B137 R100 V3_3 2 MECC3 CB3 CB7 MECC7 2 A54 GND GND B138 0 MD16 A55 DQ48 B139 MD48 DQ16 R106 MD17 A56 DQ17 DQ49 B140 MD49 MD18 A57 DQ18 DQ50 B141 MD50 0 MD19 A58 DQ19 DQ51 B142 MD51 A59 V3_3 V3_3 B143 MD20 A60 DQ20 DQ52 B144 MD52 A61 NC NC B145 A62 VREF (NC) DU B146 7 CKE5 A63 CKE1 REGE B147 A64 GND GND B148 MD21 A65 DQ21 DQ53 B149 MD53 MD22 A66 DQ22 DQ54 B150 MD54 MD23 A67 DQ23 DQ55 B151 MD55 V3_3 A68 GND GND B152 MD24 A69 DQ24 DQ56 B153 MD56 MD25 A70 DQ25 DQ57 B154 MD57 R126 MD26 A71 DQ26 DQ58 B155 MD58 MD27 A72 DQ27 DQ59 B156 MD59 4.7K A73 V3_3 V3_3 B157 MD28 A74 DQ28 DQ60 B158 MD60 MD29 A75 DQ29 DQ61 B159 MD61 MD30 A76 DQ30 DQ62 B160 MD62 MD31 A77 DQ31 DQ63 B161 MD63 A78 GND GND B162 14 SDCLK10 A79 CK2 CK3 B163 SDCLK11 14 A80 NC NC B164 A81 WP SA0 B165 8,11,12,14,15,20 SMBDATA A82 SDA SA1 B166 8,11,12,14,15,20 SMBCLK A83 SCL SA2 B167 A84 V3_3 V3_3 B168 SDRAM DIMM Slave address 10100010b

1 1

Intel Corporation

Embedded Intel Architecture Division 5000 W. Chandler Blvd. Chandler, AZ 85226-3699 THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT Designed By: Application Design-In Center (Folsom, CA) BEEN VERIFIED FOR MANUFACTURING AS AN END USER Title Intel® Pentium® III - Low Power / 440BX AGPset Reference Design

PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE Size Document Number Rev MISUSE OF THIS INFORMATION. C A0 Date:Monday, August 27, 2001 Sheet 13 of 28 A B C D E A B C D E System Clocks TP17

V2_5 TP V3_3

1 V5_0

U5

2 Out In 3 V2_5 4 R15 OutTab 124 C162 C95 1% 0.1uF C94 C93 C165 C173 C169 C101 C171 C170 C168 C164 C163 100uF 10uF 4 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 4 47uF 0.01uF 1 Adj/GND

R16 LT117 1%124 V3_3 Note: R15 and R16 should be placed as close as possible to U5 8 7 6 5 8 7 6 5 RP20 RP22 10K 10K 1 2 3 4 1 2 3 4 Note: Stuff only to enable U6 15 9 21 48 19 33 37 41 46 stopping of clocks 40 R24 22 CPUCLK0 CPUCLKR_01 CPUCLK0 4,6 AVDD AVDD CPUCLK1 39

VDDPCI VDDPCI 36 VDDREF VDDUSB VDDCPU VDDCPU

VDDAPIC CPUCLK2 35 R35 0 CPUCLK3 20 CPU_STOP# 30 CPU_STOP# R33 0 31 7 R23 33 20 PCI_STOP# PCI_STOP# PCICLK_F PCICLKF_R PCICLKF 20 R37 0 29 8 R26 33 20 SUSA# PWR_DWN# PCI_CLK1 PCICLKR_1 PCICLK1 16 10 R28 33 PCI_CLK2 PCICLKR_2 PCICLK2 16 11 R30 33 PCI_CLK3 PCICLKR_3 PCICLK3 17 27 13 R32 33 SEL0 PCI_CLK4 PCICLKR_4 PCICLK4 10 26 SEL1 PCI_CLK5 14 R34 33 7 FREQ_SEL 25 SEL100 PCI_CLK6 16 PCICLKR_6 PCLKAPIC 19 3 28 17 R36 33 3 1 1 SEL_SS# CY2280 PCI_CLK7 PCICLKR_7 PCICLK7 6 J15 J14 22 R38 33 JUMP2 HDR2 USBCLK0 USBCLKR_0 USBCLK0 20 42 RESERVED USBCLK1 23

2 2 R18 33 1 REF0 24 REF0 REFR_0 R21 33 2 REFR_1 REF1 22 REF1 R17 33 4 XTALIN REF2 47 REFR_2 REF2 20 5 XTALOUT R19 33 APIC0 45 APICCLKR_0 APICCLK0 19 APIC1 44

Y1 VSS VSS VSS VSS VSS VSS VSS VSS VSS Note: Keep crystal close to clock and 1 2 VSS caps close to crystal. All lead 14.318MHz 3 6 12 18 20 24 32 34 38 43 lengths should be equal.

C99 C100 10pf 10pf

V3_3

2 C213 C217 C223 C221 C212 C225 C220 C224 C222 C216 C211 C150 C149 C148 2 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 15uF 15uF 15uF

U16 3 7 12 16 20 23 29 33 37 42 46 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD R110 0 4 SDCLKR0 SDCLK0 11 SDRAM0 R112 0 5 SDCLKR1 SDCLK1 11 SDRAM1 R114 0 8 SDCLKR2 SDCLK2 11 R308 33 SDRAM2 R116 0 11 9 SDCLKR3 SDCLK3 11 7 BXDCLKO CLK_IN SDRAM3 R119 0 13 SDCLKR8 SDCLK8 13 SDRAM4 R121 0 38 OE SDRAM5 14 SDCLKR9 SDCLK9 13 SDRAM6 17 SDRAM7 18 CY2318NZ SDRAM8 31 32 SDRAM9 R120 0 1 NC 35 SDCLKR10 SDCLK10 13 SDRAM10 R118 0 2 NC 36 SDCLKR11 SDCLK11 13 SDRAM11 R115 0 47 NC 40 SDCLKR7 SDCLK7 12 SDRAM12 R113 0 48 NC 41 SDCLKR6 SDCLK6 12 SDRAM13 R111 0 44 SDCLKR4 SDCLK4 12 SDRAM14 R109 0 45 SDCLKR5 SDCLK5 12 SDRAM15 R122 0 SDRAM16 21 BxFBCLK 7 SDRAM17 28

8,11,12,13,15,20 SMBDATA 24 SDATA 8,11,12,13,15,20 SMBCLK 25 SCLK

1 1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 6 10 15 19 22 26 27 30 34 39 43

Intel Corporation

Embedded Intel Architecture Division 5000 W. Chandler Blvd. Chandler, AZ 85226-3699 THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT Designed By: Application Design-In Center (Folsom, CA) BEEN VERIFIED FOR MANUFACTURING AS AN END USER Title Intel® Pentium® III - Low Power / 440BX AGPset Reference Design

PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE Size Document Number Rev MISUSE OF THIS INFORMATION. C A0 Date:Monday, August 27, 2001 Sheet 14of 28 A B C D E A B C D E PCI / ISA Pullups

V5_0 M1 ISA Pullups TP 1 PCI Pullups V5_0 M2 19,22,24,26 SD[15:0] TP 1 RP9 1 8 RP50 SD0 2 7 1 8 SD1 10,16,17 -PERR M3 3 6 6,10,16,17,19 -SERR 2 7 SD2 4 5 3 6 1 4 SD3 6,10,16,17,19 PAR TP 4 6,10,16,17,19 -FRAME 4 5 10K RP8 2.7K 1 8 RP53 SD4 2 7 1 8 SD5 6,10,16,17,19 -IRDY M4 3 6 6,10,16,17,19 -TRDY 2 7 SD6 4 5 3 6 1 SD7 6,10,16,17,19 -DEVSEL TP 6,10,16,17,19 -STOP 4 5 10K RP33 2.7K M5 1 8 SD8 2 7 TP 1 SD9 3 6 RP49 SD10 4 5 1 8 SD11 10,16,17,19,20 PIRQA# 10,16,17,18,19,20 PIRQB# 2 7 10K 10,16,17,18,19,20 PIRQC# 3 6 M6 RP35 10,16,17,19,20 PIRQD# 4 5 1 8 TP 1 SD12 2 7 2.7K SD13 3 6 SD14 4 5 M7 SD15 RP52 10K 6,16,19 -PREQ0 1 8 TP 1 6,16,19 -PREQ1 2 7 6,17,19 -PREQ2 3 6 6,10,19 -PREQ3 4 5 M8 10K TP 1 RP25 16,17 SDONE 1 8 16,17 -SBO 2 7 M9 16,17 REQ64# 3 6 16,17 ACK64# 4 5 TP 1 RP19 2.7K 19,22,24,26 SA[19:0] SA0 1 8 M10 3 2 7 3 SA1 R71 2.7K 3 6 6,10,16,17 -PLOCK 1 SA2 R44 2.7K TP SA3 4 5 6 -PREQ4 10K M11 RP17 SA4 1 8 TP 1 2 7 SA5 V3_3 SA6 3 6 SA7 4 5 10K R41 10K 6,19 -PHOLD RP15 R40 10K 6,19 -PHOLDA SA8 1 8 SA9 2 7 SA10 3 6 R43 10K SA11 4 5 6 -PGNT4 10K RP51 RP13 6,10 -PGNT3 1 8 SA12 1 8 6,16 -PGNT0 2 7 SA13 2 7 6,16 -PGNT1 3 6 SA14 3 6 6,17 -PGNT2 4 5 SA15 4 5 10K 10K RP11 V2_5 SA16 1 8 SA17 2 7 SA18 3 6 R47 124 SA19 4 5 19 APICD0 10K R46 124 19 APICD1 RP27 LA17 1 8 R49 1K LA18 2 7 20 CPURST LA19 3 6 2 LA20 4 5 2 10K RP24 VCCT LA21 1 8 RP29 RP38 LA22 2 7 19,24,26 MEMW# 1 8 LA23 3 6 19,22,24,26 IOW# 2 7 4,20 A20M# 1 8 19,24 LA[23:17] 4 5 19,24,26 MEMR# 3 6 4,20 INIT 2 7 19,22,24 IOR# 4 5 4,20 SLP# 3 6 10K 4,20 IGNNE# 4 5 10K RP10 280 1 8 Note IRQ8 Pull-up 19,24 REFRESH# RP40 24 MASTER16# 2 7 is on PIIX4 page RP16 19,22,24 IOCHRDY 3 6 4,20 NMI 1 8 19,20,22 IRQ1 1 8 19,24 ZEROWS# 4 5 4,19,20 INTR 2 7 19,20,22,24 IRQ3 2 7 19,20 PX4_SMI# 3 6 1K 19,20,22,24 IRQ4 3 6 20 STPCLK_P# 4 5 19,20,22,24 IRQ5 4 5 10K RP23 280 RP14 19,24 IOCS16# 1 8 1 8 2 7 19,20,22,24 IRQ6 19,24 MEMCS16# V3_3 19,20,22,24 IRQ7 2 7 19,24 IOCHK# 3 6 3 6 4 5 19,20,24 IRQ9 RP37 19,20,22,24 IRQ10 4 5 1K 1 8 10K 19,20 APICCS# 2 7 RP26 RP21 8,11,12,13,14,20 SMBDATA 3 6 19,20,24 IRQ11 1 8 19,24 SMEMW# 1 8 8,11,12,13,14,20 SMBCLK 4 5 19,20,22,24 IRQ12 2 7 19,24 SMEMR# 2 7 19,20,21,22,24 IRQ14 3 6 19,24 SBHE# 3 6 2.7K 19,20,21,22,24 IRQ15 4 5 19,24 BALE 4 5 10K 10K RP12 20,22,24 DRQ0 1 8 20,22,24 DRQ1 2 7 1 1 20,22,24 DRQ2 3 6 20,22,24 DRQ3 4 5 5.6K RP34 Intel Corporation 20,24 DRQ5 1 8 20,24 DRQ6 2 7 Embedded Intel Architecture Division 20,24 DRQ7 3 6 4 5 5000 W. Chandler Blvd. Chandler, AZ 85226-3699 5.6K THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT Designed By: Application Design-In Center (Folsom, CA) BEEN VERIFIED FOR MANUFACTURING AS AN END USER Title Intel® Pentium® III - Low Power / 440BX AGPset Reference Design

PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE Size Document Number Rev MISUSE OF THIS INFORMATION. C A0 Date:Monday, August 27, 2001 Sheet 15of 28 A B C D E A B C D E PCI Connectors 0 and 1 V5_0 V3_3 V5_0 V3_3

C55 C116 C85 C73 C113 C66 C119 C106 C90 C56 C117 C114 C86 C74 C67 C120 C91 C107 10uF 0.1uF 0.1uF 0.1uF 0.01uF 0.01uF 10uF 0.1uF 0.1uF 10uF 0.1uF 0.1uF 0.1uF 0.01uF 0.01uF 10uF 0.1uF 0.1uF

4 4

AD[31:0] 6,10,17,19 AD[31:0]

6,10,17,19 -C/BE[3:0] -C/BE[3:0]

J7 J8 B1 A1 B1 A1 -12V PCI_TRST 17 -12V PCI_TRST B2 TRST A2 B2 TRST A2 17 PCI_TCLK TCK +12V PCI_TCLK TCK +12V B3 A3 B3 A3 GND TMS PCI_TMS 17 GND TMS PCI_TMS B4 A4 B4 A4 TDO TDI PCI_TDI 17 TDO TDI PCI_TDI B5 V5_0 V5_0 A5 B5 V5_0 V5_0 A5 B6 A6 B6 A6 V5_0 INTA PIRQA# 10,15,17,19,20 V5_0 INTA PIRQD# B7 A7 B7 A7 10,15,17,18,19,20 PIRQB# INTB INTC PIRQC# 10,15,17,18,19,20 PIRQA# INTB INTC PIRQB# 10,15,17,19,20 PIRQD# B8 INTD A8 PIRQC# B8 INTD A8 3 V5_0 V5_0 3 B9 NC A9 B9 NC A9 B10 PRSNT1 A10 B10 PRSNT1 A10 NC V5_0 NC V5_0 B11 A11 B11 A11 PRSNT2 NC PRSNT2 NC C77 B12 A12 C78 C81 B12 A12 GND GND GND GND 0.01uF B13 A13 0.01uF 0.01uF B13 A13 GND GND GND GND C80 B14 A14 B14 A14 NC NC NC NC 0.01uF B15 A15 B15 A15 GND RST -PCIRST 6,10,17,18,19 GND RST -PCIRST B16 A16 B16 A16 CLK V5_0 14 PCICLK2 CLK V5_0 B17 A17 B17 A17 14 PCICLK1 PCICLK1 GND GNT -PGNT0 6,15 GND GNT -PGNT1 6,15 B18 A18 B18 A18 6,15,19 -PREQ0 REQ GND 6,15,19 -PREQ1 REQ GND B19 A19 B19 A19 V5_0 NC V5_0 NC AD31 B20 AD[31] AD[30] A20 AD30 AD28 AD31 B20 AD[31] AD[30] A20 AD30 AD29 AD29 B21 AD[29] V3_3 A21 AD29 B21 AD[29] V3_3 A21 B22 A22 AD28 B22 A22 AD28 GND AD[28] R12 GND AD[28] R13 AD27 B23 AD[27] AD[26] A23 AD26 AD27 B23 AD[27] AD[26] A23 AD26 AD25 B24 AD[25] GND A24 220 AD25 B24 AD[25] GND A24 220 -C/BE3 B25 V3_3 AD[24] A25 AD24 -C/BE3 B25 V3_3 AD[24] A25 AD24 B26 C/BE3 IDSEL A26 PCIA2 B26 C/BE3 IDSEL A26 PCIB2 B27 A27 B27 A27 AD23 AD[23] V3_3 AD23 AD[23] V3_3 B28 A28 B28 A28 GND AD[22] AD22 GND AD[22] AD22 AD21 B29 AD[21] AD[20] A29 AD20 AD21 B29 AD[21] AD[20] A29 AD20 AD19 B30 AD[19] GND A30 AD19 B30 AD[19] GND A30 B31 V3_3 AD[18] A31 AD18 B31 V3_3 AD[18] A31 AD18 AD17 B32 AD[17] AD[16] A32 AD16 AD17 B32 AD[17] AD[16] A32 AD16 -C/BE2 B33 C/BE2 V3_3 A33 -C/BE2 B33 C/BE2 V3_3 A33 B34 FRAME A34 -FRAME 6,10,15,17,19 B34 FRAME A34 -FRAME B35 GND A35 B35 GND A35 6,10,15,17,19 -IRDY GND -IRDY GND B36 IRDY A36 B36 IRDY A36 V3_3 TRDY -TRDY 6,10,15,17,19 V3_3 TRDY -TRDY 6,10,15,17,19 -DEVSEL B37 DEVSEL GND A37 -DEVSEL B37 DEVSEL GND A37 B38 GND STOP A38 -STOP 6,10,15,17,19 B38 GND STOP A38 -STOP 6,10,15,17 -PLOCK B39 LOCK V3_3 A39 -PLOCK B39 LOCK V3_3 A39 10,15,17 -PERR B40 PERR SDONE A40 SDONE 15,17 -PERR B40 PERR SDONE A40 SDONE 6,10,15,17,19 -SERR B41 V3_3 SBO A41 -SBO 15,17 -SERR B41 V3_3 SBO A41 -SBO B42 SERR GND A42 PAR 6,10,15,17,19 B42 SERR GND A42 PAR -C/BE1 B43 V3_3 PAR A43 -C/BE1 B43 V3_3 PAR A43 B44 C/BE1 AD[15] A44 AD15 B44 C/BE1 AD[15] A44 AD15 AD14 B45 AD[14] V3_3 A45 AD14 B45 AD[14] V3_3 A45 B46 A46 B46 A46 2 GND AD[13] AD13 GND AD[13] AD13 2 AD12 B47 AD[12] AD[11] A47 AD11 AD12 B47 AD[12] AD[11] A47 AD11 AD10 B48 AD[10] GND A48 AD10 B48 AD[10] GND A48 B49 GND AD[09] A49 AD9 B49 GND AD[09] A49 AD9

AD8 B52 AD[08] C/BE0 A52 AD8 B52 AD[08] C/BE0 A52 AD7 B53 AD[07] V3_3 A53 AD7 B53 AD[07] V3_3 A53 B54 V3_3 AD[06] A54 AD6 B54 V3_3 AD[06] A54 AD6 AD5 B55 AD[05] AD[04] A55 AD4 AD5 B55 AD[05] AD[04] A55 AD4 AD3 B56 AD[03] GND A56 AD3 B56 AD[03] GND A56 B57 GND AD[02] A57 AD2 B57 GND AD[02] A57 AD2 AD1 B58 AD[01] AD[00] A58 AD0 AD1 B58 AD[01] AD[00] A58 AD0 B59 V5_0 V5_0 A59 B59 V5_0 V5_0 A59 15,17 ACK64# B60 ACK64 REQ64 A60 REQ64# 15,17 ACK64# B60 ACK64 REQ64 A60 REQ64# B61 V5_0 V5_0 A61 B61 V5_0 V5_0 A61 B62 V5_0 V5_0 A62 B62 V5_0 V5_0 A62

PCI Conn PCI Conn -C/BE0 -C/BE0 PCI SLOT 1 PCI SLOT 0 J7/J8 V5_0: A5, A8, A10, A16, A59, A61, A62 | A1, A3, A4 B5, B6, B19, B22, B59, B61, B62

J7/J8 V3_3: A21, A27, A33, A39 A45, A53 B25, B31, B36, B41, B43, B54

J7/J8 NC: 1 A9, A11, A14, A19 1 B10, B14

J7/J8 GND: Intel Corporation A12, A13, A18, A24, A30, A35, A37, A42, A48, A56 Embedded Intel Architecture Division B3, B12, B13, B15, B17, B28, B34, B38, B46, B49, 5000 W. Chandler Blvd. B57 Chandler, AZ 85226-3699 THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT Designed By: Application Design-In Center (Folsom, CA) BEEN VERIFIED FOR MANUFACTURING AS AN END USER Title J7/J8 +12V: A2 Intel® Pentium® III - Low Power / 440BX AGPset Reference Design -12V: B1 PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE Size Document Number Rev MISUSE OF THIS INFORMATION. C A0 Date:Monday, August 27, 2001 Sheet 16of 28 A B C D E A B C D E PCI Connector 2 V5_0 V3_3

C57 C87 C75 C118 C68 C115 C121 C108 C92 10uF 0.1uF 0.1uF 0.1uF 0.01uF 0.01uF 10uF 0.1uF 0.1uF

4 4

AD[31:0] 6,10,16,19 AD[31:0]

6,10,16,19 -C/BE[3:0] -C/BE[3:0]

J9 B1 A1 -12V PCI_TRST 16 B2 TRST A2 16 PCI_TCLK TCK +12V B3 A3 GND TMS PCI_TMS 16 B4 A4 TDO TDI PCI_TDI 16 B5 V5_0 V5_0 A5 B6 V5_0 INTA A6 PIRQC# 10,15,16,18,19,20 10,15,16,19,20 PIRQD# B7 INTB A7 PIRQA# 10,15,16,19,20 3 B8 INTC A8 3 10,15,16,18,19,20 PIRQB# INTD V5_0 B9 NC A9 B10 PRSNT1 A10 V5_0 NC V5_0 B11 A11 PRSNT2 NC B12 A12 GND GND C79 C82 B13 A13 GND GND 0.01uF 0.01uF B14 A14 NC NC B15 A15 GND RST -PCIRST 6,10,16,18,19 B16 A16 14 PCICLK3 CLK V5_0 B17 A17 R69 R68 R67 GND GNT -PGNT2 6,15 B18 A18 6,15,19 -PREQ2 REQ GND 4.7K 4.7K 4.7K B19 A19 V5_0 NC AD31 B20 AD[31] AD[30] A20 AD30 AD30 PCI_TDI PCI_TMS PCI_TCLK AD29 B21 AD[29] V3_3 A21 B22 A22 AD28 GND AD[28] R14 AD27 B23 AD[27] AD[26] A23 AD26 AD25 B24 AD[25] GND A24 220 PCI_TRST -C/BE3 B25 A25 AD24 V3_3 AD[24] R66 B26 C/BE3 IDSEL A26 PCIC2 AD23 B27 V3_3 A27 4.7K B28 AD[23] A28 GND AD[22] AD22 AD21 B29 AD[21] AD[20] A29 AD20 AD19 B30 AD[19] GND A30 B31 V3_3 AD[18] A31 AD18 AD17 B32 AD[17] AD[16] A32 AD16 -C/BE2 B33 C/BE2 V3_3 A33 B34 FRAME A34 -FRAME 6,10,15,16,19 B35 GND A35 6,10,15,16,19 -IRDY GND B36 IRDY A36 V3_3 TRDY -TRDY 6,10,15,16,19 6,10,15,16,19 -DEVSEL B37 DEVSEL GND A37 B38 GND STOP A38 -STOP 6,10,15,16,19 6,10,15,16 -PLOCK B39 LOCK V3_3 A39 10,15,16 -PERR B40 PERR SDONE A40 SDONE 15,16 6,10,15,16,19 -SERR B41 V3_3 SBO A41 -SBO 15,16 B42 SERR GND A42 PAR 6,10,15,16,19 -C/BE1 B43 V3_3 PAR A43 B44 C/BE1 AD[15] A44 AD15 2 AD14 B45 AD[14] V3_3 A45 2 B46 GND AD[13] A46 AD13 AD12 B47 AD[12] AD[11] A47 AD11 AD10 B48 AD[10] GND A48 B49 GND AD[09] A49 AD9

AD8 B52 AD[08] C/BE0 A52 AD7 B53 AD[07] V3_3 A53 B54 V3_3 AD[06] A54 AD6 AD5 B55 AD[05] AD[04] A55 AD4 AD3 B56 AD[03] GND A56 B57 GND AD[02] A57 AD2 AD1 B58 AD[01] AD[00] A58 AD0 B59 V5_0 V5_0 A59 15,16 ACK64# B60 ACK64 REQ64 A60 REQ64# 15,16 B61 V5_0 V5_0 A61 B62 V5_0 V5_0 A62

PCI Conn -C/BE0

PCI SLOT 2

1 1

Intel Corporation

Embedded Intel Architecture Division 5000 W. Chandler Blvd. Chandler, AZ 85226-3699 THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT Designed By: Application Design-In Center (Folsom, CA) BEEN VERIFIED FOR MANUFACTURING AS AN END USER Title Intel® Pentium® III - Low Power / 440BX AGPset Reference Design

PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE Size Document Number Rev MISUSE OF THIS INFORMATION. C A0 Date:Monday, August 27, 2001 Sheet 17of 28 A B C D E A B C D E

V3_3 AGP Connector

C186 C185 C184 C179 C178 C166 C167 C177 C172 C180 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF

4 4

Pin A3 is tied to ground per AGP Specification Rev 1.0

V3_3 6 SBA[7:0]

V3_3 V3_3 +12V V3_3

V5_0

V5_0 J13 R65 V5_0 4.7K R64 B1 A1 4.7K B2 OVRCNT# 12V A2 B3 5.0V SPARE A3 14 U2A 14 B4 5.0V RESERVED A4 U2B B5 USB+ USB- A5 GND GND 2 1 B6 A6 3 4 PIRQB# 10,15,16,17,19,20 10,15,16,17,19,20 PIRQC# INTB# INTA# B7 A7 -PCIRST 6,10,16,17,19 6 GCLK CLK RST# B8 A8 GGNT# 6 6 GREQ# REQ# GNT# 74AS07 B9 A9 74AS07

7 3.3V 3.3V 7 B10 A10 GST1 6 6 GST0 ST0 ST1 6 GST2 B11 A11 3 ST2 RESERVED 3 6 GRBF# B12 A12 GPIPE# 6 B13 RBF# PIPE# A13 B14 GND GND A14 SPARE SPARE SBA0 B15 A15 SBA1 B16 SBA0 SBA1 A16 B17 3.3V 3.3V A17 SBA2 SBA2 SBA3 SBA3 6 GSB_STB B18 A18 B19 SB_STB RESERVED A19 GND GND SBA4 B20 A20 SBA5 B21 SBA4 SBA5 A21 SBA6 SBA6 SBA7 SBA7

B26 A26 GAD31 AD31 AD30 GAD30 GAD29 B27 A27 GAD28 B28 AD29 AD28 A28 B29 3.3V 3.3V A29 GAD27 AD27 AD26 GAD26 GAD25 B30 A30 GAD24 B31 AD25 AD24 A31 B32 GND GND A32 6 GAD_STB1 AD_STB1 RESERVED GAD23 B33 A33 GC/BE#3 Stub length from connector to resistor B34 AD23 C/BE3# A34 must be less than 0.1" B35 VDDQ3.3 VDDQ3.3 A35 GAD21 AD21 AD22 GAD22 GAD19 B36 A36 GAD20 B37 AD19 AD20 A37 V3_3 B38 GND GND A38 GAD17 AD17 AD18 GAD18 GC/BE#2 B39 A39 GAD16 B40 C/BE2# AD16 A40 VDDQ3.3 VDDQ3.3 6 GIRDY# B41 A41 GFRAME# 6 B42 IRDY# FRAME# A42 B43 SPARE NC A43 V3_3 B44 GND GND A44 R87 8.2K B45 SPARE NC A45 GAD_STB0 3.3V 3.3V 6 GDEVSEL# B46 A46 GTRDY# 6 R77 8.2K B47 DEVSEL# TRDY# A47 GAD_STB1 VDDQ3.3 STOP# GSTOP# 6 R83 8.2K B48 A48 PERR# PME# GPME# 20 R76 8.2K B49 A49 2 GSB_STB GND GND 2 R85 8.2K B50 A50 SERR# PAR GPAR 6 B51 A51 GC/BE#1 C/BE1# AD15 GAD15 B52 A52 VDDQ3.3 VDDQ3.3 B53 A53 GAD14 AD14 AD13 GAD13 B54 A54 GAD12 AD12 AD11 GAD11 B55 A55 GND GND R78 8.2K B56 A56 GFRAME# GAD10 AD10 AD9 GAD9 B57 A57 GAD8 AD8 C/BE0# GC/BE#0 R79 8.2K B58 A58 GIRDY# VDDQ3.3 3.3V B59 A59 6 GAD_STB0 AD_STB0 RESERVED R80 8.2K B60 A60 GTRDY# GAD7 AD7 AD6 GAD6 B61 A61 GND GND R82 8.2K B62 A62 GSTOP# GAD5 AD5 AD4 GAD4 GAD3 B63 A63 GAD2 R81 8.2K AD3 AD2 GDEVSEL# B64 VDDQ3.3 VDDQ3.3 A64 GAD1 B65 A65 GAD0 R72 8.2K AD1 AD0 GREQ# B66 SMB0 SMB1 A66 GGNT# R73 8.2K V3.3SUS AGP Connector GPIPE# R74 8.2K

GRBF# R75 8.2K

GPAR R86 8.2K

GPME# R84 8.2K

6 GAD[31:0] 1 1

6 GC/BE#[3:0] Intel Corporation

Embedded Intel Architecture Division 5000 W. Chandler Blvd. Chandler, AZ 85226-3699 THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT Designed By: Application Design-In Center (Folsom, CA) BEEN VERIFIED FOR MANUFACTURING AS AN END USER Title Intel® Pentium® III - Low Power / 440BX AGPset Reference Design

PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE Size Document Number Rev MISUSE OF THIS INFORMATION. C A0 Date:Monday, August 27, 2001 Sheet 18of 28 A B C D E A B C D E PIIX4E Part 1

6,10,16,17 AD[31:0] U8A SDD[15:0] 21 B10 E15 AD0 A10 AD0 SDD0 B15 SDD0 AD1 D9 AD1 SDD1 D14 SDD1 AD2 C9 AD2 SDD2 C14 SDD2 AD3 B9 AD3 SDD3 A14 SDD3 AD4 A9 AD4 SDD4 C13 SDD4 AD5 D8 AD5 SDD5 A13 SDD5 AD6 AD6 SDD6 SDD6 4 E8 C12 4 AD7 B8 AD7 SDD7 D12 SDD7 AD8 A8 AD8 SDD8 B13 SDD8 AD9 D7 AD9 SDD9 D13 SDD9 U21B AD10 C7 AD10 IDE SDD10 B14 SDD10 AD11 SDD11 B7 AD11 SDD11 E14 3 4 RSTDRV# 21 AD12 A7 AD12 SIGNALS SDD12 A15 SDD12 RSTDRV AD13 D6 AD13 SDD13 C15 SDD13 AD14 E6 AD14 SDD14 D15 SDD14 74HCT14 AD15 E4 AD15 SDD15 SDD15 AD16 C4 AD16 C18 AD17 SDCS3# 21 B4 AD17 DS3S# H16 PDCS3# 21 AD18 AD18 A4 AD18 DS3P# B18 AD19 SDCS1# 21 D3 AD19 DS1S# H17 PDCS1# 21 AD20 E3 AD20 PCI DS1P# AD21 AD21 C3 SA[19:0] 15,22,24,26 AD22 B3 AD22 SIGNALS U11 AD23 SA0 E2 AD23 SA0 T11 AD24 C2 AD24 SA1 W11 SA1 AD25 B2 AD25 SA2 Y11 SA2 AD26 SA3 A2 AD26 SA3 T10 AD27 SA4 D1 AD27 SA4 W10 AD28 SA5 R39 E1 AD28 SA5 U9 AD29 SA6 C1 AD29 SA6 V9 220 AD30 SA7 B1 AD30 SA7 Y9 AD31 SA8 AD31 SA8 T8 SA9 SA9 W8 6,10,16,17 -C/BE[3:0] SA10 C8 SA10 U7 -C/BE0 SA11 C6 C/BE#0 SA11 V7 -C/BE1 PIIX4E SA12 D4 C/BE#1 SA12 Y7 -C/BE2 SA13 D2 C/BE#2 SA13 V6 -C/BE3 SA14 C/BE#3 SA14 Y6 SA15 SA15 T5 PIIX4 is PCI SA16 C10 SA16 W5 6,10 CLKRUN# SA17 device #8 E5 CLOCKRUN# SA17 U4 6,10,15,16,17 -DEVSEL SA18 A5 DEVSEL# SA18 V4 R_AD18 6,10,15,16,17 -FRAME SA19 XD[7:0] 26 A3 FRAME# SA19 IDSEL 6,10,15,16,17 -IRDY B5 SD[15:0] 15,22,24,26 3 IRDY# U7 3 6,10,15,16,17 PAR B6 A1 PAR V3 2 18 6,10,16,17,18 -PCIRST SD0 SD0 A1 B1 XD0 B12 PCIRST# SD0 W3 3 17 6,15 -PHOLD SD1 SD1 A2 B2 XD1 A12 PHOLD# SD1 U2 4 16 6,15 -PHOLDA SD2 SD2 A3 B3 XD2 A6 PHOLDA# SD2 T2 5 15 6,10,15,16,17 -SERR SD3 SD3 A4 B4 XD3 Place near PIIX4 C229 D5 SERR# SD3 W2 6 14 6,10,15,16,17 -STOP STOP# SD4 SD4 SD4 A5 B5 XD4 47pF C5 Y2 7 13 6,10,15,16,17 -TRDY TRDY# SD5 SD5 SD5 A6 B6 XD5 Note: U14, C203,C215, C210 and T1 SD6 SD6 8 A7 B7 12 XD6 E10 ISA/EIO SD6 V1 9 11 6,15,16 -PREQ0 REQ0# SD7 SD7 SD7 A8 B8 XD7 R51 are not populated 6,15,16 -PREQ1 A11 W16 SD8 B11 REQ1# SIGNALS SD8 T16 19 6,15,17 -PREQ2 REQ2# SD9 SD9 20 XOE# G C11 Y17 SD10 1 6,10,15 -PREQ3 REQ3# SD10 20 XDIR# DIR V5_0 V17 SD11 SD11 74ALS245 21 PDD[15:0] Y18 SD12 F20 SD12 W18 PDD0 PDD0 SD13 SD13 PDD1 E18 Y19 SD14 E20 PDD1 SD14 W19 C203 C215 C210 PDD2 PDD2 SD15 SD15 0.1uF 0.1uF 0.1uF PDD3 D18 LA[23:17] 15,24 D20 PDD3 Y15 PDD4 PDD4 GPO1/LA17 LA17 PDD5 C20 T14 LA18 B20 PDD5 GPO2/LA18 W14 PDD6 LA19 U14 64 19 51 A20 PDD6 GPO3/LA19 U13 PDD7 PDD7 GPO4/LA20 LA20 PDD8 A19 V13 LA21 B19 PDD8 GPO5/LA21 Y13 PDD9 PDD9 GPO6/LA22 LA22 VCC VCC VCC PDD10 C19 T12 LA23 59 4 APICD0 15 D19 PDD10 GPO7/LA23 58 D0 APICD0 5 PDD11 PDD11 D1 APICD1 APICD1 15 PDD12 D17 57 62 APICCLK0 14 E19 PDD12 Y12 56 D2 APICCLK PDD13 PDD13 MEMCS16# MEMCS16# 15,24 E17 V15 55 D3 PDD14 PDD14 MEMR# MEMR# 15,24,26 F19 U15 54 D4 17 PDD15 PDD15 MEMW# MEMW# 15,24,26 INTR 4,15,20 W4 53 D5 INTIN0 34 SMEMR# SMEMR# 15,24 D6 INTIN1 IRQ1 15,20,22 50 35 IRQ0 20 U3 D7 INTIN2 25 SMEMW# SMEMW# 15,24 IRQ3 15,20,22,24 C17 T7 15 INTIN3 26 21 SDA0 SDA0 SYSCLK SYSCLK 24 SA4 IRQ4 15,20,22,24 B17 U10 13 D/I# INTIN4 27 21 SDA1 SDA1 GPO0/BALE BALE 15,24 SA0 IRQ5 15,20,22,24 A18 Y1 14 A0 INTIN5 28 21 SDA2 SDA2 GPI0/IOCHK# IOCHK# 15,24 SA1 IRQ6 15,20,22,24 G19 IDE 12 A1 INTIN6 29 21 PDDACK# PDDACK# MEMR# IRQ7 15,20,22,24 A17 W7 11 RD# INTIN7 31 2 21 SDDACK# SDDACK# REFRESH# REFRESH# 15,24 MEMW# IRQ8_Buf 2 F18 SIGNALS V12 61 WR# INTIN8 30 21 PDREQ PDREQ# IOCS16# IOCS16# 15,24 15,20 APICCS# CS# INTIN9 IRQ9 15,20,24 A16 Y3 24 21 SDREQ SDREQ# ZEROWS# ZEROWS# 15,24 IRQ10 15,20,22,24 F17 9 INTIN10 23 21 PDIOR# PDIOR# 20 APICREQ# APICREQ# INTIN11 IRQ11 15,20,24 F16 W12 10 22 21 PDIOW# PDIOW# SBHE# SBHE# 15,24 20 APICACK1# APICACK1# INTIN12 IRQ12 15,20,22,24 G20 W1 8 16 21 PIORDY PIORDY RSTDRV RSTDRV 22,24 6 WSC# APICACK2# INTIN13 I13R C16 Y5 18 21 SDIOR# SDIOR# IOR# IOR# 15,22,24 INTIN14 IRQ14 15,20,21,22,24 B16 T4 2 21 21 SDIOW# SDIOW# IOW# IOW# 15,22,24,26 14 PCLKAPIC PCICLK INTIN15 IRQ15 15,20,21,22,24 D16 T3 60 37 21 SIORDY SIORDY IOCHRDY IOCHRDY 15,22,24 RSTDRV RESET INTIN16 PIRQA# 10,15,16,17,20 G16 Y4 38 21 PDA0 PDA0 AEN AEN 22,24,26 INTIN17 PIRQB# 10,15,16,17,18,20 G18 V5_0 39 21 PDA1 PDA1 INTIN18 PIRQC# 10,15,16,17,18,20 G17 3 40 21 PDA2 PDA2 TESTIN# INTIN19 PIRQD# 10,15,16,17,20 41 RP59 INTIN20 IRQ9OUT# 20 42 INTIN21 I21R PIIX4E 8 1 7 43 NC INTIN22 I22R 7 2 20 44 I13R NC INTIN23/SMI# PX4_SMI# 15,20 6 3 32 6 I21R NC SMIOUT# 5 4 I22R 36 NC 45 NC 10K 46 NC 47 NC 48 J23 NC 1 49 NC 63 NC 2 SMI# 4 RSTDRV JUMP3 3

V2_5 V3.3SUS 1

2 D4 GND GND GND Bat54 82093AA 1 33 52 R117 10K VCCT 3 This circuit is to prevent IOAPIC R51 1K

1 from being powered by IRQ#8 1 when in suspend and power 14 1 R50 680 is not applied to device. IRQ8_Buf 20 IRQ#8 2 3 Intel Corporation

7 U15A Embedded Intel Architecture Division 74LVC125 5000 W. Chandler Blvd. Chandler, AZ 85226-3699 THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT Designed By: Application Design-In Center (Folsom, CA) Title BEEN VERIFIED FOR MANUFACTURING AS AN END USER Intel® Pentium® III - Low Power / 440BX AGPset Reference Design Size Document Number Rev PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE C A0

MISUSE OF THIS INFORMATION. Date:Monday, August 27, 2001 Sheet 19of 28 A B C D E A B C D E

PIIX4E Part 2 V3_3

V3.3SUS

C195 C191 C193 C188 C187 C192 C190 C189 C194 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF

4 4

U8B R15 R6 F15 E11 F6 T6 P15 R7 G6 F14 F5 E16 E12 E9 K5 N16 R16 VCC VCC VCC VCC U14 VCC 22,24 DACK0# VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP DACK0# 22,24 DACK1# W6 VCCSUS Y10 DACK1# VCCSUS 22,24 DACK2# VCCSUSB DACK2# 22,24 DACK3# V5 DACK3# 24 DACK5# T15 F1 USBP1+ 23 DACK5# USBP1+ 24 DACK6# V16 H2 USBP1- 23 DACK6# USBP1- V3.3SUS 24 DACK7# W17 G2 USBP0+ 23 DACK7# USB USBP0+ H3 USBP0- 23 USBP0- 15,22,24 DRQ0 W15 J1 OC0# 23 DREQ0 SIGNALS OC0# 15,22,24 DRQ1 U6 J2 OC1# 23 V3_3 DREQ1 OC1# TP11 15,22,24 DRQ2 V2 U5 DREQ2 V20 14

15,22,24 DRQ3 TP DREQ3 EXTSMI# EXTSMI# U24E 15,24 DRQ5 Y16 W20 SUSA# 14 DREQ5 SUSA# 15,24 DRQ6 U16 V19 DREQ6 GPO15/SUSB# 1 U17 U18 11 10 PWRON# 27 RP30 15,24 DRQ7 DREQ7 GPO16/SUSC# 8 1 M1 7 2 N2 REQA#/GPI2 R1 74LVC14 CPU_STOP# 14 TP13 REQB#/GPI3 GPO17/CPU_STP# 7 6 3 P3 POWER R2 PCI_STOP# 14 5 4 N1 REQC#/GPI4 GPO18/PCI_STP# K16 GNTA#/GPO9 MGMT. GPO19/ZZ TP P2 T17 SUS_STAT1# 6 GNTB#/GPO10 GPO20/SUS_STAT1# 10K P4 T18 GNTC#/GPO11 GPO21/SUS_STAT2# H19 1 V3.3SUS V3_3 THERM# V10 GPI8/HCT# U19 22,24 TC TC GPI9/BATLOW# BATLOW# J17 M17 RSMRST# 27 19 APICACK1# APICACK#/GPO12 DMA/IRQ RSMRST# 15,19 APICCS# H18 U20 PWRBTN# 27 K18 APICCS#/GPO13 PWRBT# P16 19 APICREQ# LID APICREQ#/GP15 SIGNALS GPI10/LID T20 SMBDATA SMBDATA 8,11,12,13,14,15 19 IRQ0 H20 R19 SMBCLK 8,11,12,13,14,15 J20 IRQ0/GP014 SMBCLK N17 15,19,22 IRQ1 SMBALERT# IRQ1 GPI11/SMBALERT# RP39 10K 15,19,22,24 IRQ3 T9 P18 GPME# 18 W9 IRQ3 GPI12/RI#A 1 8 15,19,22,24 IRQ4 IRQ4 SERIRQ 15,19,22,24 IRQ5 U8 THERM# 2 7 3 V8 IRQ5 3 6 3 15,19,22,24 IRQ6 IRQ6 V5_0 LID 15,19,22,24 IRQ7 Y8 EXTSMI# 4 5 Y20 IRQ7 19 IRQ#8 IRQ8/GPI6 15,19,24 IRQ9 U1 U12 IRQ9 15,19,22,24 IRQ10 IRQ10 R42 15,19,24 IRQ11 W13 IRQ11 V3_3 RP36 10K 15,19,22,24 IRQ12 T13 PIIX4E 1K D3 V14 IRQ12 1 8 15,19,21,22,24 IRQ14 Bat542 SMBALERT# Y14 IRQ14 2 7 15,19,21,22,24 IRQ15 IRQ15 TEST# CONFIG2 3 6 J19 J16 1 3 4 5 SERIRQ SERIRG/GPI7 VREF IRQ#8 10,15,16,17,19 PIRQA# R3 R4 PIRQA# C134 10,15,16,17,18,19 PIRQB# PIRQB# C129 V3.3SUS 10,15,16,17,18,19 PIRQC# P5 10uF G1 PIRQC# 0.1uF 10,15,16,17,19 PIRQD# PIRQD# R300 0 Populate R366 and 4,15 SLP# K20 SLP# RP31 10K 15 CPURST M19 remove R306 if K19 CPURST 1 8 4 FERR# R301 0 FERR# STPCLK controlled 4,15 IGNNE# L17 P19 2 7 R302 0 L18 IGNNE# GPI1 L2 3 6 by microcontroller 4,15 INIT R303 0 INIT GPI13 4,15,19 INTR L19 J3 4 5 and not by PIIX4E. P1 INTR CPU GPI14 L5 RP28 10K 15 STPCLK_P# 22 KBDA20GATE R304 0 A20GATE# GPI15 4,15 NMI L20 K3 1 8 R305 0 P20 NMI INTERFACE GPI16 K4 2 7 15,19 PX4_SMI# SMI# GPI17 4,8 STPCLK# J18 H1 3 6 N20 STPCLK# GPI18 H4 4 5 R306 22 KBDRST# R307 0 RCIN# GPI19 4,15 A20M# M20 H5 0 M18 A20M# GPI20 G3 6,27 PWROK PWROK GPI21 K17 RP32 V18 SPKR TEST# TEST# R17 SYSTEM 8 1 CONFIG1 R18 7 2 CONFIG2 CONFIG2 6 3 TP4 BATLOW# 5 4 TP15 M4

19 XOE# XOE#/GPO23 TP TP5 M3 10K 19 XDIR# XDIR#/GPO22 TP TP3 M2 G4

2 Keep crystal close to PIIX4 and 26 BIOSCS# BIOSCS# GPO0 TP 2 L1 X-BUS T19 1 RTCALE/GPO25 GPO8 TP caps close to crystal K2 G5 1 RTCCS#/GPO24 GPO27 K1 F2 1 KBCCS#/GPO26 GPO28 F3 1 C132 GPO29/IRQ9Out IRQ9OUT# 19 F4 GPO30 R20 RTCX2 N19 2 R310 RTCX1 10pF L16 Trace lengths Y2 VBAT 1M N/C J4 P17 N18 should be equal C133 32.768KHz SUSCLK N/C 14 USBCLK0 L3 48Mhz N/C N3 1 R309 0 N/C M16 14 REF2 V11 OSC N/C M5 10pF 14 PCICLKF D11 PCICLK N/C R5 Do not populate. VSS - D10,E7,E13,J[9:12] K[9:12],L[9:12],M[9:12] MCCS# N4 R110 VSSUSB J5 PCS0# L4 PCS1# N5 V3.3SUS 3 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSUSB VSS VSS VSS VSS VSS VSS VSS VSS VSS D7

2 Bat54 D10 E7 E13 J9 J10 J11 J12 K9 K10 K11 K12 L9 L10 L11 L12 M9 M10 M11 M12 J5 PIIX4E 1

1-2 Normal Operation

2 2-3 Clear CMOS

1 3 1 J24 1 1

D6 Bat54 2 JUMP3 1

C147 3 Intel Corporation BT1 0.1uF BATTERY Embedded Intel Architecture Division 5000 W. Chandler Blvd.

2 R63 Chandler, AZ 85226-3699 1K THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT Designed By: Application Design-In Center (Folsom, CA) BEEN VERIFIED FOR MANUFACTURING AS AN END USER Title Intel® Pentium® III - Low Power / 440BX AGPset Reference Design

PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE Size Document Number Rev MISUSE OF THIS INFORMATION. C A0 Date:Monday, August 27, 2001 Sheet 20of 28 A B C D E A B C D E IDE Connectors Primary IDE Connector

19 PDD[15:0]

IDERSTP#R PDD7 RP61 33 JP4 R123 1 8 RP47 33 10k 4 PDD7 12 4 2 7 34 1 8 R107 PDD6 3 6 2 7 PDD8 PDD5 56 PDD9 8.2K 4 5 3 6 PDD4 78 PDD10 910 4 5 1 8 RP44 33 PDD11 PDD3 11 12 2 7 13 14 1 8 PDD2 3 6 2 7 PDD12 PDD1 15 16 PDD13 4 5 17 18 3 6 RP58 33 PDD0 RP60 33 4 5 PDD14 19 20 PDD15 19 PDREQ 1 8 21 22 2 7 PDREQR 19 PDIOW# PDIOW#R 23 24 19 PDIOR# 3 6 25 26 4 5 PDIOR#R 19 PDDACK# PDIORDYR 27 28 CSEL1 29 30 PDDACK#R R103 RP55 33 31 32 1 8 PDIRQR 19 PDA1 PDA1R 33 34 470 19 PDA0 2 7 35 36 3 6 PDA0R PDA2R 19 PDCS1# PDCS1#R 37 38 PDCS3#R 4 5 39 40 19 RSTDRV# IDERSTP#R V5_0 HEADER 20X2

R58 220

V5_0 1 2 R54 R55 IN 10k 10k D5 NC LGS260-DO HD Active LED 3 OUT 3 3 U22A 14 U25A 1 3 1 2 HD_ACT2# 2 74ALS00 74ACT05 7

Secondary IDE Connector

19 SDD[15:0]

IDERSTS#R SDD7 RP46 33 JP3 R124 RP45 33 SDD7 1 8 12 10k SDD6 2 7 1 8 SDD8 R96 34 SDD5 3 6 56 2 7 SDD9 8.2K SDD4 4 5 78 3 6 SDD10 910 4 5 SDD11 RP42 33 SDD3 1 8 11 12 SDD2 2 7 13 14 1 8 SDD12 SDD1 3 6 15 16 2 7 SDD13 SDD0 4 5 17 18 3 6 SDD14 RP41 33 RP43 33 19 20 4 5 SDD15 19 SDREQ 1 8 SDREQR 21 22 19 SDIOW# 2 7 SDIOW#R 23 24 19 SDIOR# 3 6 SDIOR#R 25 26 19 SDDACK# 4 5 SDIORDYR 27 28 CSEL2 SDDACK#R 29 30 2 R104 2 RP56 33 SDIRQR 31 32 19 SDA1 1 8 SDA1R 33 34 470 19 SDA0 2 7 SDA0R 35 36 SDA2R 19 SDCS1# 3 6 SDCS1#R 37 38 SDCS3#R RSTDRV# 4 5 IDERSTS#R 39 40 HEADER 20X2

HD_ACT2# V5_0

R102 R101 1K 1K

RP57 47 19 PIORDY 1 8 PDIORDYR PDIRQR 15,19,20,22,24 IRQ14 2 7 SDIORDYR 19 SIORDY 3 6 SDIRQR 15,19,20,22,24 IRQ15 4 5

1 1 RP54 33 PDA2R 19 PDA2 1 8 SDA2R 19 SDA2 2 7 PDCS3#R 19 PDCS3# 3 6 SDCS3#R Intel Corporation 19 SDCS3# 4 5 Embedded Intel Architecture Division 5000 W. Chandler Blvd. Chandler, AZ 85226-3699 Designed By: Application Design-In Center (Folsom, CA)

Title Intel® Pentium® III - Low Power / 440BX AGPset Reference Design

THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT Size Document Number Rev BEEN VERIFIED FOR MANUFACTURING AS AN END USER C A0 Date:Monday, August 27, 2001 Sheet 21of 28 A B CPRODUCT. INTEL IS NOT RESPONSIBLED FOR THE E MISUSE OF THIS INFORMATION. A B C D E Super I/O V5_0 V3_3 V5_0

C160 C161 C159 0.1uF 0.1uF 0.1uF

U1 62 93 121 69 65 19 20 21 15,19,24,26 SD[15:0] Install for 370 Config address VTR VCC VCC VCC

44 VBAT SD0 SD0 4 45 16 -RDATA 25 4 SD1 46 SD1 RDATA# 11 POWERON PME#/IRQ9 -WGATE 25

SD2 BUTTON_IN SD2 47 WGATE# 10 SD3 -WDATA 25 SD3 49 WDATA# 12 SD4 -SIDE1 25 SD4 50 HDSEL# 8 V5_0 SD5 -DIR 25 SD5 51 DIR# 9 SD6 -STEP 25 R5 SD6 52 STEP# 17 SD7 SD7 Floppy DSKCHG# -DSKCHG 25 15,19,24,26 SA[19:0] 5 -DRVSA 25 23 DS0# 6 SA0 SA0 DS1# -DRVSB 25 24 3 -MOTEA 25 10K SA1 25 SA1 MTR0# 4 SA2 SA2 MTR1 -MOTEB 25 Install only one 26 15 -WPT 25 SA3 27 SA3 WRTPRT# 14 resistor! SA4 SA4 TRK0# -TRK0 25 28 SA5 13 -INDEX 25 SA5 29 INDEX# 1 SA6 SA6 DRVDEN0 HDEN 25 R6 30 SA7 2 DRATE0 25 SA7 31 DRVDEN1 SA8 SA8 ISA/Host 32 112 SA9 SA9 RXD1 RXD0 25 33 SA10 113 TXD0 25 1K SA10 34 TXD1 115 SA11 RTS0# 25 35 SA11 RTS1#/SYSOP 116 Do not stuff SA12 CTS0# 25 36 SA12 CTS1# 117 SA13 DTR1# DTR0# 25 37 SA13 114 SA14 Uarts DSR0# 25 38 SA14 DSR1# 119 SA15 DCD0# 25 SA15 DCD1# 118 Install for 3F0 Config RI1# RI0# 25 19,24,26 AEN 43 AEN 123 RXD1 25 address 64 RXD2/IRRX 124 15,19,24 IOCHRDY IOCHRDY TXD2/IRTX TXD1 25 19,24 RSTDRV 53 RESET_DRV 126 RTS1# 25 40 RTS2# 127 15,19,20,21,24 IRQ15 SER/IRQ15 CTS2# CTS1# 25 15,19,20,21,24 IRQ14 39 128 DTR1# 25 55 PCI_CLK/IRQ14/GP50 DTR2# 125 15,20,24 DRQ0 DRQ0 DSR2# DSR1# 25 57 122 15,20,24 DRQ1 DRQ1 DCD2# DCD1# 25 59 120 15,20,24 DRQ2 DRQ2 RI2# RI1# 25 15,20,24 DRQ3 61 DRQ3 20,24 DACK0# 54 DACK0# 56 20,24 DACK1# DACK1# 58 96 20,24 DACK2# DACK2# PD0 PDR0 25 60 97 20,24 DACK3# DACK3# PD1 PDR1 25 3 63 98 3 20,24 TC TC PD2 PDR2 25 41 99 15,19,24 IOR# IOR# PD3 PDR3 25 42 100 15,19,24,26 IOW# IOW# PD4 PDR4 25 101 PD5 PDR5 25 Parallel PD6 102 PDR6 25 14 REF1 22 CLOCK14 PD7 103 PDR7 25 66 95 XTL1 SLCTIN# -SLCTRIN 25 68 94 XTL2 PINIT# -INIT 25 18 CLK32OUT ALF# 110 -ALF 25 STROBE# 111 -STROBE 25 BUSY 107 -BUSY 25 ACK# 108 -ACK 25 70 106 KDAT PE PE 25 71 105 KCLK SLCT SLCT 25 72 109 MDAT ERROR# -ERR 25 73 MCLK 20 KBDRST# 75 KBDRST# 20 KBDA20GATE 76 A20M GP10 77 15,19,20 IRQ1 83 IRQ1 GP11 78 15,19,20,24 IRQ3 84 IRQ3 GP12 79 85 80 V5_0 15,19,20,24 IRQ4 IRQ4 GP13 15,19,20,24 IRQ5 86 IRQ5 GP14 81 15,19,20,24 IRQ6 87 IRQ6 GP15 82 15,19,20,24 IRQ7 88 IRQ7 89 R11 IRQ8 15,19,20,24 IRQ10 90 IRQ10 91 IRQ11/ROMCS# 15,19,20,24 IRQ12 92 IRQ12 10K VSS VSS VSS VSS

This disables the ROM buffers. AVSS FDC37B78X

BIOS needs to enable and 67 7 48 74 104 configure IRQs

2 PULL romCs# high so as not to 2 interfere with boot rom! V5_0

V5_0

F3 SMD250-002 8 7 6 5 2 RP48 FB9 4.7K BLM41P750S 12 1 2 3 4 1

J1 FB8 1 2 T1 12 KBDATA T2 NC BLM41A800S T3 GND FB5 T4 KB_VCC 1 2 T5 12 KB_CLK T6 TOP BLM41A800S NC 13 GND 14 GND 15 GND 16 GND GND 17 FB7 1 122 B1 MDATA 1 1 B2 NC BLM41A800S B3 GND FB6 B4 M_VCC BOTTOM 1 122 B5 M_CLK B6 NC BLM41A800S Intel Corporation PS2 STACK Embedded Intel Architecture Division 5000 W. Chandler Blvd. Chandler, AZ 85226-3699 C29 C30 C28 C31 C32 Designed By: Application Design-In Center (Folsom, CA) 470pF 470pF 470pF 470pF 470pF THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT Title BEEN VERIFIED FOR MANUFACTURING AS AN END USER Intel® Pentium® III - Low Power / 440BX AGPset Reference Design Size Document Number Rev PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE C A0

MISUSE OF THIS INFORMATION. Date:Monday, August 27, 2001 Sheet 22of 28 A B C D E A B C D E USB Connectors

USBVFIL1 USBVFIL2

R4 R2 10K 10K V5_0

4 20 OC1# 20 OC0# 4 R3 R1 C7 15K C1 15K SMD250-002 F2 F1 SMD250002 0.01UF 0.01UF Poly-Fuse Poly-Fuse Poly fuses should be in range of 1.5A to 5A

USBVFIL1

USBVFIL2 2 2 FB4 FB3 Place these caps within 1 inch BLM41P750S BLM41P750S of USB Connector stack 12 12 75 Ohm/100

1 1 MHz/3A 75 Ohm/100 MHz/3A

C2 C157 C158 100uF 0.1uF 0.01uF C6 C22 C23 100uF 0.1uF 0.01uF Place As Close as Possible to PIIX4 Z1_VCC Z0_VCC R95 27 20 USBP0- Z0-

R94 27 20 USBP0+ PCB Trace 45 Ohm Matched, Z0+ J2 3 Routed Together BOTTOM of Stacked 3 R90 R91 Stripline width 0.015 (1 oz) USB Connector C123 C122 1 15K 15K 44.88/45.45 Ohm VCC0 2 9 47pF 47pF D0- GND 3 10 D0+ GND 4 Z0_GND GND0 1

1 FB1 5 VCC1 BLM41P750S 6 D1- GND 11 7 12

2 D1+ GND 8 GND1 2

USB Stack TOP of Stacked USB Connector

PCB Trace 45 Ohm Matched, Routed Together Place As Close as Stripline width 0.015 (1 oz) 44.88/45.45 Possible to PIIX4 R93 27 Ohm 20 USBP1- Z1-

R92 27 20 USBP1+ Z1+

R88 R89 C125 C124 15K 15K 2 47pF 47pF 2

Z1_GND 1

1 FB2 BLM41P750S 2 2

NOTE 1: USB differential traces route together (Z0- & Z0+) and (Z1- & Z1+). Must be 45 Ohm Matched Stripline width 0.015 (for 1 oz)->44.88/45.45 Ohm. NOTE 2: Protect differential traces w/ guard traces or double space to any other signal. NOTE 3: Place ferrites at connector.

NOTE 4: Poly-fuse min 1.5A max 5A.

1 1

Intel Corporation

Embedded Intel Architecture Division 5000 W. Chandler Blvd. Chandler, AZ 85226-3699 THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT Designed By: Application Design-In Center (Folsom, CA) BEEN VERIFIED FOR MANUFACTURING AS AN END USER Title Intel® Pentium® III - Low Power / 440BX AGPset Reference Design

PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE Size Document Number Rev MISUSE OF THIS INFORMATION. C A0 Date:Monday, August 27, 2001 Sheet 23of 28 A B C D E A B C D E

ISA Connectors -5V -12V +12V V5_0

C3 C60 C59 C4 C63 C62 C5 C71 C70 C8 C111 C112 C42 C126 C127 10uF 0.1uF 0.1uF 10uF 0.1uF 0.1uF 10uF 0.1uF 0.1uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF

Note Cap Direction Note Cap Direction 4 4

15,19,22,26 SA[19:0] SA[19:0]

15,19,22,26 SD[15:0] SD[15:0]

15,19 LA[23:17] LA[23:17]

+12V -12V -5V +12V -12V -5V 3 3

J5 J6 B1 A1 B1 A1 GND IOCHCK IOCHK# 15,19 GND IOCHCK IOCHK# 19,22 RSTDRV B2 RSTDRV SD7 A2 SD7 RSTDRV B2 RSTDRV SD7 A2 SD7 B3 V5_0 SD6 A3 SD6 B3 V5_0 SD6 A3 SD6 15,19,20 IRQ9 B4 IRQ9 SD5 A4 SD5 IRQ9 B4 IRQ9 SD5 A4 SD5 B5 A5 B5 A5 -5V SD4 SD4 -5V SD4 SD4 15,20,22 DRQ2 B6 DRQ2 SD3 A6 SD3 DRQ2 B6 DRQ2 SD3 A6 SD3 B7 -12V SD2 A7 SD2 B7 -12V SD2 A7 SD2 B8 A8 B8 A8 15,19 ZEROWS# 0WS SD1 SD1 ZEROWS# 0WS SD1 SD1 B9 A9 B9 A9 +12V SD0 SD0 +12V SD0 SD0 B10 A10 B10 A10 GND IOCHRDY IOCHRDY 15,19,22 GND IOCHRDY IOCHRDY 15,19 SMEMW# B11 SMEMW AEN A11 AEN 19,22,26 MEMW# B11 SMEMW AEN A11 AEN B12 A12 B12 A12 15,19 SMEMR# SMEMR SA19 SA19 MEMR# SMEMR SA19 SA19 15,19,22,26 IOW# B13 IOW SA18 A13 SA18 IOW# B13 IOW SA18 A13 SA18 B14 A14 B14 A14 15,19,22 IOR# IOR SA17 SA17 IOR# IOR SA17 SA17 20,22 DACK3# B15 DACK3 A15 SA16 DACK3# B15 DACK3 A15 SA16 B16 SA16 A16 B16 SA16 A16 15,20,22 DRQ3 DRQ3 SA15 SA15 DRQ3 DRQ3 SA15 SA15 20,22 DACK1# B17 DACK1 SA14 A17 SA14 DACK1# B17 DACK1 SA14 A17 SA14 15,20,22 DRQ1 B18 DRQ1 SA13 A18 SA13 DRQ1 B18 DRQ1 SA13 A18 SA13 15,19 REFRESH# B19 REFRESH SA12 A19 SA12 REFRESH# B19 REFRESH SA12 A19 SA12 19 SYSCLK B20 CLK SA11 A20 SA11 SYSCLK B20 CLK SA11 A20 SA11 15,19,20,22 IRQ7 B21 IRQ7 SA10 A21 SA10 IRQ7 B21 IRQ7 SA10 A21 SA10 15,19,20,22 IRQ6 B22 IRQ6 SA9 A22 SA9 IRQ6 B22 IRQ6 SA9 A22 SA9 15,19,20,22 IRQ5 B23 IRQ5 SA8 A23 SA8 IRQ5 B23 IRQ5 SA8 A23 SA8 15,19,20,22 IRQ4 B24 IRQ4 SA7 A24 SA7 IRQ4 B24 IRQ4 SA7 A24 SA7 15,19,20,22 IRQ3 B25 IRQ3 SA6 A25 SA6 IRQ3 B25 IRQ3 SA6 A25 SA6 20,22 DACK2# B26 DACK2 SA5 A26 SA5 DACK2# B26 DACK2 SA5 A26 SA5 20,22 TC B27 TC SA4 A27 SA4 TC B27 TC SA4 A27 SA4 15,19 BALE B28 BALE SA3 A28 SA3 BALE B28 BALE SA3 A28 SA3 B29 V5_0 SA2 A29 SA2 B29 V5_0 SA2 A29 SA2 14 REF0 B30 OSC SA1 A30 SA1 REF0 B30 OSC SA1 A30 SA1 B31 GND SA0 A31 SA0 B31 GND SA0 A31 SA0

2 2 15,19 MEMCS16# D1 MCS16 SBHE C1 SBHE# 15,19 MEMCS16# D1 MCS16 SBHE C1 SBHE# 15,19 IOCS16# D2 IOCS16 LA23 C2 LA23 IOCS16# D2 IOCS16 LA23 C2 LA23 D3 C3 D3 C3 15,19,20,22 IRQ10 IRQ10 LA22 LA22 IRQ10 IRQ10 LA22 LA22 D4 C4 D4 C4 15,19,20 IRQ11 IRQ11 LA21 LA21 IRQ11 IRQ11 LA21 LA21 D5 C5 D5 C5 15,19,20,22 IRQ12 IRQ12 LA20 LA20 IRQ12 IRQ12 LA20 LA20 D6 C6 D6 C6 15,19,20,21,22 IRQ15 IRQ15 LA19 LA19 IRQ15 IRQ15 LA19 LA19 D7 C7 D7 C7 15,19,20,21,22 IRQ14 IRQ14 LA18 LA18 IRQ14 IRQ14 LA18 LA18 D8 C8 D8 C8 20,22 DACK0# DACK0 LA17 LA17 DACK0# DACK0 LA17 LA17 15,20,22 DRQ0 D9 DRQ0 MEMR C9 MEMR# 15,19,26 DRQ0 D9 DRQ0 MEMR C9 MEMR# 20 DACK5# D10 DACK5 MEMW C10 MEMW# 15,19,26 DACK5# D10 DACK5 MEMW C10 MEMW# 15,20 DRQ5 D11 DRQ5 SD8 C11 SD8 DRQ5 D11 DRQ5 SD8 C11 SD8 20 DACK6# D12 DACK6 SD9 C12 SD9 DACK6# D12 DACK6 SD9 C12 SD9 15,20 DRQ6 D13 DRQ6 SD10 C13 SD10 DRQ6 D13 DRQ6 SD10 C13 SD10 20 DACK7# D14 DACK7 SD11 C14 SD11 DACK7# D14 DACK7 SD11 C14 SD11 15,20 DRQ7 D15 DRQ7 SD12 C15 SD12 DRQ7 D15 DRQ7 SD12 C15 SD12 D16 V5_0 SD13 C16 SD13 D16 V5_0 SD13 C16 SD13 15 MASTER16# D17 MASTER SD14 C17 SD14 MASTER16# D17 MASTER SD14 C17 SD14 D18 GND SD15 C18 SD15 D18 GND SD15 C18 SD15 ISA Conn A ISA Conn B

J5/J6 V5_0: B03, B29, B31, D16 J5/J6 GND: B01, B10, D18 J5/J6: +12V B09 -12V B07 -5V B05

1 1

Intel Corporation

Embedded Intel Architecture Division 5000 W. Chandler Blvd. Chandler, AZ 85226-3699 THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT Designed By: Application Design-In Center (Folsom, CA) BEEN VERIFIED FOR MANUFACTURING AS AN END USER Title Intel® Pentium® III - Low Power / 440BX AGPset Reference Design

PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE Size Document Number Rev MISUSE OF THIS INFORMATION. C A0 Date:Monday, August 27, 2001 Sheet 24of 28 A B C D E A B C D E

Serial / Parallel / Floppy -12V +12V V5_0 -12V +12V V5_0

V5_0

C49 C54 C64 C43 C48 C65 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF

+12V 8 7 6 5 8 7 6 5 8 7 6 5 U4 RP5 RP6 RP7 20 1 R7 V5_0 +12V 4.7K 4.7K 4.7K 19 2 4.7K 22 DCD0# RY1 RA1 SP_DCD0 PARALLEL 18 3 4 22 DSR0# RY2 RA2 4 17 4 SP_DSR0 22 RXD0 RY3 RA3 16 5 SP_RXD0 1 2 3 4 1 2 3 4 1 2 3 4 22 RTS0# DA1 DY1 J4 15 6 SP_RTS0 22 TXD0 DA2 DY2 SP_TXD0 R9 22 CTS0# 14 RY4 RA4 7 13 8 SP_CTS0 5 22 DTR0# DA3 DY3 5 22 -SLCTRIN 12 9 SP_DTR0 9 -PSLCTIN 22 RI0# RY5 RA5 9 11 10 SP_RI0 4 GND -12V 4 22 8 8 3 -PPINIT GD75232SOP 3 C53 C52 C51 C50 7 C12 470pF 470pF 470pF 470pF 7 COM0 220pF 2 2 6 -12V 6 1 1 C40 C39 C38 C37 470pF 470pF 470pF 470pF -PPERR C11 220pF 14 14 SERIAL 18 18 13 13 +12V 17 17 12 12 COM1 -PALF 16 16 U3 C24 11 11 20 1 15 220pF V5_0 +12V 15 19 2 10 22 DCD1# RY1 RA1 SP_DCD1 10 18 3 22 DSR1# RY2 RA2 SP_DSR1 17 4 22 RXD1 RY3 RA3 SP_RXD1 16 5 22 RTS1# DA1 DY1 SP_RTS1 SERIAL STACK -PSTROBE 15 6 22 TXD1 DA2 DY2 SP_TXD1 14 7 RP1 C9 22 CTS1# RY4 RA4 SP_CTS1 13 8 1 8 220pF 22 DTR1# DA3 DY3 SP_DTR1 22 -INIT -INIT 12 9 2 7 22 RI1# RY5 RA5 SP_RI1 22 -ERR -ERR 11 10 3 6 GND -12V 22 -ALF -ALF 4 5 22 -STROBE -STROBE GD75232SOP PPDR0 C47 C46 C45 C44 22 3 470pF 470pF 470pF 470pF C10 3 220pF -12V

C36 C35 C34 C33 470pF 470pF 470pF 470pF PPDR1 C25 220pF

PPDR2 RP2 1 8 C26 22 PDR0 PDR0 220pF 22 PDR1 PDR1 2 7 22 PDR2 PDR2 3 6 22 PDR3 PDR3 4 5

33 PPDR3 V5_0 C13 220pF 26 27

PPDR4 1 14 4 3 2 1 C14 2 RP18 220pF 15 R25 1K 3 1K 16 FLOPPY 4 RP3 17 5 6 7 8 22 PDR4 PDR4 1 8 PPDR5 5 PDR5 2 7 18 22 PDR5 C15 22 PDR6 PDR6 3 6 6 4 5 220pF 19 2 22 PDR7 PDR7 2 7 33 20 8 21 JP1 PPDR6 9 C16 22 22 -DSKCHG 34 33 220pF 10 22 -SIDE1 32 31 23 22 -RDATA 30 29 11 22 -WPT 28 27 24 22 -TRK0 26 25 12 22 -WGATE 24 23 PPDR7 25 22 -WDATA 22 21 C17 13 22 -STEP 20 19 220pF 22 -DIR 18 17 22 -MOTEB 16 15 J3 22 -DRVSA 14 13 RP4 DB25 22 -DRVSB 12 11 1 8 22 -MOTEA 10 9 22 -ACK -ACK -PPACK 22 -INDEX 8 7 22 -BUSY -BUSY 2 7 PE 3 6 C18 22 DRATE0 6 5 22 PE 220pF 4 3 22 SLCT SLCT 4 5 22 HDEN 2 1 22

-PPBUSY

C19 220pF FLOPPY HEADER 17X2

PPE

C20 220pF

1 1 PPSLCT

C21 220pF Intel Corporation

Embedded Intel Architecture Division 5000 W. Chandler Blvd. Chandler, AZ 85226-3699 THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT Designed By: Application Design-In Center (Folsom, CA) BEEN VERIFIED FOR MANUFACTURING AS AN END USER Title Intel® Pentium® III - Low Power / 440BX AGPset Reference Design

PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE Size Document Number Rev MISUSE OF THIS INFORMATION. C A0 Date:Monday, August 27, 2001 Sheet 25of 28 A B C D E A B C D E Flash BIOS / Port 80

V5_0

C196 0.1uF V5_0 Port 80

4 4 15,19,22,24 SD[15:0] SD[15:0] C200 V5_0 0.1uF V5_0 V5_0 TP16 TP14 TP12 TP10 R105 10K SA[19:0] TP TP TP TP U10 U12 U13 1 1 1 1 24 V5_0 14 C206 14 C205 C145 15,19,22,24 IOW# V5_0 V5_0 3 2 3 1 0.1uF 3 1 0.1uF 10uF 1 1A1 1B1 A V5_0 A V5_0 U9 SD4 4 5 2 2 R98 1A2 1B2 B B 2 17 SD5 7 6 13 13 I1/CLK O1 1A3 1B3 C C TP 3 18 SD6 8 9 12 12 I2 O2 1A4 1B4 D D 4 19 SD7 11 10 TP2 I3 O3 1A5 1B5 SA9 5 20 SA8 I4 O4 0 6 21 14 15 19,22,24 AEN I5 O5 2A1 2B1 SA0 7 23 SD0 17 16 I6 O6 2A2 2B2 SA1 9 24 SD1 18 19 SA2 I7 O7 SD2 2A3 2B3 10 25 21 20 SA3 I8 O8 SD3 2A4 2B4 11 26 22 23 10 10 SA4 I9 O9 2A5 2B5 RTDEC RTDEC 12 27 4 4 SA5 I10 O10 LFTDEC LFTDEC 13 1 8 8 SA6 I11 BEA GND GND 16 1 13 7 7 SA7 I12 NC BEB GND GND 8 5 LATCH 5 LATCH 22V10 NC NC 15 12 GND Expect All 0's except NC 22 QST3384 TIL311 SOCKET TIL311 SOCKET SA7=1 for P80 Decode Standard Stuff Option 1 1 1 1

3 TP TP TP TP 3 TP6 TP7 TP8 TP9

V5_0 Flash BIOS +12V 2 J21 2 1x3 1 3

15,19,22,24 SA[19:0] 2 C130 0.1uF

U11 XD[7:0] 19 21 SA0 A0 20 25 SA1 A1 DQ0 XD0 19 26 SA2 A2 DQ1 XD1 18 27 SA3 A3 DQ2 XD2 17 28 SA4 A4 DQ3 XD3 16 32 SA5 A5 DQ4 XD4 15 33 SA6 A6 DQ5 XD5 SA7 14 A7 DQ6 34 XD6 SA8 8 35 XD7 A8 DQ7 V5_0 SA9 7 A9 SA10 36 A10 VPP 11 SA11 6 A11 SA12 5 A12 VCC 31 SA13 4 A13 VCC 30 SA14 3 39 C208 A14 GND 0.1uF SA15 2 A15 GND 23 SA16 1 A16 SA17 40 A17

NC 12 SA18 15,19,24 MEMW# 9 WE# NC 13 15,19,24 MEMR# 24 OE# NC 37 20 BIOSCS# 22 CE# NC 38 10 RP# 1 1

C131 28F002BC 0.1uF or 28F004B5 Intel Corporation Embedded Intel Architecture Division +12V 5000 W. Chandler Blvd. Chandler, AZ 85226-3699 Designed By: Application Design-In Center (Folsom, CA) 2 Title 1 3 PWROK5 27 Intel® Pentium® III - Low Power / 440BX AGPset Reference Design J22 THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT Size Document Number Rev HDR3 BEEN VERIFIED FOR MANUFACTURING AS AN END USER C A0 Date:Monday, August 27, 2001 Sheet 26of 28 A B C PRODUCT. INTEL IS NOT RESPONSIBLED FOR THE E MISUSE OF THIS INFORMATION. A B C D E ATX Power Connector Power Indicators V5_0 V3_3 Place at ATX Connector -12V

R10 R8 220 124 C76 C69 C83 0.1uF 220uF 220uF

Note Cap Direction 4 Place at ATX Connector +12V 1 2 1 2 4 IN IN

D2 NC D1 NC LGS260-DO LGS260-DO J11 C102 C110 C98 C41 C27

0.1uF 220uF OUT 470pF OUT 470pF 11 V3_3 V3_3 1 220uF 12 -12V V3_3 2 13 GND GND 3 3 3 14 PS_ON V5_0 4 15 GND GND 5 16 6 2 GND V5_0 17 GND GND 7 V5_0 20 PWRON# 1 3 18 -5V PW_OK 8 19 V5_0 5VSB 9 J20 20 V5_0 +12V 10 Note: Add screen marking for V5_0 LED, V3_3 LED JUMP3

ATX POW CONN 14 V5_0 U25B Open Collector -5V 8 DBRESET 3 4 Place at ATX Connector R128 R53 4.7K 74ACT05 10K 7 C97 C88 C89 0.1uF 100uF 100uF S2

Note Cap Direction RESET SWITCH C138 C141 10uF 0.01uF V3.3SUS

3 V5_0 3

R127 PS_OK 10K 14 U22B U21C 14 U25C U24A Place at ATX Connector Place at ATX Connector 4 6 5 6 5 6 1 2 PWROK V3_3 V5_0 9 CPUPWROK 5 6,20

74ALS00 74HCT14 74ACT05 74LCT14 7 7

PWROK5 26 C61 C72 C58 C96 C84 C109 0.1uF 100uF 100uF 0.1uF 100uF 100uF PS_OK = OR of PW_OK,-DBRESET,RESET SWITCH V3.3SUS

V3.3SUS V5_0

14 U24B S1 14 3 4 PWRBTN# 20 U25D

POWER SWITCH 9 8 H_PWROK 4 R56 74LCT14 TP18 V3.3SUS 10K 7 C142 74ACT05 TP

0.1uF 7 V3.3SUS 1

U24C 14 U24D 14 U23 R57 V5_0 6 5 8 9 2 3 2 20 RSMRST# Out In 2 4 OutTab 2.7K 74LCT14 74LCT14

7 7 C153 C152 C154 J12 10uF 47uF 47uF 1 Adj/GND 1 1 LT117-3.3

2 2

3 3 1 TP

TP1

AMP173981-3

1 1

Intel Corporation

Embedded Intel Architecture Division 5000 W. Chandler Blvd. Chandler, AZ 85226-3699 THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT Designed By: Application Design-In Center (Folsom, CA) BEEN VERIFIED FOR MANUFACTURING AS AN END USER Title Intel® Pentium® III - Low Power / 440BX AGPset Reference Design

PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE Size Document Number Rev MISUSE OF THIS INFORMATION. C A0 Date:Monday, August 27, 2001 Sheet 27of 28 A B C D E A B C D E Unused Devices

4 4

V3.3SUS

V5_0 V5_0 14 4

5 6

14 U2C 14 U21D

5 6 7 U15B 9 8 74LVC125

74AS07 7

74HCT14 14 7 U2D 14 10 14 U21E 9 8

11 10 9 8 74AS07 7 14 74HCT14 U2E 7 7 U15C 11 10 74LVC125 14 U21F

13 12 74AS07

3 7 3 14 U2F

Make these connections 74HCT14 14 13 Cutable 7 13 12 12 11 74AS07 Make these connections 7 Make these connections Cutable 7 U15D Cutable 74LVC125

V3.3SUS

14 U24F V5_0

13 12 V5_0

74LCT14 7

2 2 Make these connections 14 Cutable U22C 9 8 10

74ALS00 14 U25E 7 11 10 14 U22D 12 11 74ACT05

13 7

74ALS00 14 U25F 7 Make these connections 13 12 Cutable 74ACT05 Make these connections 7 Cutable

1 1

Intel Corporation

Embedded Intel Architecture Division 5000 W. Chandler Blvd. Chandler, AZ 85226-3699 THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT Designed By: Application Design-In Center (Folsom, CA) Title BEEN VERIFIED FOR MANUFACTURING AS AN END USER Intel® Pentium® III - Low Power / 440BX AGPset Reference Design Size Document Number Rev PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE C A0

MISUSE OF THIS INFORMATION. Date:Monday, August 27, 2001 Sheet 28of 28 A B C D E Intel® Pentium® III Processor – Low Power/440BX AGPset

Appendix C PLD Code Listing

The code listing below is for the 22V10 PLD.

TITLE 22V10 PORT 80 ADDRESS DECODER / FLASH DECODE PATTERN 1 REVISION B AUTHOR CHRIS BANYAI COMPANY INTEL CORPORATION DATE 10/1/97

OPTIONS SECURITY = OFF

; ( part was 22V10FN before conversion ) CHIP P80B iPLD22V10N

PIN 19 IOWR_BAR PIN 3 AEN PIN [6:7] SA[0:1] PIN [9:13] SA[2:6] PIN 16 SA7 PIN [5:4] SA[8:9] PIN [26:23] SA[19:16] PIN [21:20] SA[15:14] PIN 2 SEL

PIN 18 /CS_BAR PIN 17 /CS_DOC PIN 27 OX

EQUATIONS CS_BAR = /IOWR_BAR * /AEN * /SA0 * /SA1 * /SA2 * /SA3 * /SA4 * /SA5 * /SA6 * SA7 * /SA8 * /SA9 CS_BAR.TRST = VCC

CS_DOC = /SEL * /AEN * SA19 * SA18 * /SA17 * /SA16 * SA15 * /SA14 + SEL * /AEN * SA19 * SA18 * /SA17 * SA16 * /SA15 * /SA14 CS_DOC.TRST = VCC

OX = /IOWR_BAR OX.TRST = VCC

SIMULATION

SETF /AEN /SA0 /SA1 /SA2 /SA3 /SA4 /SA5 /SA6 /SA7 /SA8 /SA9 IOWR_BAR SETF SA7 IOWR_BAR SETF /IOWR_BAR SETF IOWR_BAR SETF AEN /IOWR_BAR SETF /AEN

Design Guide 155 Intel® Pentium® III Processor – Low Power/440BX AGPset

SETF IOWR_BAR SETF SA0 /IOWR_BAR SETF /SA0 /IOWR_BAR SETF IOWR_BAR SETF /SA0 /SA1 /SA2 /SA3 /SA4 /SA5 /SA6 /SA7 /SA8 /SA9 SETF /SA19 /SA18 /SA17 /SA16 /SA15 /SA14 SETF /SEL SETF SA19 SA18 /SA17 /SA16 SA15 /SA14 SETF /SEL SETF /AEN SETF /SA19 SETF SA19 SETF /SA18 SETF SA18 SETF SA17 SETF /SA17 SETF SA16 SETF /SA16 SETF /SA15 SETF SA15 SETF SA14 SETF /SA14 SETF /SEL SETF SA19 SA18 /SA17 SA16 /SA15 /SA14 SETF /SEL SETF /AEN SETF SEL SETF /SA19 SETF SA19 SETF /SA18 SETF SA18 SETF SA17 SETF /SA17 SETF /SA16 SETF SA16 SETF SA15 SETF /SA15 SETF SA14 SETF /SA14 SETF /SEL

156 Design Guide