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Pentium III Processor Power Distribution Guidelines

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Pentium III Processor Power Distribution Guidelines Pentium® III Processor Power Distribution Guidelines Application Note April 1999 Order Number: 245085-001 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Pentium® III processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © Intel Corporation, 1999 *Third-party brands and names are the property of their respective owners. Application Note Pentium® III Processor Power Distribution Guidelines Contents 1.0 Introduction ..................................................................................................................7 1.1 Terminology...........................................................................................................7 1.2 References ............................................................................................................8 2.0 Typical Power Distribution.....................................................................................8 3.0 Pentium® III Processor Power Requirements ..............................................10 3.1 Voltage Tolerance ...............................................................................................10 3.2 Multiple Voltages.................................................................................................11 3.3 Voltage Sequencing ............................................................................................11 3.3.1 Non-AGTL+ Signals ...............................................................................14 3.3.2 AGTL+ Signals .......................................................................................14 3.3.3 Memory Side Signals .............................................................................14 3.3.4 PCI Side Signals ....................................................................................14 3.3.5 Clock Input .............................................................................................14 4.0 Meeting the Pentium® III Processor Power Requirements .....................15 4.1 Voltage Budgeting ...............................................................................................15 4.2 Supplying Power .................................................................................................15 4.2.1 Local DC-to-DC Converters vs. Centralized Power Supply ...................17 4.2.2 AC vs. DC Input Voltage ........................................................................17 4.2.3 Linear Regulators vs. Switching Regulators...........................................17 4.3 Decoupling Technologies and Transient Response............................................18 4.3.1 Bulk Capacitance ...................................................................................20 4.3.2 High Frequency Decoupling ...................................................................22 4.4 Power Planes or Islands......................................................................................24 4.4.1 Location of High Frequency Decoupling ................................................26 4.4.2 Location of Bulk Decoupling...................................................................27 4.4.3 Impedance And Emission Effects Of Power Islands ..............................27 5.0 The AGTL+ Bus Power Requirements.............................................................27 5.1 Tolerance ............................................................................................................28 5.2 Reference Voltage...............................................................................................28 6.0 Meeting the AGTL+ Power Requirements......................................................29 6.1 Generating VTT....................................................................................................29 6.2 Distributing VTT ...................................................................................................29 6.3 Generating and Distributing VREF .......................................................................30 6.3.1 Distributing VREF Or VTT ........................................................................32 7.0 Recommendations...................................................................................................32 7.1 VCC_L2...............................................................................................................32 7.2 VCC_CORE ........................................................................................................32 7.2.1 The Main Power Supply .........................................................................33 7.3 VTT ......................................................................................................................34 7.3.1 Termination Resistors ............................................................................35 7.4 VREF ....................................................................................................................35 Application Note 3 Pentium® III Processor Power Distribution Guidelines 7.5 Component Models ............................................................................................. 36 8.0 Measuring Transients............................................................................................. 37 9.0 Existing Technology for a Pentium® III Processor System Design .... 37 9.1 Solutions for VCC_CORE ................................................................................... 37 9.2 Linear Regulators for VTT.................................................................................... 37 9.3 Termination Resistors ......................................................................................... 37 10.0 Pentium® III Processor Power Distribution Network Modeling............. 38 11.0 Right Angle Connector Power Delivery Considerations ......................... 40 Figures 1 Ideal Pentium® III Processor Power Supply Scheme............................................ 8 2 Physical Power Distribution of a Pentium® III System .......................................... 9 3 Detailed Power Distribution Model ........................................................................ 9 4Pentium® III Processor Substrate ....................................................................... 11 5 SC242 Connector Power Pins, Top View (Through the SC242 Connector) ....... 12 6 Voltage Sequencing Example ............................................................................. 13 7 Non-AGTL+ ESD Diodes .................................................................................... 13 8 AGTL+ ESD Diodes ............................................................................................13 9 System Design Model ......................................................................................... 16 10 Remote Sense .................................................................................................... 16 11 Location of Capacitance in a Power Model with a DC-to-DC Converter............. 19 12 Effect of Transients on a Power Supply .............................................................. 20 13 ESR Cylindrical Capacitor................................................................................... 20 14 Capacitor Model .................................................................................................. 20 15 ESR Required for Various Current Demands ..................................................... 21 16 Capacitance Required vs. ESR at 8.5A, 60 mV DV, and 30 µs Dt .....................22 17 Baseboard Layer Definition................................................................................. 24 18 Pentium® III Processor VCC_CORE Voltage Island ........................................... 25 19 Pentium® III Processor VCC_L2 Voltage Island ................................................. 26 20 Capacitor Pad and Via Layouts........................................................................... 28 21 Pentium III Processor VTT/VREF Voltage Island .................................................. 30 22 A Simple Circuit
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