8Th Generation Intel® Core™ Processor Datasheet, Vol. 1
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8th and 9th Generation Intel® Core™ Processor Families and Intel® Xeon® E Processor Family Datasheet, Volume 1 of 2 Supporting 8th Generation Intel® Core™ Processor Families, Intel® Pentium® Processors, Intel® Celeron® Processors for U/H/S Platforms, formerly known as Coffee Lake. Supporting 9th Generation Intel® Core™ Processor Families, Processors for S Platforms, formerly known as Coffee Lake Refresh For Datasheet Volume 2, Refer to Doc ID: 337345 October 2018 Revision 002 Document Number: 337344-002 Legal Lines and Disclaimers You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. 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All rights reserved. 2 Datasheet, Volume 1 of 2 Contents 1 Introduction ............................................................................................................ 10 1.1 Processor Volatility Statement............................................................................. 12 1.2 Supported Technologies ..................................................................................... 12 1.3 Power Management Support ............................................................................... 13 1.3.1 Processor Core Power Management........................................................... 13 1.3.2 System Power Management ..................................................................... 13 1.3.3 Memory Controller Power Management...................................................... 14 1.3.4 Processor Graphics Power Management ..................................................... 14 1.4 Thermal Management Support ............................................................................ 14 1.5 Package Support ............................................................................................... 15 1.6 Ballout Information............................................................................................ 15 1.7 Processor Testability .......................................................................................... 15 1.8 Operation System Support ................................................................................. 15 1.9 Terminology ..................................................................................................... 15 1.10 Related Documents............................................................................................ 18 2 Interfaces................................................................................................................ 19 2.1 System Memory Interface................................................................................... 19 2.1.1 System Memory Technology Supported ..................................................... 19 2.1.2 System Memory Timing Support............................................................... 22 2.1.3 System Memory Organization Modes......................................................... 23 2.1.4 System Memory Frequency...................................................................... 24 2.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)..........25 2.1.6 Data Scrambling .................................................................................... 25 2.1.7 ECC H-Matrix Syndrome Codes................................................................. 25 2.1.8 DDR I/O Interleaving .............................................................................. 26 2.1.9 Data Swapping....................................................................................... 27 2.1.10 DRAM Clock Generation........................................................................... 27 2.1.11 DRAM Reference Voltage Generation ......................................................... 28 2.1.12 Data Swizzling ....................................................................................... 28 2.2 PCI Express* Graphics Interface (PEG)................................................................. 28 2.2.1 PCI Express* Support ............................................................................. 28 2.2.2 PCI Express* Architecture ....................................................................... 30 2.2.3 PCI Express* Configuration Mechanism ..................................................... 31 2.2.4 PCI Express* Equalization Methodology ..................................................... 31 2.3 Direct Media Interface (DMI)............................................................................... 32 2.3.1 DMI Lane Reversal and Polarity Inversion .................................................. 32 2.3.2 DMI Error Flow....................................................................................... 33 2.3.3 DMI Link Down ...................................................................................... 33 2.4 Processor Graphics ............................................................................................ 34 2.4.1 API Support (Windows*) ......................................................................... 34 2.4.2 Media Support (Intel® QuickSync and Clear Video Technology HD) ...............34 2.4.3 Switchable/Hybrid Graphics ..................................................................... 37 2.4.4 Gen 9 LP Video Analytics ......................................................................... 38 2.4.5 Gen 9 LP (9th Generation Low Power) Block Diagram .................................. 39 2.4.6 GT2/3 Graphic Frequency ........................................................................ 39 2.5 Display Interfaces ............................................................................................. 40 2.5.1 DDI Configuration .................................................................................. 40 2.5.2 eDP* Bifurcation .................................................................................... 40 2.5.3 Display Technologies............................................................................... 43 2.5.4 DisplayPort* .......................................................................................... 45 Datasheet, Volume 1 of 2 3 2.5.5 High-Definition Multimedia Interface (HDMI*)............................................ 46 2.5.6 Digital Video Interface (DVI) ................................................................... 47 2.5.7 embedded DisplayPort* (eDP*) ............................................................... 47 2.5.8 Integrated Audio.................................................................................... 47 2.5.9 Multiple Display Configurations (Dual Channel DDR) ................................... 48 2.5.10 Multiple Display Configurations (Single Channel DDR) ................................. 49 2.5.11 High-bandwidth Digital Content Protection (HDCP) ..................................... 49 2.5.12 Display Link Data Rate Support................................................................ 50 2.5.13 Display Bit Per Pixel (BPP) Support........................................................... 51 2.5.14 Display Resolution per Link Width ............................................................ 51 2.6 Platform Environmental Control Interface (PECI) ................................................... 51 2.6.1 PECI Bus Architecture............................................................................. 51 3 Technologies........................................................................................................... 54 3.1 Intel® Virtualization Technology (Intel® VT) ......................................................... 54 3.1.1 Intel® Virtualization Technology (Intel® VT) for IA-32, Intel® 64 and