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Intel Pentium Processor Users Manual Volume 1 1993

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~ • INTEL. ~~ " Founded in 1968 to pursue the integration of large numbers of transistors onto tiny silicon chips, Intel's history has been marked by a remarkable number of scientific breakthroughs and innovations. In 1971, Intel introduced the 4004, the first microprocessor. Containing 2300 transistors, this first commercially available computer-on-a-chip is primitive compared with today's million-plus transistor products. Innovations such as the microprocessor, the erasable programmable read-only memory (EPROM) and the dynamic random access memory (DRAM) revolutionized electronics by making integrated circuits the mainstay of both consumer and business computing products. Over the last two-and-a-half decades, Intel's business has evolved and today the company's focus is on delivering an extensive line of component, module and system-level building block products to the computer industry. The company's product line covers a broad spectrum, and includes microprocessors, flash memory, microcontrollers, a broad line of PC enhancement and local area network products, multimedia technology products, and massively parallel supercomputers. Intel's 32-bit X86 architecture, represented by the Inte1386™ and Inte1486™ microprocessor families, is the de facto standard of modem business computing in millions of PCs worldwide. Intel has over 26,000 employees located in offices and manufacturing facilities around the world. Today, Intel is the largest semiconductor company in the world. LITERATURE To order Intel literature or obtain literature pricing information in the U.S. and Canada call or write Intel Literature Sales. In Europe and other international locations, please contact your local sales office or distributor. INTEL LITERATURE SALES In the U.S. and Canada P.O. Box 7641 call toll free Mt. Prospect, IL 60056-7641 (BOO) 548-4725 This 800 number is for external customers only. CURRENT HANDBOOKS Product line handbooks contain data sheets, application notes, article reprints, and other design information. All handbooks can be ordered individually, and most are available in a pre-packaged set in the U.S. and Canada. Intel Title Order Number ISBN SET OF TWELVE HANDBOOKS 231003 N/A (Available in U.S. and Canada) CONTENTS LISTED BELOW FOR INDIVIDUAL ORDERING: CONNECTIVITY 231658 1-55512-174-8 EMBEDDED APPLICATIONS (1993/94) 270648 1-55512-179-9 EMBEDDED MICROCONTROLLERS & PROCESSORS 270645 1-55512-176-4 (2 volume set) MEMORY PRODUCTS 210830 1-55512-172-1 MICROCOMPUTER PRODUCTS 280407 1-55512-173-X MICROPROCESSORS (2 volume set) 230843 1-55512-169-1 MOBILE COMPUTER PRODUCTS 241420 1-55512-186-1 i750®, iB60™, i960® PROCESSORS AND RELATED PRODUCTS 272084 1-55512-185-3 PACKAGING 240800 1-55512-182-9 PERIPHERAL COMPONENTS 296467 1-55512-181-0 PRODUCT OVERVIEW 210846 NlA (A guide to Intel Architectures and Applications) PROGRAMMABLE LOGIC 296083 1-55512-180-2 ADDITIONAL LITERATURE: (Not included in handbook set) AUTOMOTIVE 231792 1-55512-125-X COMPONENTS QUALITY/RELIABILITY 210997 1-55512-132-2 CUSTOMER LITERATURE GUIDE 210620 N/A INTERNATIONAL LITERATURE GUIDE EOO029 N/A (Available in Europe only) MILITARY AND SPECIAL PRODUCTS (2 volume set) 210461 1-55512-189-6 SYSTEMS QUALITY/RELIABILITY 231762 1-55512-091-9 HANDBOOK DIRECTORY 241197 N/A (Index of all data sheets contained in the handbooks) LlTINCOV-W/111193 inte!® Pentium™ Processor User's Manual Volume 1: Pentium™ Processor Data Book NOTE: The Pentium™ Processor User's Manual consists of three books: Pentium™ Processor Data Book, Order Number 241428; the 82496 Cache Controller and 82491 Cache SRAM Data Book, Order Number 241429; and the Architecture and Programming Manual, Order Number 241430. Please refer to all three volumes when evaluating your design needs. 1993 I Intel Corporation makes no warranty for the use of Its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contamed herein. Intel retains the right to make changes to these specifications at any time, without notice. Contact your local sales office to obtain the latest specifications before placing your ~rder The following are trademarks of Intel Corporation and may only be used to identify Intel products: 376™ i860™ MCS® Above™ i960® Media MailTM ActionMedia® Intel287™ NetPort® BITBUSTM Intel386™ NetSentry ™ Code Builder™ Intel387™ NetSight™ DeskWare™ Intel486™ OpenNET'M Digital Studio™ Intel487™ OverDrive™ DVI® Intel® Paragon™ EtherExpress ™ intel inside® Pentium™ ETOXTM Intellec® ProSolver™ ExCA'M iPSC® RapidCADTM Exchange and Go ™ iRMX® READV-LAN'M FaxBACK® iSBC® Reference Point® Grand Chalienge™ iSBXTM RMXl80™ i® iWARpTM RxServer™ ICETM LANDeskTM SallSFAXtion® iCOMpTM LANPrint® SmartWire™ iLBXTM LANProtect™ Snapln 386™ Inboard™ LANSelect® Storage Broker™ Indeo™ LANShell® Storage Express ™ 1287™ LANSlght™ SugarCube™ i386™ LANSpace® The Computer Inslde™ i387™ LANSpool® Token Express ™ i486™ MAPNET'M Visual Edge ™ 1487™ Matched™ WVPIWYF® i750® MDS is an ordering code only and is not used as a product name or trademark. MDS is a registered trademark of Mohawk Data Sciences Corporation. CHMOS and HMOS are patented processes of Intel Corp. Intel Corporation and Intel's FASTPATH are not affiliated with Kinetics, adivision of Excelan, Inc. or its FASTPATH trade­ mark or products. MS-DOS and Windows are trademarks of Microsoft Corp. NeXTstep is a registered trademark of NeXT Computers, Inc. OSI2 IS a registered trademark of IBM Corp. UNIX IS a registered trademark of UNIX System Laboratories, Inc. ' Addition~1 copies of this manual or other Intel literature may be obtained from: Intel Corporation Literature Sales P.O. Box 7641 Mt. Prospect, IL 60056-7641 © INTEL CORPORATION 1993 CG·010493 PENTIUMTM PROCESSOR • Binary Compatible with Large • 273-Pin Grid Array Package Software Base • BiCMOS Silicon Technology MS-DOS, Windows, OS/2, UNIX SVR4, NeXTstep 486, Solaris 2.0 • Increased Page Size 4M for Increased TLB Hit Rate • 32-Bit Microprocessor 32-Bit Addressing • Multi-Processor Support 64-Bit Data Bus Multiprocessor Instructions Support for Second Level Cache • Superscalar architecture Two pipelined integer units • Internal Error Detection Capable of under one Clock per Functional Redundancy Checking Instruction Built in Self Test Pipelined Floating Point Unit Parity testing and checking • Separate Code and Data Caches • IEEE 1149.1 Boundary Scan 8K Code, 8K Write Back Data Compatibility 2-way 32-byte Line Size • Performance Monitoring Software Transparent Counts Occurrence of Internal MESI Cache Consistency Events Protocol Traces Execution through • Advanced Design Features Pipelines Branch Prediction Virtual Mode Extensions The Pentium processor provides the new generation of power for high-end workstations and servers. The Pentium processor is compatible with the entire installed base of applications for DOS, Windows, OS/2, and UNIX. The Pentium processor's superscalar architecture can execute two instructions per clock cycle. Branch Prediction and separate caches also increase performance. The pipelined floating point unit of the Pentium processor delivers workstation level performance. Separate code and data caches reduce cache conflicts while remaining software transparent. The Pentium processor has 3.1 million transistors and is built on Intel's .8 Micron BiCMOS silicon technology. I iii I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I TABLE OF CONTENTS CHAPTER 1 PINOUT Page 1.1. PINOUT AND PIN DESCRIPTIONS ............................................................................. 1-1 1.1.1. Pentium™ Processor Pinout.. .................................................................................... 1-1 1.2. DESIGN NOTES ........................................................................................................... 1-6 1.3. QUICK PIN REFERENCE ............................................................................................. 1-6 1.4. PIN REFERENCE TABLES ........................................................................................ 1-14 1.5. PIN GROUPING ACCORDING TO FUNCTION ......................................................... 1-17 1.6. OUTPUT PIN GROUPING ACCORDING TO WHEN DRIVEN ................................... 1-18 CHAPTER 2 MICROPROCESSOR ARCHITECTURE OVERVIEW CHAPTER 3 COMPONENT OPERATION 3.1. PIPELINE AND INSTRUCTION FLOW ......................................................................... 3-1 3.1.1. Pentium Processor Pipeline Description and Improvements .................................... 3-2 3.1.1.1. INSTRUCTION PREFETCH ................................................................................. 3-3 3.1.2. Instruction Pairing Rules ........................................................................................... 3-4 3.2. BRANCH PREDICTION ................................................................................................ 3-5 3.3. WRITE BUFFERS AND MEMORY ORDERING ........................................................... 3-6 3.3.1. External Event Synchronization ................................................................................ 3-6 3.3.2. Serializing Operations ............................................................................................... 3-7 3.3.3. Linefill and Writeback Buffers ..................................................................................
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