3.2 Combinational Logic

3.2 Combinational logic

Components of microprocessors 3.2.1 Adder and subtractor

2 Ripple Carry Adder (RCA)

Truth table of full adder (FA) A B Cin Cout S 00000 00101 01001 01110 10001 10110 11010 11111

A+B+Cin

3 Full Adder

Truth table Logic

A B Cin Cout S 00000A + B B 00101 01001 01110CI A + B 10001 10110 11010B 11111A + B

If (A xor B) Cout = Cin; A+B+Cin = Odd number else Cout = B; 4 Subtractor

F  A  B  A  (B)

0 -1 1 Complement on two 000 111 001 1. Bit-wise inversion -2 110 010 2 2. Addition of 1 101 011 -3 100 3 (A carry input is used.) -4 3bit two's complement

5 Adder-subtractor

(OPCODE)

I F 0 A + B 1 A - B

6 Arithmetic logic unit (ALU) SUN SPARC Cout A31 F31

B31 Adder Full

A30 F30

B30 Adder Full

A1 Subtraction instruction F1 I0 1

B1 Adder Full I/O Data Data I1 0 register RAM ROM I2 0 A0 F0 Cin 1 B0 Multiplier Full Adder B

ALU (算術論理 A Z ALU I0 演算ユニット) I1 SEL I2 Accumulator Cin register 32bit ALU MUX 7 3.2.2 Decoder

8 Function of binary decoder

D3 A 1-of-N binary decoder asserts one of its n output bits for every integer input value. I1 D2 There are some types of decoder, for I0 D1 example, a BCD to decimal decoder, D0 demultiplexer and code translators.

Truth table of 2 oto4 line decoder Disjunctive canonical form I1 I0 Line D3 D2 D1 D0 D0  I1I0 0 0 D0 0 0 0 1 D1  I1I0 0 1 D1 0 0 1 0 1 0 D2 0 1 0 0 D2  I1I0 1 1 D3 1 0 0 0 D3  I1I0 9 Circuit of decoder

I1 I0 D0I1 ·I0 I1I0 D1I1 ·I0I1I0 D2I1∙I0 I1 I0 D3I1∙I0I1 I0 D0

10 Usage example of decoder

Memory cell array ・・・・

A0 Cache A1 memory cell

Memory Row decoder

・・・・ Column decoder Decoder I1 I0 A2 A3

SRAM cell D0 Wi

D2 Di Di

D3 Intel Mobile Pentium III 11 3.2.3 Shifter

12 Uses of shifter • Shift operation – Constant multiplication (= Shift and addition), floating- point arithmetic n n-1 0 Example： a * b = a * (bn・2 + bn-1・2 +・・・+ b0・2 ) = bn・ (a<

• Circuit system – Barrel shifter (See next slide.) – Logarithmic shifter Algorithms and circuits of other arithmetic operations (multiplication, division, discrimination, modulo) will be covered in the lectures of integrated circuit C and D. 13 Barrel shifter

Rhe n-ch MOSFET switch matrix (The p-ch MOSFET switch matrix is omitted.) Truth table of right shift operation A3 B3 Sh3 Sh2 Sh1 Sh0 B3 B2 B1 B0 A2 0 0 0 1 A3 A2 A1 A0 B2 0 0 1 0 A3 A3 A2 A1 0 1 0 0 A3 A3 A3 A2 A1 1 0 0 0 A3 A3 A3 A3 B1

The blue A3 is a sign-extended value. A0 B0

Buffer

I1 I0 DECODER

14 Sign extension (符号拡張)

Inside the circle: Decimal Outside the circle: Binary 000 000 000 111 111 111 0 001 -1 1 000 001 111 110 2 010 110 -2 000 010 111 101 3 -3 011 000 011 111 100 101 -4 100

Extended 6bit complement 3bit complement Extended 6bit complement (Negative number) (Positive number)

The value of MSB is added as the upper bits. 15 3.2.4 Encoder

16 Function of encoder

If there are 2n input lines, and at most D3 only one of them will ever be high, the D2 P1 binary code of this 'hot' line is produced D1 P0 on the n-bit output lines. D0

Truth table D3 D2 D1 D0 P1 P0 0 0 0 0 (0 0 ) DC DC DC 1 1 1 DC DC 1 0 1 0 DC 1 0 0 0 1 1 0 0 0 0 0 17 Circuit of encoder

P1  D0  D0D1 D3 不要  D0(1 D1)  D0D1 D2 P0  D0  D0D1 D0D1  D0  (D0  D0)D1 D1 P1 D0  D0  D1 P0  D0  D0D1D2  D0  D0(D1D2)  D0(1 D1D2)  D0(D1D2)  D0  (D0  D0)(D1D2)  D0  D1D2 18 Usage example of encoder

ref +V Encoder Latch Comparator Flash ADC R/2

Vin 0.125V

R 0.875 1 Vref = 1V 0.25V Vin = 0V R 0.625 1 0.25V R 0.375 1 0.25V Lecroy 10GS/s ADC 1 0.125 Binary Data R 0.25V -0.125 0 R Vin (V) Thermometer Code Binary Code 0.25V ~ -0.875 1 1 1 1 1 1 1 1 (1) 0 0 0 R -0.375 0 -0.875 ~ -0.625 0 1 1 1 1 1 1 1 1 1 1 0.25V -0.625 ~ -0.375 0 0 1 1 1 1 1 1 1 1 0 R -0.625 0 -0.375 ~ -0.125 0 0 0 1 1 1 1 1 1 0 1 -0.125 ~ 0.125 0 0 0 0 1 1 1 1 1 0 0 0.25V 0 0.125 ~ 0.375 0 0 0 0 0 1 1 1 0 1 1 R/2 -0.875 0.375 ~ 0.625 0 0 0 0 0 0 1 1 0 1 0 Encode 0.125V 0.625 ~ 0.875 0 0 0 0 0 0 0 1 0 0 1 0.875 ~ 0 0 0 0 0 0 0 0 0 0 0 －Vref SYS_CLK Clocking Circuit 19