US0071900.52B2

(12) United States Patent (10) Patent No.: US 7,190,052 B2 Lindgren (45) Date of Patent: Mar. 13, 2007

(54) SEMICONDUCTOR DEVICES WITH OXIDE 5,516,721 A 5/1996 Galli et al. COATINGS SELECTIVELY POSITONED 5,683,946 A 1 1/1997 Lu et al. OVER EXPOSED FEATURES INCLUDING 5,776,829 A 7/1998 Homma et al. SEMCONDUCTOR MATERAL 6,022,814 A 2/2000 Mikoshiba et al. 6,045,877 A 4/2000 Gleason et al. (75) Inventor: Joseph T. Lindgren, Boise, ID (US) 6,174,8246,130,116 AB1 10/20001/2001 MichaelSmith et etal. al. 6, 197,110 B1 3/2001 Lee et al. (73) Assignee: Micron Technology, Inc., Boise, ID 6,251,753 B1 6/2001 Yeh et al. (US) (*) Notice: Subject to any disclaimer, the term of this (Continued) patent is extended or adjusted under 35 OTHER PUBLICATIONS U.S.C. 154(b) by 0 days. Schreiber, S.J. et al., “Low Temperature Deposition of Microcrystal line For Thin Film Transistors,' CUED Electronic Devices (21) Appl. No.: 10/454.256 and Materials Group, http://www2.eng.cam.ac.uk/~www-edm/ (22) Filed: Jun. 3, 2003 projects/lowtempdepf1.htm, prior to Sep. 2000, 2 pages. e as (Continued) (65) Prior Publication Data Primary Examiner T. N. Quach US 2004/OO33682 A1 Feb. 19, 2004 (74) Attorney, Agent, or Firm TraskBritt Related U.S. Application Data (57) ABSTRACT (62) Division of application No. 10/218.268, filed on Aug. 13, 2002, now Pat. No. 6,593,221. A semiconductor device structure includes a passivation layer through which only non-silicon-comprising structures (51) Int. Cl. are exposed. The semiconductor device structure is formed HOIL 2.3/58 (2006.01) by selectively forming the passivation layer on an exposed (52) U.S. Cl...... 257/632: 257/638; 257/758 silicon-comprising surface by exposing surfaces of the semi (58) Field of Classification Search ...... 257/632, conductor device to a liquid phase solution Supersaturated in 257/638,639, 649 . The exposure is conducted at Substantially See application file for complete search history. atmospheric temperature and pressure and achieves an effec tive passivation layer in an abbreviated time, and without (56) References Cited Subsequent heat treatment. A wafer that includes a back side U.S. PATENT DOCUMENTS coated with Such a passivation layer may be subjected to a high-speed electroless process for plating the bond pad with 4,599,792 A * 7/1986 Cade et al...... 438,454 a solder-enhancing material. The semiconductor device 5, 192,714 A * 3/1993 Suguro et al...... 438,631 5,256,593 A 10, 1993 Iwai structure may also include via holes and microvia holes with 5,365,112 A 11/1994 Oshima walls that are passivated. 5,395,645 A 3, 1995 Kodera et al. 5,429,956 A 7, 1995 Shell et al. 20 Claims, 4 Drawing Sheets

US 7,190,052 B2 Page 2

U.S. PATENT DOCUMENTS Niskanen, Antti J., “Liquid Phase Deposition of Silicon Dioxide.” http://.../Liquid Silicon Dioxide. 6,294,832 B1 9, 2001 Yeh et al. htm+liquid-phase--Silicon--Dioxide+deposition&hl=en&start=. 6,335,224 B1 1/2002 Peterson et al. 6,399.494 B1* 6/2002 Nagata ...... 438,682 prior to Nov. 2000, 2 pages.(Cache of http://www.hut.fi/Units/ 6,671,947 B2 1/2004 Bohr ...... 29,846 Electron/Projects2000/LiquidSiliconDioxide.htm). Yeh, Ching-Fa et al., “Properties of Silicon Exide Prepared by OTHER PUBLICATIONS Liquid-Phase Deposition.” Mar. 26, 1999, 1 page, http://www.aps. Niskanen, Sampo, “Development of Liquid Phase Deposition of org/meet/CCNT99/BAPS/abs/S8880001.html). Zirconium Oxide and Comparison to Silicon Dioxide.” http:// sampo.rdx.net/LPD/lpd.html, Nov. 19, 2000, 15 pages. * cited by examiner U.S. Patent Mar. 13, 2007 Sheet 1 of 4 US 7,190,052 B2 O N 8 12 2O f It S 16

28 12 FFEIt Fig. 1C

U.S. Patent Mar. 13, 2007 Sheet 2 of 4 US 7,190,052 B2

1O

30 12

Fig. 2B

12 31 = - A-17 N

Fig. 2C U.S. Patent Mar. 13, 2007 Sheet 3 of 4 US 7,190,052 B2

NICKEL RINSE PLATING RINSE SOLN.

56 Fig. 3 U.S. Patent Mar. 13, 2007 Sheet 4 of 4 US 7,190,052 B2

H2SiF6 H2SiF6 High Concentration High Concentration

SiO2 Dilution H2O

Filtration H2SiF6 Low Concentration

SiO2-saturated H2SiF6 SiO2

High Concentration

Filtration

H2O

SiO2-saturated SiO2-saturated H2SiF6 H2SiF6 Low Concentration Low Concentration

HBO3 HBO

SiO2-supersaturated SiO2-supersaturated H2SiF6 H2SiF6

Contact with Exposed Contact with Exposed Silicon or SiO2 at <50°C Silicon or SiO2 at <50°C to Deposit SiO2 to Deposit SiO2

Fig. 4 Fig. 5 US 7,190,052 B2 1. 2 SEMCONDUCTOR DEVICES WITH OXDE operating costs of oxidation furnaces are high. Furthermore, COATINGS SELECTIVELY POSITONED a problem, which must be considered in thermal oxidation, OVER EXPOSED FEATURES INCLUDING is the formation of Surface dislocations which may cause SEMCONDUCTOR MATERAL circuit problems. Another consideration relating to oxide growth is the CROSS-REFERENCE TO RELATED inability to adequately passivate the lateral walls of a small APPLICATION via hole (Such as a laser-formed microvia) of a multilayer device prior to deposition of a conductive material (Such as This application is a divisional of application Ser. No. tungsten) into the via hole. Present passivation methods for 10/218.268, filed Aug. 13, 2002, now U.S. Pat. No. 6.59, 10 insulating the lateral walls of such small-diameter holes tend 3221. to produce uneven coverage, sometimes leading to either short circuits between the conductive via and the semicon BACKGROUND OF THE INVENTION ductor or excessive filling of the via hole. In forming semiconductor devices, the electrically con 1. Field of the Invention 15 ductive bond pads on the active surface are grounded to the The present invention relates to methods for electrically back side of the wafer. Unless neutralized by a passivation isolating dielectric materials. More particularly, the inven layer, the wafer back side has a net positive (+) charge. tion pertains to methods for electrical isolation, i.e., passi Bond pad formation typically includes applying a copper Vation of exposed silicon Such as occurs on the back side of or aluminum base, then coating the base with another a semiconductor (SC) wafer comprising semiconductor material so that wire bonds or conductive structures, such as devices or dice of a DRAM, SRAM, or other semiconductor solder, may be secured to the bond pad. die configuration. The invention also pertains to passivation In the case of bond pads to which bond wires are to be of apparatus Such as carrier Substrates, interposer Substrates secured, copper is typically employed as the bond pad for flip-chip packaging, conductive interconnects for test material. As copper forms a “slippery' oxide that is difficult packages, and the like. 25 to remove with a wire bonding capillary, nickel and gold 2. Background of Related Art adhesion layers are typically used. As copper alone will not Silicon is a basic material from which a broad range of initiate the adhesion of nickel thereto, a palladium “strike'. semiconductor devices is composed. Silicon is a semicon or seed layer, is typically formed prior to conducting an ductor while its oxidation product, silicon dioxide, acts as a electroless nickel-plating process. dielectric (insulating) material. Thus, silicon dioxide is one 30 Efforts have been made to use more aggressive plating of the classical insulators used to electrically isolate silicon chemistries in order to speed the plating rate and create a from conductive , specific functional devices in elec higher density coating at lower cost. Such chemistries, e.g., tronic apparatus, and the atmosphere. Other insulators that palladium chloride in hydrochloric acid, greatly enhance the are used include a variety of organic and inorganic com plating rate and plate density. However, unless the wafer pounds. 35 back side is first passivated, copper pads which communi The manufacture of semiconductor devices is performed cate with the silicon Substrate (e.g., pads that communicate by forming a plurality of the functional devices on a wafer with active-device regions of transistors) and, thus, which and Subsequently separating each semiconductor device by may form a circuit directly through the silicon Substrate, cutting along a pattern of saw lines crisscrossing the wafer. may be attacked by the plating chemistry and dissolve in as The various processes for forming a semiconductor device 40 little as several minutes of exposure, resulting in damaged such as a DRAM or SRAM device may be generally pads with performance anomalies. In addition, bath chemi characterized as including crystal growth, bare wafer for cals will be inordinately consumed. The use of mation, Surface preparation, oxidation/nitridation, heat treat in the palladium electroless plating Solution may curb Such ment, patterning, layer deposition, doping, metallization, an attack of the bond pads to Some extent, but does not and packaging. Typically, each of these processes includes 45 completely resolve this problem. Once the palladium strike several Subprocesses. has been formed, nickel may be plated onto the copper and Layer deposition is generally performed by one of several palladium by way of electroless deposition processes, then processes, such as physical vapor deposition (PVD), chemi a gold layer may be formed by immersion plating processes. cal vapor deposition (CVD), Sputtering, and electron-beam Aluminum is typically used as the base metal for bond evaporation. In cases where the desired layer is to be an 50 pads that will receive solder balls or other discrete conduc oxide of the base material, e.g., silicon dioxide, another tive elements. As aluminum is not itself solderable, adhesion common method includes the direct thermal oxidation of the layers are typically deposited onto aluminum bond pads. existing silicon Surface. Although the processes by which Again, nickel is often used as such an adhesion layer. Nickel 'growth of a passivation layer on silicon by oxidizing the does not, however, adhere well to aluminum. A Zincating Surface are highly developed, they have certain limitations. 55 process, usually “double zinc. is typically used to facilitate First, the rate of formation significantly slows as the layer adhesion of electrolessly deposited nickel to aluminum. If thickness increases. Long times at high temperature are the back side of the silicon substrate upon which the bond generally required to form thick layers, such as field oxides, pads are carried is not adequately passivated, the Zincating Surface passivation layers, and some masking oxide layers. process may etch the aluminum bond pads or deposit large Secondly, the growth rate is a function of wafer orientation. 60 Zinc grains, which, in turn, adversely affects the Subse The <111> planes of a wafer have more silicon atoms than quently deposited nickel layer. <100> planes, thus leading to faster formation of a SiO, Moreover, in forming adhesion layers on both copper and layer. In addition, other factors affecting growth rates aluminum bond pads, if the back side of the silicon substrate include the types and concentrations of doping materials in is not sufficiently passivated, these nickel and gold layers the silicon and the presence of polysilicon or impurities. 65 may also be loosely deposited onto portions of the back side, Differential oxidation causes the resulting SiO layer to have which may result in the formation of particles in the plating a stepped surface. It should be noted that the initial costs and baths, shortening the lives thereof and creating potential US 7,190,052 B2 3 4 problems for downstream processes which are particle The present invention is directed to the application of a sensitive, Such as Subsequent tape and probe processes. silicon dioxide layer on an exposed silicon layer. The In the current state of the art, the general approach is to deposition is selective to silicon/silicon dioxide and may be continue to use the more benign electroless plating method performed by exposure to a liquid phase composition in a despite its overall cost. bath at room temperature or a temperature somewhat above In an alternative approach, a back side coating Such as a room temperature, e.g., up to about 50° C. The liquid phase photoresist material is first applied to the wafer back side to composition is Supersaturated in silicon dioxide. The silicon dioxide deposition rate is not self-limiting, that is, it does not cover the wafer's Substrate material, e.g., silicon or germa depend upon the layer thickness. The deposition rate may be nium, and provide protection from a more aggressive plating 10 chemistry. This method has further disadvantages in that the readily controlled to provide repeatedly uniform layer thick wafer is required to be removed from its work surface and ness. Thus, for example, the method may be used to passi inverted for resist application by a spin-on technique. Inver vate the back side of a wafer or other semiconductor sion and spin-on deposition require extra steps and equip substrate without inverting the wafer or substrate. The ment, are time consuming, and require forcibly clamped 15 method is specific to the base Substrate, e.g., silicon and its placement of the wafer's active surface on the flat surface of oxide. Further exclusion of oxide from other surfaces may a vacuum hold-down tool, sometimes leading to physical be assured by, for example, covering such Surfaces with damage to the semiconductor devices being formed on the tape. Any silicon dioxide pre-existing on the silicon Surface wafer. may be first removed or, alternatively, left in place for oxide In U.S. Pat. No. 6,022,814 of Mikoshiba et al., a method deposit thereover. for forming a silicon dioxide layer is presented which In one embodiment of the invention, a silicon wafer is includes the spin-coating of a resin compound having an formed for the purpose of producing a plurality of semicon O—COOH-O, Si O, or Si N backbone. After application, ductor devices, e.g., DRAM semiconductor devices, SRAM the coated surface is heat-treated to set the resin, followed by semiconductor devices or other types of semiconductor heating at between 250° C. and the glass transition point 25 devices. After forming the semiconductor devices on the (-450–500° C.) for 3 to 4 hours to form silicon dioxide. This active surface of the wafer, covering the semiconductor method for forming a silicon dioxide layer suffers from the devices with an insulative layer, and forming conductive spin-coating disadvantages listed above. In addition, it traces on each semiconductor device, bond pads are formed requires significant furnace exposure at elevated tempera to connect the traces (generally copper, aluminum, or alloys tures. 30 thereof) to external connectors (via wire bonds, for It is desired to have a semiconductor manufacturing example). Prior to forming the bond pads by an electroless method to plate bond pads to achieve uniform high-quality, method, the wafer is submerged in a bath of supersaturated high-density pads. It is further desired to have such bond pad silicon dioxide at room temperature or somewhat higher, up formation without wafer inversion, while minimizing 35 to about 50° C., by which exposed silicon on the wafer back chemical usage, minimizing time consumption, and reduc side becomes covered with a passivating layer of silicon ing the use of high-cost equipment. In addition, it is desired dioxide. to have a method to produce Such semiconductor devices at an optimally high yield. The exposed copper or aluminum metallization at each bond pad location may then be coated with immersion In a paper of Antti J. Niskanen, published prior to Novem 40 ber 2000 and entitled LIQUID PHASE DEPOSITION OF palladium or Zinc, followed by an electroless nickel and, SILICON DIOXIDE, the author briefly summarizes tests to optionally, immersion gold, in a bath to form pads amenable determine the possibility of liquid phase deposition of to Soldering or another joint with an external conductor. For silicon dioxide. In a paper of Sampo Niskanen, dated example, the bond pads may then be coated with gold or November 2000 and titled DEVELOPMENT OF LIQUID 45 solder-bonded to conductive wires. The overall process PHASE DEPOSITION OF ZIRCONIUM OXIDE AND results in devices which are produced at reduced time and COMPARISON TO SILICON DIOXIDE, a summary is expense and which are more reliable than those currently presented of tests comparing liquid phase depositions of produced. Zirconium dioxide and silicon dioxide to form thin films. The liquid bath is supersaturated with respect to an oxide 50 of a material which is capable of forming a hexafluoro salt. SUMMARY OF THE INVENTION This includes, for example, silicon, Zirconium, iron, and Vanadium. In this invention, the primary passivation mate The present invention is a method for selectively forming rial of interest is silicon dioxide, but other oxides may also a dense layer of passivating oxide, e.g., silicon dioxide or be used. Zirconium oxide, onto an exposed semiconductor wafer 55 The liquid bath of saturated silicon dioxide is formed by Surface, e.g., silicon or germanium. The layer is applied by adding silicon dioxide and water to hexafluorosilicic acid Submersion of the exposed semiconductor wafer Surface in HSiF. The solution may be diluted with water either before a liquid at low or ambient temperature. The passivation layer or after silicon dioxide is added to the saturation point. Boric of easily controlled thickness may be formed in a limited acid (HBO) is then added to supersaturate the liquid in amount of time. The method differs from conventional 60 silicon dioxide. The silicon dioxide selectively precipitates high-temperature thermal oxidation, chemical vapor depo onto the silicon/silicon oxide Surface as a dense cohesive sition, and spin-on passivation methods, each of which layer of uniform thickness. requires Sophisticated equipment and high manpower costs. In addition to the application for enhancing bond pad The method does not require inversion of a semiconductor plating, the method of the invention is applicable to the wafer Such as required by prior art back side deposition 65 passivation of Vias and microvias and to forming other using spin-on deposition, nor does it require protracted layers on exposed silicon, Such as on a semiconductor device heating at a high temperature to cure the layer. wafer, interposer wafer, etc. US 7,190,052 B2 5 6 BRIEF DESCRIPTION OF THE SEVERAL 1C, followed by a layer 29 of immersion plated gold, as VIEWS OF THE DRAWINGS illustrated in FIG. 1D. Following plating of bond pads 12, the upper surface of semiconductor device 10 may be further The nature of the present invention, as well as other covered with a passivation and/or final package. It is under embodiments thereof, may be more clearly understood by 5 stood that semiconductor device 10, as shown, is part of a reference to the following detailed description of the inven multi-semiconductor device wafer containing a plurality, tion, to the appended claims, and to the several drawings e.g., hundreds, of semiconductor devices, although the herein, wherein: method is applicable to a single discrete semiconductor FIGS. 1A-1D are schematic cross-sectional representa device as well. tions through a semiconductor device, the back side of 10 which is depicted with a passivation layer applied in accor FIG. 2A illustrates a semiconductor device 10' with each dance with a method of the present invention; of the features of semiconductor device 10 (FIG. 1A). In FIGS. 2A-2C are schematic cross-sectional representa addition, semiconductor device 10' includes another passi tions through another semiconductor device, the back side of vation layer 15 which overlies passivation layer 14 and each which is depicted with a passivation layer applied in accor 15 bond pad 12 exposed therethrough, a redistributed bond pad dance with teachings of the present invention; 12' exposed through passivation layer 15, and a conductive FIG. 3 is a schematic representation of a method for redistribution trace 13 extending between passivation layer forming a passivation layer on silicon in accordance with the 14 and passivation layer 15 from bond pad 12 to its present invention and Subsequent plating of bond pads of a corresponding redistributed bond pad 12. Redistributed semiconductor device; bond pad 12" may be configured to receive a discrete FIG. 4 is a representation of an exemplary embodiment of conductive element (not shown). Such as a solder ball, and, a method for forming a Supersaturated silicon dioxide Solu therefore, may be formed from aluminum or another mate tion for passivating a silicon Surface in accordance with a rial Suitable for securing Such a discrete conductive element. method of the present invention; and Semiconductor device 10' also includes a back side passi FIG. 5 is a representation of the processes of another 25 vation layer 34 on a back side thereof. embodiment of forming a Supersaturated silicon dioxide As shown in FIGS. 2B and 2C, a zincate process may be Solution for passivating a silicon Surface in accordance with conducted on redistributed bond pad 12" (FIG. 2B) to form a method of the present invention. Zinc grains 30 thereon, which facilitate adherence of an electrolessly deposited nickel layer 31 to redistributed bond DETAILED DESCRIPTION OF THE 30 pad 12 (FIG. 2C). INVENTION Turning now to FIG. 3, one or more semiconductor wafers 40 are shown in a wafer carrier 42 for forming a back side With reference to FIGS. 1A-1D and 2A-2C, different silicon dioxide layer. First, at reference 46, the wafers 40 are types of bond pads 12, 12 that are typically used in immersed in a Supersaturated silicon dioxide Solution 44 to semiconductor devices 10, 10' are depicted. In FIG. 1A, a 35 precipitate, i.e., deposit a dense passivation layer 34 (see semiconductor device which includes copper bond pads 12 FIGS. 1A and 2A) on the back side 32 of each wafer 40. The is shown. Copper bond pads 12 are typically formed on a deposition is specific to exposed silicon (and its oxide), and passivation layer 14 of semiconductor device 10 and com substantially does not plate out on bond pads 12, 12 (FIGS. municate with underlying, integrated circuitry of semicon 1A and 2A, respectively) or on organic materials, such as ductor device 10. By way of example, one or more generally 40 photoresist. However, in the event that minute quantities of downwardly extending conductive vias 16 may establish silicon dioxide are found to adhere to bond pads 12, 12", the electrical communication with conductive traces 18, or latter may be precovered with tape to prevent deposition “runners', that, in turn, electrically communicate with the thereto. The back sides 32 of wafers 40 are shown as being integrated circuitry of semiconductor device 10. For in a vertical position during immersion. However, the wafer example, runners 18 may to contact plugs 20 that 45 orientation appears to be irrelevant to deposition rate or provide a conductive link between runners 18 and a con layer properties in this process, as long as constant exposure ductively doped silicon active-device region 22 of a tran to the Solution 44 is maintained. sistor 24 of semiconductor device 10. In the submersion process 46, the following factors are In order to use a rapid electroless plating method to plate controlled: bond pads 12, 12" without incurring damage to the semi 50 conductor device 10, it is necessary to insulate the net a. The concentration of components in the Supersaturated positive (+) charge on the semiconductor device's back side silicon dioxide solution 44 is controlled to provide 32. FIG. 1A also shows a back side passivation layer 34 of sufficient silicon dioxide for the desired layer depth and silicon dioxide that has been formed in accordance with insulative value. Inasmuch as deposition is specific to teachings of the present invention. In FIG. 1A, a back side 55 Surfaces of silicon and its oxide, the required solution passivation layer 34 of silicon dioxide has been formed by composition may be readily calculated. a method of this invention to electrically insulate the back b. During Submersion, the solution temperature generally side 32, preventing etching of bond pad 12, as well as other may be between about room temperature and about 50° possible damage to the circuits of semiconductor devices 10 C. While the temperature may be even higher, e.g., up by, for example, short circuiting during plating of bond pads 60 to about 90° C., there may be no reason to control the 12. temperature at much above room temperature in most Once back side passivation layer 34 has been formed, a CaSCS. palladium activation layer 26 may be formed thereon, as c. The time of submersion is relatively short, typically on depicted in FIG. 1B, such as by the aggressive, acid the order of about 1 minute to about 60 minutes, accelerated electroless plating processes described previ 65 depending upon the particular application. Some appli ously herein. A layer 28 of electrolessly deposited nickel cations may require longer immersion times to achieve may then be formed on each bond pad 12, as shown in FIG. the desired layer thickness. The deposition rate has US 7,190,052 B2 7 8 been found to be independent of the layer thickness, but which will tie up the HF to supersaturate the solution in may attain a “steady-state' thickness upon long-term silicon dioxide. In this invention, a silicon-Surfaced semi exposure. conductor device, wafer, interposer or other device is d. The pressure at which the exposure takes place is immersed in the Supersaturated Solution 44 for deposition of preferably atmospheric, or nearly so, requiring no spe a silicon dioxide layer. Following completion of Such depo cial control. sition, the coated device is rinsed to remove extraneous During submersion of the wafers 40, the supersaturated materials and further processed to completion. silicon dioxide solution 44 is preferably stirred or recycled An alternate method of the present invention is shown in to prevent local depletion of silicon dioxide and provide FIG. 5, in which the initial concentrated hexafluorosilicic fresh solution for coating the silicon Surfaces. 10 acid is first diluted with water prior to saturating with silicon Following formation of the back side passivation layer 34, dioxide. Following filtration, the method may follow sub the wafers 40 are extracted from the supersaturated silicon stantially the same process flow shown in FIG. 4. dioxide solution 44 and rinsed in rinsing apparatus 48 at The thickness of silicon dioxide layers which may be reference 50. Solution remaining on the wafer surfaces is formed by the methods of the invention range up to about washed away including any hexafluorosilicic acid, unat 15 100 nm in a single deposition. Typically, a desired layer tached precipitated silicon dioxide, and stable complex- thickness for passivating the back side of a semiconductor BF. wafer may be about 100 to 500 A (about 10 to about 50 nm), Optionally, the rinsed wafers 40 may be dried to prevent and other applications may use silicon dioxide layers of less any dilution (though slight) of the Subsequent plating solu than 100 A thickness. tion 52. However, there is no need to heat-treat the wafers It should be noted that in either of the foregoing methods 40. Such as is required by some layering processes. of FIGS. 4 and 5, aluminum may be substituted for boric As shown in FIG. 3, the bond pads 12, 12 (FIGS. 1A and acid. In this case, the aluminum reacts with HF to form AlF. 2A) may then be plated with nickel or other metal in an driving reaction A to the right to Supersaturate the Solution electroless process, from plating Solution 52, in a plating in silicon dioxide. represented at reference 54. Of course, such an electroless 25 Thus far, the invention has been described in terms of a plating process may include activation or other preparation passivation layer comprising silicon dioxide. Other oxides of the surface of bond pads 12, 12", as explained previously may be formed which will deposit onto an exposed silicon herein (e.g., palladium activation of copper, Zincating alu Surface, having similar chemical routes. For example, the minum, etc.) A Subsequent rinsing process 58 is conducted layer-forming solution may be configured to deposit the using rinsing apparatus 56 before Subsequent manufacturing 30 oxides of Zirconium, titanium, Vanadium and even iron. processes, e.g., attachment of wires and packaging, are In another embodiment of the method of the present performed. Each of the indicated processes may be com invention, a silicon dioxide-depositing solution may be prised of several Subprocesses. formed by adding ammonia (NH) to a hexafluorosilicic acid Alternative methods for forming the supersaturated sili solution whereby the solution becomes supersaturated in con dioxide solution 44 are depicted in drawing FIGS. 4 and 35 silicon dioxide. 5. As shown in the drawing figures, the aqueous reaction In a first embodiment, already described, a passivating solution 44 comprises an acid salt of the desired layer of silicon dioxide is formed on the back side of a oxide, whether silicon dioxide, Zirconium oxide, etc., and semiconductor wafer, with many advantages over the prior the solution is supersaturated in the desired oxide by the art. The invention also encompasses the application of a addition of a buffer, e.g., boric acid. The reactions, which 40 passivating layer on the inner walls of a laser-formed via, on take place in the formation of Solution 44, specific to silicon members such as carrier Substrates, interposer Substrates for dioxide, are as follows: flip-chip packaging, beneath interconnects for test packages, and the like. The method of the present invention is par ticularly useful for passivating vias and microvias Such as 45 made by lasers through silicon. The method of the present HBO+4HFCs BF +HO'+2H2O (Reaction B) invention deposits a uniform layer of oxide on the silicon It can be seen that in Reaction B, HF produced in Reaction surfaces of the via hole, without covering metallization to A is consumed by the addition of boric ion to produce a which the via hole may extend. Previous methods tend to stable complex ionic species BF (as well as ion produce uneven deposition so that, in order to assure com HO), driving Reaction A to the right. The result is super 50 plete coverage, the layer must in some places be much saturation of the solution with respect to SiO, which thicker than desired. The uneven coverage also unduly deposits on the exposed silicon Surface (and silicon dioxide limited the diameter of microvia holes. Use of the present Surface). invention avoids these problems, enabling uniform thin As shown in drawing FIG. 4, one method for making a coatings within Vias or microvias, formed easily, without Supersaturated silicon dioxide Solution is to first form an 55 prolonged exposure, and without covering nonsilicon Sur aqueous solution of hexafluorosilicic acid HSiF. The solu faces. tion is formed at a generally high concentration, for Although the foregoing description contains many spe example, about 20–50 weight percent HSiF. Silicon diox cifics, these should not be construed as limiting the scope of ide (SiO) is then added whereby, at equilibrium, the solu the present invention, but merely as providing illustrations tion is saturated with respect to the oxide and contains 60 of some exemplary embodiments. Similarly, other embodi . ments of the invention may be devised which do not depart Any silicon dioxide which precipitates, together with any from the spirit or scope of the present invention. Features other solids, is then preferably removed from the solution 44 from different embodiments may be employed in combina with, for example, a 0.2 um filter. The result is a substan tion. The scope of the invention is, therefore, indicated and tially solid-free solution 44 saturated in silicon dioxide. 65 limited only by the appended claims and their legal equiva The solution is then diluted with water. To this diluted lents, rather than by the foregoing description. All additions, solution 44 is added boric acid (HBO) at a concentration deletions, and modifications to the invention, as disclosed US 7,190,052 B2 9 10 herein, which fall within the meaning and scope of the 10. The semiconductor device structure of claim 8, claims are to be embraced thereby. wherein the at least one at least partially formed semicon What is claimed is: ductor device component comprises at least one of a semi 1. A semiconductor device structure, comprising: conductor device structure, an interposer, and a carrier a semiconductor Substrate including an active surface and substrate. a backside; at least one at least partially formed semiconductor device 11. The semiconductor device structure of claim 7, component carried by the active Surface; and wherein the oxide coating Substantially covers a backside of an oxide coating of Substantially uniform thickness cov the semiconductor Substrate. ering Substantially all Surface features of the semicon 10 12. The semiconductor device structure of claim 7, ductor Substrate and the at least one at least partially wherein the semiconductor Substrate includes at least one formed semiconductor device that comprise semicon via hole including at least one surface coated with a portion ductor material, including unoxidized forms of the of the oxide coating. semiconductor material, doped forms of the semicon 13. The semiconductor device structure of claim 7, ductor material, and oxides, nitrides, or oxynitrides of 15 wherein the oxide coating has a thickness of about 100 A to the semiconductor material, non-silicon-containing about 500 A. surface features of the semiconductor substrate and the at least partially formed semiconductor device being 14. A semiconductor device structure, comprising: exposed through the oxide coating. a semiconductor Substrate; and 2. The semiconductor device structure of claim 1, wherein an oxide coating Substantially covering all Surface fea the semiconductor Substrate includes at least one aperture tures of the semiconductor Substrate comprising unoxi including at least one interior Surface coated with a portion dized forms of the semiconductor material, doped of the oxide coating. forms of the semiconductor material, and oxides, 3. The semiconductor device structure of claim 1, wherein nitrides, or oxynitrides of the semiconductor material, the oxide coating has a thickness of about 100 A to about 25 preexisting metal Surface features of the semiconductor 500 A. Substrate being exposed through the oxide coating. 4. The semiconductor device structure of claim 1, wherein the semiconductor Substrate carries a plurality of at least 15. The semiconductor device structure of claim 14, partially formed semiconductor device components. wherein an active surface of the semiconductor substrate 5. The semiconductor device structure of claim 1, wherein 30 carries at least one at least partially formed semiconductor the at least one at least partially formed semiconductor device component. device component comprises at least one of a semiconductor 16. The semiconductor device structure of claim 15, device structure, an interposer, and a carrier Substrate. wherein the at least one at least partially formed semicon 6. The semiconductor device structure of claim 1, wherein ductor device component comprises at least one of a semi the oxide coating substantially covers the backside of the 35 conductor device structure, an interposer, and a carrier semiconductor Substrate. substrate. 7. A semiconductor device structure, comprising: a semiconductor Substrate; and 17. The semiconductor device structure of claim 15, an oxide coating of Substantially uniform thickness cov wherein the active surface of the semiconductor substrate ering all features of the semiconductor substrate that 40 carries a plurality of at least partially formed semiconductor comprise semiconductor material, including unoxi device components. dized forms of the semiconductor material, doped 18. The semiconductor device structure of claim 14, forms of the semiconductor material, and oxides, wherein the oxide coating Substantially covers a backside of nitrides, or oxynitrides of the semiconductor material, the semiconductor Substrate. without coating preexisting Surface features that com 45 19. The semiconductor device structure of claim 14, prise metal. wherein the semiconductor Substrate includes at least one 8. The semiconductor device structure of claim 7, further via hole including at least one surface coated with a portion comprising: of the oxide coating. at least one at least partially formed semiconductor device component carried by an active surface of the semi 50 20. The semiconductor device structure of claim 14, conductor Substrate. wherein the oxide coating has a thickness of about 100 A to 9. The semiconductor device structure of claim 8, wherein about 500 A. the semiconductor Substrate carries a plurality of at least partially formed semiconductor device components.