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United States Patent (10) Patent No.: US 7,190,052 B2 Lindgren (45) Date of Patent: Mar

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United States Patent (10) Patent No.: US 7,190,052 B2 Lindgren (45) Date of Patent: Mar US0071900.52B2 (12) United States Patent (10) Patent No.: US 7,190,052 B2 Lindgren (45) Date of Patent: Mar. 13, 2007 (54) SEMICONDUCTOR DEVICES WITH OXIDE 5,516,721 A 5/1996 Galli et al. COATINGS SELECTIVELY POSITONED 5,683,946 A 1 1/1997 Lu et al. OVER EXPOSED FEATURES INCLUDING 5,776,829 A 7/1998 Homma et al. SEMCONDUCTOR MATERAL 6,022,814 A 2/2000 Mikoshiba et al. 6,045,877 A 4/2000 Gleason et al. (75) Inventor: Joseph T. Lindgren, Boise, ID (US) 6,174,8246,130,116 AB1 10/20001/2001 MichaelSmith et etal. al. 6, 197,110 B1 3/2001 Lee et al. (73) Assignee: Micron Technology, Inc., Boise, ID 6,251,753 B1 6/2001 Yeh et al. (US) (*) Notice: Subject to any disclaimer, the term of this (Continued) patent is extended or adjusted under 35 OTHER PUBLICATIONS U.S.C. 154(b) by 0 days. Schreiber, S.J. et al., “Low Temperature Deposition of Microcrystal line Silicon For Thin Film Transistors,' CUED Electronic Devices (21) Appl. No.: 10/454.256 and Materials Group, http://www2.eng.cam.ac.uk/~www-edm/ (22) Filed: Jun. 3, 2003 projects/lowtempdepf1.htm, prior to Sep. 2000, 2 pages. e as (Continued) (65) Prior Publication Data Primary Examiner T. N. Quach US 2004/OO33682 A1 Feb. 19, 2004 (74) Attorney, Agent, or Firm TraskBritt Related U.S. Application Data (57) ABSTRACT (62) Division of application No. 10/218.268, filed on Aug. 13, 2002, now Pat. No. 6,593,221. A semiconductor device structure includes a passivation layer through which only non-silicon-comprising structures (51) Int. Cl. are exposed. The semiconductor device structure is formed HOIL 2.3/58 (2006.01) by selectively forming the passivation layer on an exposed (52) U.S. Cl. ....................... 257/632: 257/638; 257/758 silicon-comprising surface by exposing surfaces of the semi (58) Field of Classification Search ................ 257/632, conductor device to a liquid phase solution Supersaturated in 257/638,639, 649 silicon dioxide. The exposure is conducted at Substantially See application file for complete search history. atmospheric temperature and pressure and achieves an effec tive passivation layer in an abbreviated time, and without (56) References Cited Subsequent heat treatment. A wafer that includes a back side U.S. PATENT DOCUMENTS coated with Such a passivation layer may be subjected to a high-speed electroless process for plating the bond pad with 4,599,792 A * 7/1986 Cade et al. ................. 438,454 a solder-enhancing material. The semiconductor device 5, 192,714 A * 3/1993 Suguro et al. .............. 438,631 5,256,593 A 10, 1993 Iwai structure may also include via holes and microvia holes with 5,365,112 A 11/1994 Oshima walls that are passivated. 5,395,645 A 3, 1995 Kodera et al. 5,429,956 A 7, 1995 Shell et al. 20 Claims, 4 Drawing Sheets US 7,190,052 B2 Page 2 U.S. PATENT DOCUMENTS Niskanen, Antti J., “Liquid Phase Deposition of Silicon Dioxide.” http://.../Liquid Silicon Dioxide. 6,294,832 B1 9, 2001 Yeh et al. htm+liquid-phase--Silicon--Dioxide+deposition&hl=en&start=. 6,335,224 B1 1/2002 Peterson et al. 6,399.494 B1* 6/2002 Nagata ....................... 438,682 prior to Nov. 2000, 2 pages.(Cache of http://www.hut.fi/Units/ 6,671,947 B2 1/2004 Bohr ........................... 29,846 Electron/Projects2000/LiquidSiliconDioxide.htm). Yeh, Ching-Fa et al., “Properties of Silicon Exide Prepared by OTHER PUBLICATIONS Liquid-Phase Deposition.” Mar. 26, 1999, 1 page, http://www.aps. Niskanen, Sampo, “Development of Liquid Phase Deposition of org/meet/CCNT99/BAPS/abs/S8880001.html). Zirconium Oxide and Comparison to Silicon Dioxide.” http:// sampo.rdx.net/LPD/lpd.html, Nov. 19, 2000, 15 pages. * cited by examiner U.S. Patent Mar. 13, 2007 Sheet 1 of 4 US 7,190,052 B2 O N 8 12 2O f It S 16 28 12 FFEIt Fig. 1C U.S. Patent Mar. 13, 2007 Sheet 2 of 4 US 7,190,052 B2 1O 30 12 Fig. 2B 12 31 = - A-17 N Fig. 2C U.S. Patent Mar. 13, 2007 Sheet 3 of 4 US 7,190,052 B2 NICKEL RINSE PLATING RINSE SOLN. 56 Fig. 3 U.S. Patent Mar. 13, 2007 Sheet 4 of 4 US 7,190,052 B2 H2SiF6 H2SiF6 High Concentration High Concentration SiO2 Dilution H2O Filtration H2SiF6 Low Concentration SiO2-saturated H2SiF6 SiO2 High Concentration Filtration H2O SiO2-saturated SiO2-saturated H2SiF6 H2SiF6 Low Concentration Low Concentration HBO3 HBO SiO2-supersaturated SiO2-supersaturated H2SiF6 H2SiF6 Contact with Exposed Contact with Exposed Silicon or SiO2 at <50°C Silicon or SiO2 at <50°C to Deposit SiO2 to Deposit SiO2 Fig. 4 Fig. 5 US 7,190,052 B2 1. 2 SEMCONDUCTOR DEVICES WITH OXDE operating costs of oxidation furnaces are high. Furthermore, COATINGS SELECTIVELY POSITONED a problem, which must be considered in thermal oxidation, OVER EXPOSED FEATURES INCLUDING is the formation of Surface dislocations which may cause SEMCONDUCTOR MATERAL circuit problems. Another consideration relating to oxide growth is the CROSS-REFERENCE TO RELATED inability to adequately passivate the lateral walls of a small APPLICATION via hole (Such as a laser-formed microvia) of a multilayer device prior to deposition of a conductive material (Such as This application is a divisional of application Ser. No. tungsten) into the via hole. Present passivation methods for 10/218.268, filed Aug. 13, 2002, now U.S. Pat. No. 6.59, 10 insulating the lateral walls of such small-diameter holes tend 3221. to produce uneven coverage, sometimes leading to either short circuits between the conductive via and the semicon BACKGROUND OF THE INVENTION ductor or excessive filling of the via hole. In forming semiconductor devices, the electrically con 1. Field of the Invention 15 ductive bond pads on the active surface are grounded to the The present invention relates to methods for electrically back side of the wafer. Unless neutralized by a passivation isolating dielectric materials. More particularly, the inven layer, the wafer back side has a net positive (+) charge. tion pertains to methods for electrical isolation, i.e., passi Bond pad formation typically includes applying a copper Vation of exposed silicon Such as occurs on the back side of or aluminum base, then coating the base with another a semiconductor (SC) wafer comprising semiconductor material so that wire bonds or conductive structures, such as devices or dice of a DRAM, SRAM, or other semiconductor solder, may be secured to the bond pad. die configuration. The invention also pertains to passivation In the case of bond pads to which bond wires are to be of apparatus Such as carrier Substrates, interposer Substrates secured, copper is typically employed as the bond pad for flip-chip packaging, conductive interconnects for test material. As copper forms a “slippery' oxide that is difficult packages, and the like. 25 to remove with a wire bonding capillary, nickel and gold 2. Background of Related Art adhesion layers are typically used. As copper alone will not Silicon is a basic material from which a broad range of initiate the adhesion of nickel thereto, a palladium “strike'. semiconductor devices is composed. Silicon is a semicon or seed layer, is typically formed prior to conducting an ductor while its oxidation product, silicon dioxide, acts as a electroless nickel-plating process. dielectric (insulating) material. Thus, silicon dioxide is one 30 Efforts have been made to use more aggressive plating of the classical insulators used to electrically isolate silicon chemistries in order to speed the plating rate and create a from conductive leads, specific functional devices in elec higher density coating at lower cost. Such chemistries, e.g., tronic apparatus, and the atmosphere. Other insulators that palladium chloride in hydrochloric acid, greatly enhance the are used include a variety of organic and inorganic com plating rate and plate density. However, unless the wafer pounds. 35 back side is first passivated, copper pads which communi The manufacture of semiconductor devices is performed cate with the silicon Substrate (e.g., pads that communicate by forming a plurality of the functional devices on a wafer with active-device regions of transistors) and, thus, which and Subsequently separating each semiconductor device by may form a circuit directly through the silicon Substrate, cutting along a pattern of saw lines crisscrossing the wafer. may be attacked by the plating chemistry and dissolve in as The various processes for forming a semiconductor device 40 little as several minutes of exposure, resulting in damaged such as a DRAM or SRAM device may be generally pads with performance anomalies. In addition, bath chemi characterized as including crystal growth, bare wafer for cals will be inordinately consumed. The use of sulfuric acid mation, Surface preparation, oxidation/nitridation, heat treat in the palladium electroless plating Solution may curb Such ment, patterning, layer deposition, doping, metallization, an attack of the bond pads to Some extent, but does not and packaging. Typically, each of these processes includes 45 completely resolve this problem. Once the palladium strike several Subprocesses. has been formed, nickel may be plated onto the copper and Layer deposition is generally performed by one of several palladium by way of electroless deposition processes, then processes, such as physical vapor deposition (PVD), chemi a gold layer may be formed by immersion plating processes. cal vapor deposition (CVD), Sputtering, and electron-beam Aluminum is typically used as the base metal for bond evaporation. In cases where the desired layer is to be an 50 pads that will receive solder balls or other discrete conduc oxide of the base material, e.g., silicon dioxide, another tive elements.
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