A SOFT-CORE PROCESSOR ARCHITECTURE OPTIMISED FOR RADAR SIGNAL PROCESSING APPLICATIONS by René Broich Submitted in partial fulfilment of the requirements for the degree Master of Engineering (Electronic Engineering) in the Department of Electrical, Electronic and Computer Engineering Faculty of Engineering, Built Environment and Information Technology UNIVERSITY OF PRETORIA December 2013 © University of Pretoria SUMMARY A SOFT-CORE PROCESSOR ARCHITECTURE OPTIMISED FOR RADAR SIGNAL PROCESSING APPLICATIONS by René Broich Promoters: Hans Grobler Department: Electrical, Electronic and Computer Engineering University: University of Pretoria Degree: Master of Engineering (Electronic Engineering) Keywords: Radar signal processor, soft-core processor, FPGA architecture, signal- flow characteristics, streaming processor, pipelined processor, soft-core DSP, processor design, DSP architecture, transport-based processor. Current radar signal processor architectures lack either performance or flexibility in terms of ease of modification and large design time overheads. Combinations of processors and FPGAs are typically hard-wired together into a precisely timed and pipelined solution to achieve a desired level of func- tionality and performance. Such a fixed processing solution is clearly not feasible for new algorithm evaluation or quick changes during field tests. A more flexible solution based on a high-performance soft-core processing architecture is proposed. To develop such a processing architecture, data and signal-flow characteristics of common radar sig- nal processing algorithms are analysed. Each algorithm is broken down into signal processing and mathematical operations. The computational requirements are then evaluated using an abstract model of computation to determine the relative importance of each mathematical operation. Critical portions of the radar applications are identified for architecture selection and optimisation purposes. Built around these dominant operations, a soft-core architecture model that is better matched to the core computational requirements of a radar signal processor is proposed. The processor model is iteratively refined based on the previous synthesis as well as code profiling results. To automate this iterative process, a software development environment was designed. The software development en- vironment enables rapid architectural design space exploration through the automatic generation of © University of Pretoria development tools (assembler, linker, code editor, cycle accurate emulator / simulator, programmer, and debugger) as well as platform independent VHDL code from an architecture description file. To- gether with the board specific HDL-based HAL files, the design files are synthesised using the vendor specific FPGA tools and practically verified on a custom high performance development board. Tim- ing results, functional accuracy, resource usage, profiling and performance data are analysed and fed back into the architecture description file for further refinement. The results from this iterative design process yielded a unique transport-based pipelined architec- ture. The proposed architecture achieves high data throughput while providing the flexibility that a software-programmable device offers. The end user can thus write custom radar algorithms in software rather than going through a long and complex HDL-based design. The simplicity of this architecture enables high clock frequencies, deterministic response times, and makes it easy to un- derstand. Furthermore, the architecture is scalable in performance and functionality for a variety of different streaming and burst-processing related applications. A comparison to the Texas Instruments C66x DSP core showed a decrease in clock cycles by a factor between 10.8 and 20.9 for the identical radar application on the proposed architecture over a range of typical operating parameters. Even with the limited clock speeds achievable on the FPGA technology, the proposed architecture exceeds the performance of the commercial high-end DSP processor. Further research is required on ASIC, SIMD and multi-core implementations as well as compiler technology for the proposed architecture. A custom ASIC implementation is expected to further improve the processing performance by factors between 10 and 27. © University of Pretoria OPSOMMING ’N SAGTEKERNPROSESSEERDERARGITEKTUUR WAT VIR RADARSEINPROSESSERINGTOEPASSINGS OPTIMEER IS deur René Broich Promotors: Hans Grobler Departement: Elektriese, Elektroniese en Rekenaar-Ingenieurswese Universiteit: Universiteit van Pretoria Graad: Magister in Ingenieurswese (Elektroniese Ingenieurswese) Sleutelwoorde: Radarseinverwerker, sagtekernverwerker, FPGA-argitektuur, seinvloei- eienskappe, vloeiverwerker, pyplynargitektuur, DSP-sagtekern, DSP- verwerker, vervoergebaseerde verwerker Die huidige radarseinverwerkerargitekture kort óf prestasie óf buigbaarheid betreffende maklike modifikasie en hoë oorhoofse ontwerptydkoste. Kombinasies van verwerkers en FPGAs word tipies hard bedraad in ’n noukeurig gemete en pyplynoplossing om die vereiste vlak van funksionaliteit en prestasie te bereik. So ’n vasteverwerker-oplossing is duidelik nie vir nuwe algoritmiese bereken- inge of vinnige veranderinge tydens veldtoetse geskik nie. ’n Meer buigsame oplossing gebaseer op hoëprestasie-sagtekernverwerkerargitektuur word voorgestel. Om so ’n verwerkingsargitektuur te ontwikkel, is data- en seinvloei-eienskappe van gemeenskap- like radarseinverwerkingalgoritmes ontleed. Elke algoritme word afgebreek in seinverwerking- en wiskundige berekeninge. Die berekeningvereistes word dan geëvalueer met behulp van ’n abstrakte berekeningsmodel om die relatiewe belangrikheid van elke wiskundige operasie te bepaal. Krit- ieke gedeeltes van die radartoepassings word geïdentifiseer vir argitektuurseleksie en optimering- doeleindes. ’n Sagtekern-argitektuurmodel, wat volgens die dominante operasies gebou is en wat beter aan die kernberekeningsvereistes van ’n radarseinverwerker voldoen, word voorgestel. Die verwerkermodel word iteratief verfyn op die basis van die vorige sintese sowel as kodeprofielresultate. Om hierdie © University of Pretoria herhalende proses te outomatiseer, is ’n sagteware-ontwikkelingomgewing ontwerp. Die sagteware- ontwikkelingsomgewing maak vinnige argitektoniese ontwerpsverkenning van die ruimte deur mid- del van die outomatiese generasie van ontwikkelinggereedskap (samesteller, binder, koderedakteur, siklus-akkurate emulator/simulator, programmeerder en ontfouter) sowel as platform-onafhanklike VHDL-kode van ’n argitektuurbeskrywinglêer moontlik. Saam met die bord-spesifieke HDL- gebaseerde HAL-lêers word die ontwerpslêers gesintetiseer deur die verkoper-spesifieke FPGA- gereedskap te gebruik en prakties geverifieer op ’n doelgemaakte hoëprestasie-ontwikkelingbord. Tydsberekeningresultate, funksionele akkuraatheid, middele-gebruik, profiele en prestasiedata word ontleed en teruggevoer in die argitektuurbeskrywinglêer vir verdere verfyning. Die resultaat van hierdie iteratiewe ontwerpsproses is ’n unieke vervoergebaseerde pyplynargitektuur. Die voorgestelde argitektuur bereik hoë deurvoer van data en verleen terselfdertyd die buigsaamheid wat ’n sagteware-programmeerbare toestel bied. Die eindgebruiker kan dus doelgemaakte radar- algoritmes in sagteware skryf, eerder as om dit deur ’n lang en komplekse HDL-gebaseerde ontwerp te doen. Die eenvoud van hierdie argitektuur lewer hoë klokfrekwensie en deterministiese reaksietye en maak dit maklik om te verstaan. Verder is die argitektuur skaleerbaar wat prestasie en funksionaliteit betref vir ’n verskeidenheid vloeiverwerkerverwante toepassings. In vergelyking met die Texas Instruments C66x DSP-kern was daar ’n afname in kloksiklusse met ’n faktor van tussen 10,8 en 20,9 vir die identiese radar op die voorgestelde argitektuur oor ’n ver- skeidenheid tipiese bedryfstelselparameters. Selfs met die beperkte klokspoed wat haalbaar is op die FPGA-tegnologie, oorskry die voorgestelde argitektuur die prestasie van die kommersiële hoëspoed- DSP-verwerker. Verdere navorsing is nodig oor ASIC, SIMD en multi-kern-implementering, sowel as samesteller- tegnologie vir die voorgestelde argitektuur. Daar word voorsien dat ’n pasgemaakte ASIC- implementering die verwerkingprestasie tussen 10 en 27 maal sal verbeter. © University of Pretoria LIST OF ABBREVIATIONS AAU Address arithmetic unit ABI Application binary interface ADL Architecture description language AESA Active electronically scanned array AGU Address generation unit BRF Burst repetition frequency BRI Burst repetition interval CAM Content-addressable memory CFAR Constant false alarm rate CLB Configurable logic block CORDIC Coordinate rotational digital computer CPI Coherent processing interval CW Continuous wave DDS Direct digital synthesizer DFG Data flow graphs DFT Discrete Fourier transform DIF Decimation-in-frequency DIT Decimation-in-time DLP Data-level parallelism DPU Data processing units DSP Digital signal processor EPIC Explicitly parallel instruction computing EW Electronic warfare FM Frequency modulating FU Functional unit GPGPU General purpose computing on GPUs HDL Hardware descriptive language HLS High-level synthesis HRR High range resolution HSDF Homogeneous synchronous data flow © University of Pretoria I/Q In-phase and quadrature IDFT Inverse discrete time Fourier transform IF Intermediate frequency ILP Instruction-level parallelism IP Intellectual property LE Logic elements LFM Linear frequency modulated LNA Low noise amplifier LUT Look up