IBM System Z9 Enterprise Class Technical Guide

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Front cover IBM System z9 Enterprise Class Technical Guide Structure and design a total systems approach Processor unit, memory, channel subsystems, and subchannel sets Concurrent upgrade and maintenance options Bill White Franck Injey Greg Chambers Marian Gasparovic Parwez Hamid Brian Hatfield Ken Hewitt Dick Jorna Patrick Kappeler ibm.com/redbooks International Technical Support Organization IBM System z9 Enterprise Class Technical Guide June 2007 SG24-7124-02 Note: Before using this information and the product it supports, read the information in “Notices” on page vii. Third Edition (June 2007) This edition (SG24-7124-02) applies to the IBM® System z9 Enterprise Class server. © Copyright International Business Machines Corporation 2005, 2006, 2007. All rights reserved. Note to U.S. Government Users Restricted Rights -- Use, duplication or disclosure restricted by GSA ADP Schedule Contract with IBM Corp. Contents Notices . vii Trademarks . viii Preface . ix The team that wrote this book . ix Become a published author . .x Comments welcome. xi Chapter 1. Overview . 1 1.1 Introduction . 2 1.2 z9 EC models . 4 1.3 System functions and features . 6 1.3.1 The CEC cage . 7 1.3.2 I/O connectivity . 10 1.3.3 Cryptography . 12 1.3.4 Performance . 14 1.3.5 Parallel Sysplex support . 16 1.3.6 Server Time Protocol . 17 1.3.7 Intelligent Resource Director (IRD) . 18 1.3.8 Capacity On Demand . 19 1.3.9 Reliability, Availability, and Serviceability (RAS). 20 1.3.10 Software . 21 1.4 Service-Oriented Architecture (SOA) . 21 1.5 Summary. 24 Chapter 2. System structure and design . 27 2.1 System structure . 28 2.1.1 Book concept . 28 2.1.2 Models . 31 2.1.3 Memory . 32 2.1.4 Ring topology . 36 2.1.5 Connectivity . 37 2.1.6 Frames and cages . 39 2.1.7 The MCM . 42 2.1.8 The PU, SC, SD, and MSC chips . 42 2.1.9 Summary. 44 2.2 System design. 45 2.2.1 Design highlights. 45 2.2.2 Book design . 46 2.2.3 Processor Unit design. 48 2.2.4 Processor Unit functions . 54 2.2.5 Memory design . 68 2.3 Model configurations . 71 2.4 Logical partitioning . 79 2.5 Storage operations . 84 2.5.1 Reserved storage . 86 2.5.2 Logical partition storage granularity . 87 2.5.3 LPAR Dynamic Storage Reconfiguration (DSR). 87 © Copyright IBM Corp. 2005, 2006, 2007. All rights reserved. iii Chapter 3. I/O system structure. 89 3.1 Overview . 90 3.2 I/O cages. 91 3.2.1 Self-Timed Interconnect (STI). 93 3.2.2 STIs and I/O cage connections. 94 3.2.3 Balancing I/O connections . 96 3.3 I/O and cryptographic feature cards . 97 3.3.1 I/O feature cards . 97 3.3.2 Physical Channel IDs (PCHIDs) . 98 3.4 Connectivity. 101 3.4.1 I/O and cryptographic features support and configuration rules . 101 3.4.2 ESCON channels . 105 3.4.3 FICON channels . 108 3.4.4 OSA-Express2 and OSA-Express adapters . 115 3.4.5 Coupling links . 124 3.4.6 External Time Reference feature (FC 6155). 126 3.4.7 Cryptographic features . 127 Chapter 4. Channel Subsystem . 129 4.1 Channel Subsystem (CSS) . 130 4.1.1 Multiple CSSs concept . 131 4.1.2 Multiple CSSs structure. 131 4.1.3 Multiple Subchannel Sets (MSS) . ..

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