AIDA-C: Analog IC Design Optimization Embedding Ngspice As the Evaluation Engine

AIDA-C: Analog IC Design Optimization Embedding NGSpice as the Evaluation Engine

Catarina Figueiredo Aleixo

Thesis to obtain the Master of Science Degree in

Electrical and Computer Engineering

Supervisors: Prof. Nuno Cavaco Gomes Horta

Prof. Rui Santos Tavares

Examination Comittee:

Chairperson: Prof. Teresa Maria Sá Ferreira Vazão Vasques

Supervisors: Prof. Nuno Cavaco Gomes Horta

Member of the Committee: Prof. Manuel Fernando Martins de Barros

November 2019

ii Declaration

I declare that this document is an original work of my own authorship and that it fulfils all the requirements of the Code of Conduct and Good Practices of the Universidade de Lisboa.

iii

iv Acknowledgments

I would like to thank the Integrated Circuits group from Instituto de Telecomunicações for all the support given during the development of this work. I would like to give a special thanks to my parents and my sister for being always by my side and for the way they raised me. Lastly, I would like also to thank my boyfriend Valter, for always supporting and helping me.

Resumo

Na automatização do dimensionamento de circuitos integrados analógicos duas abordagens podem ser seguidas: knowledge-based ou optimization-based, sendo que a última é ainda subdividida em duas categorias, equation-based ou simulation-based. Relativamente ao dimensionamento baseado em simulações, o método de avaliação é sustentado num simulador de circuitos, como é o caso do AIDA- C, um otimizador de circuitos integrados analógicos. O trabalho desenvolvido ao longo desta tese visa integrar um simulador de circuitos open-source, nomeadamente o NGSpice, no AIDA, que atualmente utiliza o ELDO, um simualdor comercial. Para verificar que comandos devem ser invocados no NGSpice, para que os valores obtidos para as várias medidas sejam o mais próximas possível dos valores obtidos no ELDO, várias netlists foram simuladas em ambos os simuladores, para garantir que os outputs obtidos são bastante similares. Integrar o NGSpice no AIDA requereu o desenvolvimento de uma interface, visto que o ficheiro de saída do NGSpice não é compatível com o ficheiro que o AIDA espera receber com todas as medidas e os seus respetivos valores. Esta interface foi desenvolvida em Python e permite executar várias simulações em paralelo. O paralelismo desta interface permite aumentar o seu desempenho, culmatando as limitações do NGSpice, principalmente quando são simulados corners. Foi feita uma análise estatística aos resultados obtidos, onde se obtiveram intervalos de confiança a 95% para os erros relativos de cada uma das medidas obtidas, onde se provou que o NGSpice pode substituir o ELDO como simulador do AIDA. É preciso ter em consideração que os resultados obtidos pelo AIDA em cada otimização variam, não só entre simuladores, mas também entre simulações, para o mesmo simulador, visto que o algoritmo desenvolvido é baseado num processo estocástico, pelo que, para ser possível comparar diretamente os dois simuladores de forma justa e equitativa, os pontos simulados no ELDO foram posteriormente simulados no NGSpice e vice- versa.

vii

viii

Abstract

Two distinct approaches can be followed when automatizing analog IC sizing: knowledge-based or optimization-based. The latter is subdivided into two categories: equation-based and simulation-based. Simulation-based sizing uses a circuit simulator as evaluation engine, which is the case of AIDA-C, an Analog Integrated Circuit Design Automation environment. The work developed throughout this thesis aims to integrate an open source circuits simulator, namely the NGSpice, into AIDA, which currently uses ELDO as its simulation engine. Multiple netlists were run in NGSpice in order to check which simulation commands should be invoked, to guarantee that the corresponding outputs match with ELDO’s outputs. Integrating NGSpice into AIDA required the development of an interface, since the latter has a specific input format which is not compatible with NGSpice’s output. This interface is written in Python and is able to run multiple netlists in parallel. The parallelism allows to increase the interface performance, which had to overcome NGSpice limitations, particularly when running corners. The results obtained were analysed statistically, where 95% confidence intervals for the relative errors of each performance measure were obtained, proving that NGSpice can be AIDA’s simulation engine. AIDA’s outputs always differ among optimizations, even using the same simulator, due to the algorithm used, which is based on a stochastic process. Taking this into account, to fairly compare both simulators the points simulated in ELDO were then simulated in NGSpice, and vice-versa.

x Table of Contents

Introduction...... 1

1.1 Motivation ...... 1 1.2 Circuit-level EDA ...... 2 1.3 Challenges and Benefits of an Open Source Evaluation Engine ...... 3 1.4 Goals ...... 3 1.5 Document Outline ...... 4

Related Work and AIDA Framework ...... 5

2.1 Optimization-based EDA Tools ...... 5 2.2 AIDA Framework ...... 6 2.3 Evaluation Engines ...... 8

2.3.1 Summary ...... 9

2.4 Conclusions ...... 10

NGSpice Evaluation ...... 11

3.1 Requirements ...... 11 3.2 NGSpice Execution Modes ...... 12 3.3 NGSpice Parameter Level ...... 13 3.4 NGSpice and ELDO Netlists ...... 13 3.5 NGSpice and Corners Simulation ...... 18 3.6 NGSpice Alterparam ...... 23 3.7 Conclusions ...... 25

Proposed Solution Architecture and Implementation ...... 27

4.1 Workflow of The Proposed Solution ...... 27

4.1.1 Calculate Measures ...... 29 4.1.2 Run Corners ...... 29 4.1.3 Output File ...... 30 4.1.4 Change Parameter Values ...... 30 4.1.5 Interface Development Language ...... 31

4.2 Implementation Details ...... 32

4.2.1 Run ACEI ...... 32 4.2.2 Netlists Generation to Run Corners ...... 33 4.2.3 Run Each Corner ...... 36 4.2.4 Generate Output File ...... 38

4.3 Conclusions ...... 40

xi Results ...... 41

5.1 Circuits Optimization ...... 41 5.2 NGSpice vs ELDO ...... 45 5.3 AIDA – Circuits Optimization...... 46

5.3.1 Project Setup ...... 46 5.3.2 Circuits Optimization ...... 47

5.4 Conclusions ...... 56

Conclusions ...... 57

6.1 Achievements ...... 57 6.2 Future Work ...... 58

Bibliography ...... 59 Appendix A ...... 63 NGSpice Guide to Use With AIDA ...... 63

A.1 NGSpice Commands ...... 63

A.1.1 Commands Used Outside of Control Section ...... 64 A.1.2 Analysis Commands ...... 65 A.1.3 Commands to Obtain Measures Inside Section ...... 67 A.2 Examples ...... 68

Appendix B ...... 71 Scripts Developed ...... 71

B.1 ACEI Developed ...... 71 B.2 R Script ...... 73

xii List of Figures

Figure 1.1: An Analog Devices engineer laying out a circuit board with tape by hand [1] ...... 1 Figure 1.2: Optimization-based Circuit Sizing [2] ...... 3 Figure 2.1: AIDA Architecture [34] ...... 7 Figure 2.2: AIDA GUI [42] ...... 7 Figure 2.3: ACEI Architecture [9] ...... 8 Figure 3.1: Interaction between AIDA and simulators ...... 11 Figure 3.2: NGSpice running in batch mode ...... 12 Figure 3.3: NGSpice running in interactive mode ...... 12 Figure 3.4: Level 53 not supported in current binary ...... 13 Figure 3.5: Fully-differential amplifier [47] ...... 13 Figure 3.6: Single-stage amplifier [46] ...... 14 Figure 3.7: Comparison between ELDO and NGSpice netlists ...... 14 Figure 3.8: Comparison of the IDD measure between simulators invoking only AC analysis ...... 15 Figure 3.9: IDD measure comparison among simulators invoking OP analysis in NGSpice ...... 15 Figure 3.10: NGSpice example where FOM measure depends on variables from both analyses ..... 16 Figure 3.11: NGSpice output of running a netlist with measures that depend on both analyses ...... 16 Figure 3.12: Differences between running corners in ELDO and in NGSpice ...... 18 Figure 3.13: Run only corner library ...... 19 Figure 3.14: Run typical and corner libraries in NGSpice using ELDO Syntax ...... 19 Figure 3.15: L130E_HG_RVT33_V131.lib.eldo file ...... 20 Figure 3.16: L130E_HG_RVT33_V131.mdl.eldo file...... 21 Figure 3.17: Error thrown when invoking L130E_HG_RVT33_V131.lib.eldo with altermod ...... 22 Figure 3.18: NGSpice simulation replacing expressions by values ...... 22 Figure 3.19: Netlist without alterparam command ...... 23 Figure 3.20: Netlist changing parameter values using alterparam command ...... 24 Figure 3.21: Output of running the netlist without alterparam command ...... 24 Figure 3.22: Output of running the netlist with alterparam command ...... 25 Figure 3.23: Output of running the netlist using reset command instead of mc_source ...... 25 Figure 4.1: User interaction with AIDA ...... 27 Figure 4.2: Interaction between AIDA and NGSpice ...... 28 Figure 4.3: Workflow between AIDA, ACEI and NGSpice...... 28 Figure 4.4: Calculate an overdrive and a margin in NGSpice netlist ...... 29 Figure 4.5: Corners.inc file that includes corners to be run ...... 30 Figure 4.6: Design_var.inc file example ...... 31 Figure 4.7: Run ACEI from AIDA ...... 32 Figure 4.8: Main() method of the ACEI developed ...... 33 Figure 4.9: Fill queue that contains the netlists to simulate (typical plus corners) ...... 34

xiii Figure 4.10: Corners.inc example changing temperatures and parameter values simultaneously .... 35 Figure 4.11: Method to replicate the original netlist according to the corners ...... 35 Figure 4.12: Method to copy the original netlist ...... 36 Figure 4.13: Method to change a file searching for a pattern and replace the value for a new one ... 36 Figure 4.14: Developed ACEI workflow ...... 37 Figure 4.15: Method executed by each thread to simulate netlists in parallel ...... 38 Figure 4.16: NGSpice Output ...... 38 Figure 4.17: Methods to write the output file which will be AIDA's input ...... 39 Figure 4.18: Output file of ACEI for NGSpice ...... 39 Figure 5.1: Folded Voltage-Combiners Biased Amplifier circuit [44] ...... 41 Figure 5.2: Dynamic Voltage-Combiners Biased OTA circuit [45] ...... 42 Figure 5.3: Testbenches for both circuits ...... 42 Figure 5.4: Corners.inc file optimizing Folded Voltage-Combiners Biased Amplifier Circuit ...... 43 Figure 5.5: Corners.inc file optimizing Dynamic Voltage-Combiners Biased OTA Circuit ...... 43 Figure 5.6: AIDA GUI – Validation and Run buttons ...... 46 Figure 5.7: AIDA-C Convergence Plot ...... 47 Figure 5.8: POFs obtained simulating ELDO points (Folded Voltage-Combiners Biased Amplifier Circuit) ...... 48 Figure 5.9: POFs obtained simulating ELDO points (Dynamic Voltage-Combiners Biased OTA Circuit) ...... 48 Figure 5.10: POFs obtained simulating NGSpice points (Folded Voltage-Combiners Biased Amplifier Circuit...... 49 Figure 5.11: POFs obtained simulating NGSpice points (Dynamic Voltage-Combiners Biased OTA Circuit) ...... 49 Figure B.1: R Script to obtain 95% confidence intervals for the relative errors of all performance measures ...... 73

xiv List of Tables

Table 2.1: Comparison between commercial simulators and NGSpice ...... 10 Table 3.1: AC Measures obtained running Single-stage amplifier circuit ...... 17 Table 3.2: OP Measures obtained running Single-stage amplifier circuit ...... 17 Table 5.1: Design Variables - Folded Voltage-Combiners Biased Amplifier Circuit ...... 44 Table 5.2: Design Variables - Dynamic Voltage-Combiners Biased OTA Circuit ...... 44 Table 5.3: Optimization options – Folded Voltage-Combiners Biased Amplifier Circuit ...... 45 Table 5.4: Optimization options - Dynamic Voltage-Combiners Biased OTA Circuit ...... 45 Table 5.5: Runtimes for Folded Voltage-Combiners Biased Amplifier circuit ...... 45 Table 5.6: Runtimes for Dynamic Voltage-Combiners Biased OTA circuits ...... 45 Table 5.7: 95% Confidence Intervals for Relative Errors - ELDO points (Folded Voltage-Combiners Biased Amplifier Circuit) ...... 52 Table 5.8: 95% Confidence Intervals for Relative Errors - NGSpice points (Folded Voltage-Combiners Biased Amplifier Circuit) ...... 53 Table 5.9: 95% Confidence Intervals for Relative Errors - ELDO points (Dynamic Voltage-Combiners Biased OTA Circuit) ...... 54 Table 5.10: 95% Confidence Intervals for Relative Errors - NGSpice points (Dynamic Voltage- Combiners Biased OTA Circuit) ...... 55 Table B.1: ACEI Methods ...... 72

xv List of Acronyms

ACEI AIDA-C Custom Evaluation Interface

AIDA Analog Integrated Circuit Design Automation

CAD Computer Aided Design

EDA Electronic Design Automation

FOM Figure of Merit

GBW Gain Bandwidth Product

GUI Graphical User Interface

IC Integrated Circuit

POF Pareto Optimal Front

RF Radio-Frequency

VHDL VHSIC Hardware Description Language

VHSIC Very High Speed Integrated Circuits

VLSI Very Large-Scale Integration

xvi Introduction

This first chapter introduces the concept Electronic Design Automation (EDA) applied to analog IC design and discusses its relevance. The two main approaches with respect to automate analog IC sizing, knowledge-based and optimization-based are briefly explained. The challenges and benefits of having an open-source simulator engine is presented, as well as, the goals of this thesis.

1.1 Motivation

In the context of this thesis, EDA is a category of products and processes to support analog IC design at circuit-level. In general terms, EDA emerged in the 70’s and revolutionized the way how engineers design products (integrated circuits, circuit boards, etc.). By that time, engineers did not have design constraints to obey, therefore they could put their creativity in practice and design what they desired, since circuits were really simple compared to nowadays, which made them hand-drawable and eye- verifiable [1].

Figure 1.1: An Analog Devices engineer laying out a circuit board with tape by hand [1]

Nevertheless, the circuits began to be increasingly complex, which allowed the development of software tools capable of making hard and complex tasks, considering the limits of computer power. In the 80’s, VLSI was introduced and electronic designs started to be compiled. After that, design verification and simulation tools were developed in order to design more complex integrated circuits. EDA tools started to be commercialized in 1981, when companies like Hewlett-Packard, Tektronix and Intel used them internally and also when VHDL emerged. A few years after that, Verilog was developed and there was a need to develop simulators capable of supporting these languages.

Nowadays, integrated circuits are mainly implemented through digital circuits, although radio-frequency and analog circuits are still the basis for many interfaces and transceivers. Having in account that the electronic systems are composed by multimillion transistor ICs, their design is only possible due to EDA and CAD tools.

1 Nevertheless, despite most of design stages of digital circuits being automated, the lack of CAD tools for electronic design automation of analog and radio frequency ICs contributes to error-prone designer’s intervention, during the entire course of the design process, which impacts on the overall system of development. These divergences among digital and analog design are related to the fact that the latter is not as systematic as the former, since different designs produce different circuits, which entails that most of the designed analog blocks are not usually reused in other circuits. In addition, in analog design, the optimization is fully heuristic and requires a larger knowledge base from the designer. Once the tendency is mixing digital and analog systems, the lower reuse rate of analog circuit blocks increases the production period of developing mixed-signal integrated circuits.

Commonly, an analog project may require weeks or months to be manually developed. Considering that market demands are increasing, automate the developing process is extremely important, using EDA tools. These tools have many advantages, such as: eliminating errors, optimizing the design of integrated circuits, minimizing the time-to-market and handle the complexity of the design of integrated circuits and systems.

1.2 Circuit-level EDA

There are two different approaches with respect to automate analog IC sizing, namely knowledge-based and optimization-based. Focusing on the early automation systems, the initial strategy applied did not use any optimization, on the contrary, the knowledge-based approaches try to systematize the design deriving a design plan through specific knowledge, i.e., consist of a plan supported by design equations and applying design strategies to produce devices that meet the performance requirements [2]. The short consuming time is the main advantage of these approaches. On the other hand, deriving a plan is not an easy task, consumes plenty of time and requires maintenance to keep up with the technological evolution.

The other approaches, optimization-based, schematized in Figure 1.2, apply optimization techniques to automate IC sizing and they can be divided in two main different subclasses: equation-based or simulation-based, which is defined according to the method used to evaluate circuit’s performance. Equation-based techniques use analytic design equations, while simulation-based use a circuit simulator. The latter benefits from a faster execution time, which makes it preferable since equations are expensive to maintain and the results are not so accurate. Nowadays, the simulation-based sizing is clearly in a better position due to the increase in computational resources. There are also other evaluation methods, based on machine learning techniques, such as support vector machines or artificial neural networks.

Figure 1.2: Optimization-based Circuit Sizing [2]

1.3 Challenges and Benefits of an Open Source Evaluation Engine

Nowadays, there are several evaluation engines, both commercial and open-source simulators. Open source evaluation engines raise many challenges and also bring many benefits. The main advantage of these engines is that they offer a flexibility and freedom of integration, that the commercial simulators do not have, since they do not have any costs associated and the code is exposed and available to download and edit. Nevertheless, open source simulators also have limitations, namely the lack of support and possible instability of versions. NGSpice [3], Gnucap [4] , Qucs [5] or Xyce [6] are examples of open source circuit simulators that are quite used nowadays.

NGSpice is being developed and maintained for more than fifteen years, which make it popular among free spice-based simulators. In fact, this simulator is used in many tools nowadays, both free and commercial, which validates its potential, such that, EasyEDA, KiCad, Eagle or CppSim, among many others [7].

1.4 Goals

The main goal of this thesis is to integrate an open source simulator, namely, NGSpice simulator, in AIDA (Analog Integrated Circuit Design Automation environment), in order to make it completely independent from any commercial circuit simulator. In order to achieve the main goal, several steps need to be followed, such as:

• Define the list of measurements to be accomplished; • Find the commands of NGSpice to gather all the measurements previously defined; • Simulate the same circuits using NGSpice and a simulator currently supported by AIDA;

3 • Compare the results of both simulators in order to validate NGSpice output values, since the syntax differs from ELDO’s; • Find how to run corners and variations in combinations of parameters and its values in NGSpice, in the most efficient way; • Analyse the format of the output file of NGSpice, which will be an input to AIDA; • Develop a new ACEI (AIDA-C Custom Evaluation Interface) compatible with NGSpice outputs; • Compare the execution time of running AIDA using NGSpice and using the simulator currently supported by AIDA; • Validate the new approach by running complete optimizations using NGSpice as AIDA’s evaluation engine.

After addressing all these steps, AIDA will be independent of the commercial evaluation engines and free for dissemination among the academic community.

1.5 Document Outline

This thesis focuses on defining the existing problem, describing the main objectives, revaluing the related work, proposing a new approach and presenting the corresponding results.

In the second chapter many optimization-based EDA tools are described and the AIDA Framework is presented, along with its components. In addition, the most used electrical simulators nowadays are identified and characterized. A comparison among them and NGSpice will be performed, since is the open source simulator that will be integrated in AIDA.

The third chapter starts by reviewing the problem to be solved and proposes a solution to fix it. In order to structure the problem, tests to NGSpice have to be done, to guarantee that can be integrated in AIDA. To accomplish that, comparisons with ELDO outputs will be made, since is one of the simulators that AIDA uses nowadays, along with the commands that both support.

After structure the problem and identifying how NGSpice behaves, a solution to integrate it in AIDA will be proposed. In the fourth chapter that solution is defined, along with the implementation details of all development performed.

In the fifth chapter, results from the optimization of two different circuits, using both simulators, ELDO and NGSpice, will be presented. These results include the POFs obtained for both circuits and 95% confidence intervals for the relative errors of all performance measures.

Finally, in the sixth chapter the conclusions about all work performed are drawn, along with some features which can improve the implemented solution.

4 Related Work and AIDA Framework

In this chapter, all features and all components of the Analog Integrated Circuit Design Automation environment, AIDA, in which NGSpice aims to be integrated, will be exposed. Other EDA tools will also be presented, focusing on the ones that follow an optimization-based approach.

2.1 Optimization-based EDA Tools

As mentioned in the previous chapter, optimization-based approaches are subdivided into two categories: equation-based and simulation-based. With the increase in computer power, simulation- based optimization became more advantageous. Simulation-based sizing uses a circuit simulator, e.g., SPICE [8] as evaluation engine, which is the case of AIDA-C [9].

There are plenty algorithms that use optimization techniques, starting by the early approaches where local optimization around a “good” solution was used, in simulation-based automatic sizing, being SA [10] (simulated annealing) the most common optimization technique used. DELIGTH. SPICE [11] performs local optimization from a starting point provided by the user. FASY [12] and Kuo-Hsuan et al. [13] derive approximate solutions using equations and use SA in order to optimize the circuit design. Cheng et al. [14] follows a similar approach, using SA as a starting point and adding constraints to the problem through considering transistor bias conditions. Castro-Lopez et al. [15] performs the optimization also using SA combined with a deterministic method for fine-tuning, while FRIDGE [16] uses an annealing-like optimization, without imposing any restrictions to the starting point.

Genetic algorithms [17] are another class of optimization methods, which simulate the natural evolution of the current population, obtaining new solution vectors, after applying genetic operators of mutation and crossover. Alpaydin et al. [18] uses equations together with simulations to compute the performance of the circuits, through hybridization of evolutionary and annealing optimization. Barros et al. [19] [20] optimizes circuit sizing through genetic algorithms, using the circuit simulator and a support vector machine (SVM) to evaluate the populations. In Santos-Tavares [21], MAELSTROM [22] and ANACONDA [23], the parallel mechanism that allows to share the evaluation load in between multiple computers, reduces the time to simulate the population.

Other approach to optimize circuit sizing, that also uses evolutionary methods, consists of generating both the circuit topologies and the device sizes simultaneously. Koza [24], Sripramong [25] and Hongying [26] suggested a design procedure to generate new topologies, starting from low abstraction level. Although this is an innovative approach, designers are septic about it due to the generated structures being quite different from the well-known analog circuit structures.

5 In addition, swarm intelligence algorithms [27], which uses many simple agents to lead an intelligent global behaviour, are also methods to optimize analog circuit sizing. The most common ones are ant colony optimization (ACO), applied in [28] and particle swarm optimization (PSO) [29].

Circuit sizing is a multi-objective multi-constraint problem where the designer explores the trade-off in between opposed performance measures, such as, minimizing power consumption while maximizing bandwidth or maximizing gain and minimizing the area of an amplifier, which makes multi-objective optimization techniques being commonly used. Considering diverse objectives implies having a set of optimal trade-off solutions, generally denominated Pareto optimal front. Once both evolutionary and swarm intelligence algorithms are composed of multiple elements, they both are suitable to this approach. MOJITO [30] is an example of the application of the evolutionary multi-objective methods to circuit sizing and both sizing and topology exploration. In Pradhan and Vemuri [31], a distinct strategy is followed, using the multi-objective simulated annealing.

2.2 AIDA Framework

One of the main challenges for analog and RF integrated circuits is improving the efficiency of automated circuit sizing. This automation is performed through well-defined objectives that aimed to be achieved by dimensioning the sizes of circuit devices. Albeit optimization-based techniques use a circuit simulator to analyse the circuits performance, there are plenty of commercial solutions that address the circuit sizing problem as a single-objective, i.e., an optimization around a single solution, taking no advantage of the flexibility provided by the trade-offs of considering multiple objectives.

This thesis is related to AIDA, an Analog Integrated Circuit Design Automation environment, more properly on AIDA-C, an EDA tool for analog integrated circuit optimization at circuit-level, which solves the referred limitations. This EDA tool uses state-of-the-art multi-objective multi-constraint optimization techniques, including robust design requirements, since considers corner analysis, together with commercial simulators, such as ELDOTM, developed by Mentor Graphics, or HSPICE, from Synopsys. The optimization outputs are a set of Pareto Optimal Fronts which are the non-dominated solutions, meaning a feasible solution, where there is not another feasible solution which is better than the present one in a certain objective function, without worsening another objective function.

AIDA’s architecture is represented in Figure 2.1, where both AIDA-C and AIDA-L, the circuit sizing optimization and the layout generation tools, respectively, are drawn.

Figure 2.1: AIDA Architecture [34]

AIDA has also a GUI (Graphical User Interface) that allows the management and interaction with the design automation process, as shown in Figure 2.2.

Figure 2.2: AIDA GUI [42]

This thesis focuses on AIDA-C, where the circuit optimizer uses commercial simulators, which evaluate the circuits performance throughout the optimization process. AIDA-C was built to allow users to integrate their simulation tools. For that, an interface that writes files, executes commands and reads output files, must be defined between AIDA-C and the simulator. After running the user’s simulation tool, AIDA-C is able to read the well-defined output files that are expected to contain the measurements of interest. This interface was named ACEI, which stands for AIDA-C Custom Evaluation Interface, illustrated in Figure 2.3.

AIDA.dat _lc _nfc _wb meas1 meas2 1.075e-04 1.075e-04 3.25e-06 …

*.cir

SIM AIDA SIM Handler (ELDO/HSPICE/ SPECTRE)

*.meas

SIM_OUT.dat _lc _nfc _wb meas1 meas2 1.075e-04 1.075e-04 3.25e-06 failed 1e4

Figure 2.3: ACEI Architecture [9]

An engine that takes advantage of the AIDA-C Custom Evaluation Interface is named ACEI engine. These engines have three main responsibilities:

• Obtain the outputs from AIDA-C, which includes an electrical list, a file with a combination of parameters names and its respective values, and a file containing corners to be tested; • Invoke the simulator and the ability to access the errors if simulation fails; • Generate a table with a specified format including the measurements of interest, which will be an input to AIDA-C.

As mention before, AIDA-C is able to support simulations either with ELDO or HSPICE simulators. However, both have license fees, which is a limitation to disseminating this EDA tool.

2.3 Evaluation Engines

The main advantage of simulation engines is their ability to afford practical feedback when designing real circuits. These tools allow the user to explore the trade-offs among different designs without actually physically building the circuit. As a result, the inherent costs of developing a system decrease, reinforcing the powerfulness of these engines.

Nowadays there are plenty of these tools, commercial and open source. Considering that this thesis is related to electronic circuit simulators, the most popular ones will be introduced and characterized, so that their capabilities/features, advantages and disadvantages can be perceived.

8 Firstly, all of commercial simulators have a common feature: they are all based on SPICE (Simulated Program with Integrated Circuit Emphasis). However, SPICE has some limitations, and one of them is related to not considering the noise, interference and crosstalk, unless that behaviour is not added to the circuit. So, each simulation is as accurate as the behaviours modelled in the SPICE devices created for it. These simulators present consistent results and have plenty of support which is valuable to users. The main limitation is imposed by the number of licenses available and the costs associated.

Apart from the commercial simulators, there are also free evaluation engines, e.g., NGSpice, Gnucap, Qucs or Xyce. These engines have more limitations than the commercial simulators, mainly due to the lack of support provided. Apart from the manual and the online forums, there is no sources to search for any doubt, which sometimes inhibits its use. However, the time spent investigating how these simulators behave could be worth it, considering that there are no costs associated with it and the unlimited number of licences available, which reinforces the powerfulness of these simulators and their capability of being integrated within other tools, which could be a great asset nowadays.

2.3.1 Summary

Currently, AIDA’s circuit optimizer uses commercial simulators. However, the number of licenses and the costs associate is a barrier to spread this tool. NGSpice emerges as a solution to overcome these limitations. However, for a better understanding about commercial and open source engines, firstly is important to highlight their main features.

In Table 2.1, a comparison between four simulators: ELDO from Mentor, SPECTRE from Cadence, HSPICE from Synopsys and NGSpice is established. Looking at Table 2.1, which resumes the features of each simulator, is clear that they all have the same functionalities, except for NGSpice that does not support sweep analysis explicitly. Although there is no command to directly perform sweep analyses in NGSpice, there is a way of implementing it, using loops and variables inside the netlist.

Despite that disadvantage of NGSpice, is the only simulator that is free, which makes it preferable in this particular case, since the main idea is turning AIDA completely independent of any commercial engine. This open source simulator is being developed and maintained for more than fifteen years and makes part of many tools nowadays. There are plenty of tools that use NGSpice for circuit simulation [7], including EDA tools, eSIM or KiCad, and another well-known software, such as Matlab, PSIM or OpenMETA, among many others, which highlight even more its potential.

9 Table 2.1: Comparison between commercial simulators and NGSpice

Simulators

Eldo Sepctre HSpice NGSpice Developed By Mentor Cadence Synopsys Open source Analog/Digital/Mixed Signal Mixed Signal Mixed Signal Mixed Signal Mixed Signal Paid/Free Paid Paid Paid Free Transient, DC and AC analyses x x x x Monte Carlo x x x x Multi-thread x x x x Sweeping analysis x x x Supports verilog x x x x Noise, transfer function, x x x x sensitivity and pole-zero analyses

2.4 Conclusions

In this chapter, a comparison among EDA tools that follow an optimization-based approach is performed and the architecture of AIDA framework is illustrated, along with its components and features. The AIDA- C Custom Evaluation Interface is an engine capable of establishing the connection between a simulator and AIDA, which will allow the integration of NGSpice, if the outputs of the simulations were coherent. Finally, a comparison between simulators, commercials and NGSpice, is presented, showing that the latter lacks only the sweep analysis.

10 NGSpice Evaluation

This chapter evaluates the open source simulator that will be integrated in AIDA, starting by defining the measures needed to be accomplished. A comparison between NGSpice and ELDO, which is one of the simulators that AIDA uses nowadays, will also be established. Besides that, NGSpice features will be explored in order to meet the requirements, which include, for example, running corners and changing the values of the parameters.

3.1 Requirements

Firstly, is important to understand how simulators interact with AIDA in order to delineate how each requirement will be addressed. The schema presented in Figure 3.1 shows, from a high perspective, how each simulator can be integrated in AIDA:

Commercial Simulators

ELDO O ACEI AIDA HSPICE S

Open-source Simulator

NGSpice S: Simulate Circuit

O: Simulation Outputs

Figure 3.1: Interaction between AIDA and simulators

Basically, the communication between AIDA and the simulators is performed through an interface, which not only executes simulations, but also collects the corresponding outputs which will then be delivered to AIDA. However, before establishing the interface structure which will be responsible for the communication between AIDA and NGSpice, several tasks must be performed in order to understand how the requirements will be met, such as:

• Compile and run NGSpice; • Simulate different circuits, with different measures, to guarantee that all important measurements can be performed; • Simulate the same circuits using ELDO simulator; • Compare the outputs of both simulators to assure that results match, since both syntaxes differ; • Run corners and simulate the same circuit changing the parameters values.

11 After gathering all this information and knowing how the simulator behaves, the interface between AIDA and NGSpice can be finally structured.

3.2 NGSpice Execution Modes

NGSpice can be executed in two different ways: batch mode or interactive mode. Although, the interactive mode is more suitable when a user can interact with the simulator, this mode also allows to run a script, the netlist, without having to perform any interaction, using control sections along with the quit command. These sections have many advantages that will be highlighted further ahead.

When using the batch mode, the behaviour of control sections used to get the measures needed is unpredictable, which inhibits its use when using these sections. Both modes, batch and interactive, are represented in Figure 3.2 and Figure 3.3, respectively.

Figure 3.2: NGSpice running in batch mode

Figure 3.3: NGSpice running in interactive mode

In short, the command line that will be used to run circuits has the following structure:

ngspice netlist.cir > output.dat

This command line saves the simulation standard output, in interactive mode, to the specified file.

12 3.3 NGSpice Parameter Level

The tests were performed using the pdk’s (process design kits) from UMC, technology node of 130nm, provided by the manufacturer that are used in ELDO simulator, apart from two values. The first is the level parameter that was changed since NGSpice does not support level 53, as demonstrated in Figure 3.4, and so, it was changed to level 8. The level 49 was also tested, but the values obtained were exactly the same. The last one is the optacm parameter that is not supported by NGSpice and throws a warning when running a circuit, although does not have impact on the output values.

Figure 3.4: Level 53 not supported in current binary

3.4 NGSpice and ELDO Netlists

One of the most important tasks to perform in this work is to understand how each measure can be obtained in NGSpice. The lack of support is a barrier since, apart from the manual, is really difficult to find examples showing how measures can be extracted from each simulation. The best way to overcome this obstacle is simulating many circuits and have the results from other simulator to compare the results. In order to understand NGSpice behaviour, two amplifiers were tested, in which both AC and OP analyses were performed. Both schematics are represented in Figure 3.5 and Figure 3.6.

Figure 3.5: Fully-differential amplifier [47]

Figure 3.6: Single-stage amplifier [46]

In spite of the output values, given by NGSpice, being very similar to the ones given by ELDO, the syntax of the netlists run in the former are quite different from the ones in the latter, as shown in Figure 3.7.

Figure 3.7: Comparison between ELDO and NGSpice netlists

14 Looking at Figure 3.7, the differences between both netlists are notorious. Firstly, in theory, both simulators perform the OP analysis by default, when the AC analysis is invoked. However, as presented below, in Figure 3.8, when invoking only the AC analysis in NGSpice there are a particular measure (in this specific case, the IDD), from the operating point analysis, which does not match with ELDO’s value.

Figure 3.8: Comparison of the IDD measure between simulators invoking only AC analysis

Although, if the OP analysis is explicitly invoked in the netlist (as pointed with an orange dashed line in Figure 3.7), the IDD value obtained with NGSpice is equal to ELDO’s value, as proved in Figure 3.9.

Figure 3.9: IDD measure comparison among simulators invoking OP analysis in NGSpice

Despite of being possible to obtain the correct value of the IDD, there is a limitation which is imposed when the OP analysis has to be explicitly invoked in NGSpice. When a new analysis is performed, all measures obtained in the previous analysis are erased from memory and no longer can be used further ahead in the netlist, for example, to calculate another measures. A concrete example is exposed in Figure 3.10, where the same netlist was run calculating the figure of merit (FOM), from the GBW and the IDD measures.

Figure 3.10: NGSpice example where FOM measure depends on variables from both analyses

Figure 3.11: NGSpice output of running a netlist with measures that depend on both analyses

As demonstrated in Figure 3.11, the out.txt file has no measure named FOM, since NGSpice throwed an error. The simulator was not able to calculate that particular measure due to not having access to the GBW measure obtained from the AC analysis.

Another difference between both simulators is how both the overdrives and margins of each transistor are obtained (as demonstrated in Figure 3.7, marked with a blue dashed line). There are a set of parameters that have to be extracted from the OP analysis, more precisely, the voltage from gate to

16 source (푉𝑔푠), the threshold voltage (푉푡ℎ), the voltage from drain to source (푉푑푠) and the voltage from drain to source, when the transistors enter the saturation region (푉푑푠푎푡). Using both simulators, inside the netlist, the user can use explicitly order to calculate both the overdrives and the margins, subtracting in each transistor 푉𝑔푠 − 푉푡ℎ and 푉푑푠 − 푉푑푠푎푡 , respectively. However, in NGSpice, both overdrives and margins have to be assigned to a variable that can be later printed to the standard output, while in ELDO with the .MEASURE command the same measures are immediately printed.

Another important difference is the command .EXTRACT used to get performance measures in ELDO simulator, which does not exist in NGSpice. To obtain these measures, NGSpice uses the .MEASURE command, differing here in the way these values are obtained. These differences are also highlighted in Figure 3.7, with a green dashed line.

Finally, in NGSpice, both the analyses and measures are enclosed in a control section. This section enables the use of interactive mode without the need of the user to interact with it. The comparison between the outputs given by both simulators are presented in the tables below, along with the relative error, for the measures declared in Figure 3.7.

Table 3.1: AC Measures obtained running Single-stage amplifier circuit

AC Measures ELDO NGSpice Relative Error IDD 3,7260E-04 3,7260E-04 0,000% GDC 5,0783E+01 5,0783E+01 0,000% GBW 7,9326E+07 7,9320E+07 0,008% PM 6,1749E+01 6,1749E+01 0,000% FOM 1,2774E+15 1,2773E+15 0,008%

Table 3.2: OP Measures obtained running Single-stage amplifier circuit

OP Measures ELDO NGSpice Relative Error

vov_mnm0 3,4472E-01 3,4472E-01 0,000%

vov_mnm1 3,8601E-01 3,8600E-01 0,003%

delta_mnm0 1,3030E+00 1,3029E+00 0,008%

delta_mnm1 6,5729E-01 6,5727E-01 0,003%

As illustrated in Table 3.1 and Table 3.2, the relative error between the output values of both simulators are negligible for both analyses, validating the syntax used in NGSpice to obtain the same measures as in ELDO.

17 3.5 NGSpice and Corners Simulation

Corners are variations in the values of fabrication parameters, more properly, represent the extremes of these parameter variations, which corresponds to varying increments of environmental conditions, such as voltage, clock frequency or temperature, simultaneously or not. The main idea of simulating corners is to verify the behaviour of circuits, testing its limits.

NGSpice has a command, altermod, which allows the user to switch between model parameters. However, the libraries used cannot have the same structure as in ELDO, since corners are not obtained in the same way. In Figure 3.12, the differences between both simulators are illustrated:

Figure 3.12: Differences between running corners in ELDO and in NGSpice

Looking at both netlists, the differences are notorious, starting by the syntax. ELDO uses two commands, ALTER and .lib commands to run a corner where a library is changed, while in NGSpice only the altermod is invoked followed by the path to the corresponding library.

However, NGSpice also supports the commands used in ELDO. Nevertheless, as demonstrated in Figure 3.13 and Figure 3.14, the .lib command overrides the typical library declared at the beginning of the netlist.

Figure 3.13: Run only corner library

Figure 3.14: Run typical and corner libraries in NGSpice using ELDO Syntax

Looking at the figures above, the values highlighted with a blue dashed line prove that the typical library is being overridden by the corner library, since the outputs of Figure 3.14 are equal and correspond to the output of running the SS library. These results do not allow the use of the same syntax as in ELDO, since both outputs cannot be gathered using the same netlist.

In addition, there is also another barrier when using altermod. In Figure 3.12, the file with the corner library is different in ELDO and in NGSpice due to the difference between invoking .lib command and altermod. In ELDO, the library is changed to the L130E_HG_RVT33_V131.lib.eldo file, which has the following content (Figure 3.15):

Figure 3.15: L130E_HG_RVT33_V131.lib.eldo file

Basically, the file presented above has many parameters that, according to the library chosen, are assigned to the corresponding value. However, independently of the library chosen, another file is included, L130E_HG_RVT33_V131.mdl.eldo. For simplicity, only part of this file is described in Figure 3.16:

Figure 3.16: L130E_HG_RVT33_V131.mdl.eldo file

The figure above shows that each parameter defined in L130E_HG_RVT33_V131.lib.eldo file will serve has label to the L130E_HG_RVT33_V131.mdl.eldo file. This allows to have only one L130E_HG_RVT33_V131.mdl.eldo file for all libraries. For example, the TOX parameter is given by the expression '6.9500E-09+DTOX_N_HG_33_L130E', which is equal to 6.9500E-09 for the typical-typical (TT) library and 6.9500E-09+1.5000E-10 for the slow-slow library (SS). However, when running NGSpice, invoking altermod command with the L130E_HG_RVT33_V131.lib.eldo file, the simulation does not run, and the following error is thrown (Figure 3.17):

Figure 3.17: Error thrown when invoking L130E_HG_RVT33_V131.lib.eldo with altermod

However, if the expression in L130E_HG_RVT33_V131.mdl.eldo file is replaced by the value itself, i.e., instead of having TOX = '6.9500E-09+DTOX_N_HG_33_L130E', assigning TOX = 7.1E-09, then the simulation runs and the output is what is expected, since the output of simulating the circuit with the SS library (Figure 3.13 and Figure 3.14), corresponds to the second group of values of Figure 3.18:

Figure 3.18: NGSpice simulation replacing expressions by values

22 This barrier implies that, instead of having one L130E_HG_RVT33_V131.mdl.eldo file for all the libraries, there must be one L130E_HG_RVT33_V131.mdl.eldo file for each library, which turns the L130E_HG_RVT33_V131.lib.eldo file useless, when using NGSpice as simulator.

Finally, when running corners using NGSpice, every time a corner is simulated, the analysis to perform has to be invoked as many times as the number of corners, which is not a good approach to users, since increases the difficulty of doing a netlist, which would have as much blocks of repeated lines as the number of corners. In short, to use altermod the number of *.mdl.eldo files and the number of repeated blocks of code, according to the analyses performed, depends on the number of corners to run.

3.6 NGSpice Alterparam

The usage of netlist variables, i.e. parameters, was also tested. NGSpice provides a command, alterparam, that allows to change the value of global parameters or in sub circuits defined by the .param statement. Tests were done in order to evaluate if the results were coherent. The first scenario included running a netlist, with just a few measures, assigning fixed values to the parameters, without using the alterparam command to change its values, as represented in Figure 3.19.

Figure 3.19: Netlist without alterparam command

Following that, a netlist with different initial parameter values was run and, inside the control section, the alterparam command was executed changing the initial parameter values to the ones presented in Figure 3.19. Both the initial parameter values and the netlist run are represented in Figure 3.20.

Figure 3.20: Netlist changing parameter values using alterparam command

The outputs of both simulations are presented in Figure 3.21 and Figure 3.22, where the blue dashed line highlights the measure’s values that should match. These results validate the use of this command once the desired values are achieved, since running a netlist with only a set of parameters (Figure 3.19), and running a netlist with the same measures, with different values for the initial parameters, and using alterparam to change them to the ones used in the first netlist (Figure 3.20) gives the same result.

Figure 3.21: Output of running the netlist without alterparam command

Figure 3.22: Output of running the netlist with alterparam command

However, there is an important detail when using the alterparam command, since if every time a user changes parameter values, another command, mc_source, has to be also invoked in order to changes to be effective. Although in the NGSpice manual, there is a reference to use the reset command along with alterparam, when tested the results were not coherent, as illustrated in Figure 3.23:

Figure 3.23: Output of running the netlist using reset command instead of mc_source

3.7 Conclusions

This chapter is dedicated to the evaluation of NGSpice, starting by defining the requirements that have to be met, to integrate it in AIDA. The execution modes of NGSpice are presented, as well as, their differences. The netlists of both simulators, ELDO and NGSpice, are quite different and their comparison is illustrated, along with simulations performed for a certain circuit, to compare both ELDO and NGSpice outputs. Lastly, the commands to run corners and to change parameter values in NGSpice were analysed in detail. This evaluation is crucial to define how the proposed solution should be structured.

26 Proposed Solution Architecture and Implementation

This thesis aims at integrating NGSpice, an open source circuits simulator, in AIDA, easing the user experience using the EDA tool and ensuring that the outputs are very similar to what is expected, compared to ELDO’s outputs. This chapter presents the interaction between AIDA-C and NGSpice, specifying how each measure will be accomplished. The script developed will be presented in order to demonstrate how NGSpice’s barriers were overcome, considering the netlist replication, according to the number of corners, and running in parallel all these netlists, improving the system’s efficiency.

4.1 Workflow of The Proposed Solution

As mentioned in the second chapter, AIDA’s circuit optimizer (AIDA-C) was developed to allow the integration of user’s simulation tools. This integration is only possible establishing a well-defined communication protocol between AIDA-C and the user’s simulator. Using NGSpice as AIDA’s evaluation engine requires the development of an interface, named ACEI. This solution has to be implemented considering all the constraints of the simulator, as well as the format of the input file that AIDA expects to receive, every time a simulation is performed. AIDA has already some features that can be used to overcome some limitations imposed by the simulator that will be explained further ahead.

Taking into account all NGSpice barriers, the following Figure 4.1 and Figure 4.2, present the workflow of the proposed solution. The process starts with the user giving the necessary inputs, which include the netlist, a file with the corners and a file with the circuit design variables. In addition, the design variables range is set, along with the performance metrics and the objectives.

netlist aida-sim

design_var.inc

netlist aida-sim0 netlist design_var.inc AIDA corner.inc netlist aida-sim1 Sets the design variables range, design_var.inc performance metrics and goals … netlist aida-simN design_var.inc

Figure 4.1: User interaction with AIDA

27 AIDA has a feature to run simulations in parallel which consists of generating N folders (aida-sim to aida-simN), in order to simulate multiple netlists, simultaneously, as represented in Figure 4.1. However, this feature will not be used when using NGSpice as simulator, since the solution that will be proposed has also parallelism to enable multiple simulations, running at the same time.

AIDA design.xml

Invokes

ACEI netlist

corners.inc

netlist NGSpice Measures.txt

ACEI_OUT.dat netlist_corner1 NGSpice Measures_corner1.txt .lib SS .TEMP 55 netlist_corner2 NGSpice Measures_corner1.txt …

.param … +vdd=1.2 netlist_cornerN NGSpice Measures_cornerN.txt

Figure 4.2: Interaction between AIDA and NGSpice

In Figure 4.2, the work develop in this thesis is described. AIDA will invoke the interface (ACEI), so that the simulations run. However, before that, the interface has to generate the netlists needed, i.e., as much as the number of corners. These netlists are copies of the original one, except for the changes according to the corners.inc file. After that, for each netlist, the NGSpice will be invoked, in parallel, and each simulation will output one file containing the measures. Finally, all these files will be parsed into an output file, which will be returned to AIDA.

In short, apart from the syntax of the netlists, the user will not have to change the usual procedure when using AIDA. The interaction between AIDA, ACEI and the simulator, is simply described in Figure 4.3, where the ACEI developed is in between AIDA and the simulator, translating the simulation outputs to a well-define structure that AIDA understands.

netlist design corners variables invokes

AIDA ACEI NGSpice

output.dat *.txt output file

Figure 4.3: Workflow between AIDA, ACEI and NGSpice

28 4.1.1 Calculate Measures

When performing a simulation, is expected that the output file generated has all measures the user ask to extract in the netlist. There are also measures that depend on other measures that can be calculated inside the netlist. AIDA has a feature for calculating any measure that depends on other measures obtained from the same netlist, i.e., if the simulation outputs the voltage from gate to source (푉𝑔푠) and the threshold voltage (푉푡ℎ) of a certain circuit device, AIDA is able to calculate the respective overdrive. However, NGSpice, as ELDO, allows to obtain these values when running the netlist. The user only has to assign the formulas of the desired measures to variables and print them to the standard output, as demonstrated in Figure 4.4, where both the overdrive and margin of a certain device is being calculated.

Figure 4.4: Calculate an overdrive and a margin in NGSpice netlist

Nevertheless, NGSpice has a limitation which was demonstrated in the previous chapter, since any measure that depends on measures from more than one analysis cannot be obtained when the simulation runs, due to NGSpice erasing from memory all vectors between different analysis. This barrier is overcome using the AIDA’s feature, gathering from the simulation only the measures needed to perform the calculation of the desired measure, which will then be calculated in AIDA, using the design.xml file.

4.1.2 Run Corners

Regarding the corners, the interface would have to invoke the simulator as much times as the number of corners. Consequently, the interface would become slower and the time spent switching between simulations could have impact on the overall performance. In order to reduce this wasting of time, a parallel solution was thought but, for that, there is a need of having a number of netlists equal to the number of corners, plus the netlist which includes the typical library, so that each simulation run in each thread.

On account of that, the interface must generate all netlists needed, which includes replicating the original netlist and make the necessary changes to simulate the corner. All corners are in a file named corners.inc, which is given by the user, as usual. An example of that file is demonstrated in Figure 4.5, where each line represents a corner.

Figure 4.5: Corners.inc file that includes corners to be run

After that, the netlists are distributed among the number of cores available. A queue to hold the netlists is built and, as soon as a thread finishes to run a netlist, picks up another one from the queue, until there are no more simulations to perform [32].

4.1.3 Output File

Each simulation outputs a file which contains all measures obtained. However, the format of the output file of each simulator differs. The only way to connect the simulator and AIDA is defining a protocol in which the output file structure is well-defined, so that AIDA is able to understand each value of each measure.

The ACEI will be responsible for translating NGSpice outputs to AIDA. After executing all the simulations and collecting all values for each measure, an output file is generated inside the interface, which contains all the parameter’s names separated by tabs and a keyword Cornr# between corners, plus an end line followed by the corresponding values, also separated by tabs. This file is the input to AIDA, which will then parse that file and find the desired measures. An example of the output file will be further ahead in the document.

4.1.4 Change Parameter Values

As demonstrated in the previous chapter, to change the parameter values in NGSpice, new values are assigned using alterparam followed by the mc_source directive. Indeed, the mc_source reloads the netlist and reruns the analyses, meaning that NGSpice is invoked twice to change the parameter values.

30 In view of that, to run the combinations of parameters with different values, an existing feature of AIDA will be used, since changing the parameter values using NGSpice has no advantage once both run the netlist twice to obtain the results.

Using AIDA, the user only has to assign the SINGLE value to the inputMethod attribute, which belongs to the TestbenchSetup element in the design.xml file. The design_var.inc file contains the parameters and the corresponding values, which will be replaced every time the user wants to perform a sweep analysis over a set of parameters. An example of design_var.inc file is demonstrated in Figure 4.6.

Figure 4.6: Design_var.inc file example

4.1.5 Interface Development Language

Although NGSpice is an open source code, nowadays is highly developed and contains many folders, within lots of files, which makes it extremely hard to program over this code, that is written in C. Besides, every time a new release is made, the code would have to fit there again to be compatible with the input file AIDA expects.

Once this thesis has a deadline to be met, Python was the language chosen to develop the interface, not only because is much quicker to develop complex operations, but also due to being more suitable to changes if, for instance, a new version of NGSpice is released and the output structure change. Python is a powerful language, is used worldwide and run programs in parallel, which makes it preferable to use in this case.

31 4.2 Implementation Details

After structuring how the problem was addressed, the implemented solution will be presented, detailing each method presented in the ACEI developed, which can be found in [33].

4.2.1 Run ACEI

Along with the script, to invoke the ACEI, the netlist, the option to run corners and the output file name have to be given as input:

• Running corners: acei-ngspice –corners netlist.cir output-file.dat; • Otherwise: acei-ngspice netlist.cir output-file.dat.

This command line is defined in the design.xml file, as an attribute named exec of the NominalTb element, as described in Figure 4.7.

Figure 4.7: Run ACEI from AIDA

When the ACEI is invoked, the first task is to evaluate if there are corners to run. If the option to run corners were given as input, then the netlist will be replicated for each corner and each thread will simulate one netlist at the time, until the queue that hold them is empty. Otherwise, if the --corners option was not invoked, then only the given netlist is simulated, having no reason to launch any thread. After simulating all netlists, the output file is written going through the measures dictionary. In Figure 4.8, the ACEI main method is presented:

Figure 4.8: Main() method of the ACEI developed

4.2.2 Netlists Generation to Run Corners

Considering that using altermod to run corners entails replicating all libraries, replacing the labels defined by the values for each library and repeating the commands to extract all measures needed, for each corner, as demonstrated in the third chapter, the best solution is replicating the original netlist and make all necessary changes to run each corner, easing the user experience. The following schema exemplifies how the netlist are generated through the file that contains the corners:

Original Netlist

Copy of the Copy of the Copy of the Copy of the original netlist original netlist original netlist original netlist

.ALTER .ALTER .ALTER .ALTER corners +_vdd=1.5 .lib FF .lib SS .TEMP 50 .TEMP 0

+_vdd=3

Queue

Original netlist Original

Netlist corner 2 corner Netlist Netlist 1 corner Netlist

Netlist 0 corner Netlist 3 corner Netlist

Figure 4.9: Fill queue that contains the netlists to simulate (typical plus corners)

As represented in Figure 4.9, generating the netlists to run the corners, implies copying the original netlist. After that, according to the corner that will be simulated, each copy of the original netlist will be adapted, taking into account the type of corner:

• Change a library: the python script looks for the include card, which is responsible for including the library, and replaces it for the new library; • Change a parameter value: the script copies the design_var.inc file (which includes all circuit variables), finds the declaration of that parameter in that file and changes its value. Following that, the netlist has also to be changed to include, not the original design_var.inc file, but the file copied and changed; • Change the temperature: the desired temperature is assigned to the .TEMP card.

The ACEI developed is also prepared to run corners which alters libraries, parameters and/or temperatures, in the same netlist. An example of a corners.inc file, in which, for each corner, temperatures and parameters are modified, is demonstrated in Figure 4.10:

Figure 4.10: Corners.inc example changing temperatures and parameter values simultaneously

The method that replicate the netlists according to the corners.inc file is presented in Figure 4.11:

Figure 4.11: Method to replicate the original netlist according to the corners

35 Basically, the corners.inc file is read line by line and a dictionary holding each corner is filled. Then, for each key of this dictionary, a copy of the original netlist is performed:

Figure 4.12: Method to copy the original netlist

For each copy of the netlist, the corner changes are divided into two different lists: one that holds the temperatures and libraries to change, and another one to keep the new parameter values. For both lists, the copy of the original netlist has to be changed according to the corner. However, for the corners which modify parameter values, the design_var.inc file needs also to be cloned, since the assignment of the new values is performed in this new file. The only modification that needs to be addressed in the copied netlist is to include the new copy of design_var.inc file inside the respective netlist, instead of the original one.

Although the netlist and the design_var.inc files have nothing in common, both are changed using the same method, reusing the code, as described in Figure 4.13. This method finds a pattern in the specified file and replaces it for the new value passed as input:

Figure 4.13: Method to change a file searching for a pattern and replace the value for a new one

4.2.3 Run Each Corner

The main idea of running each corner in parallel is to facilitate the user experience, since following this approach, the user steps to optimize a circuit in AIDA will remain the same as optimizing a circuit using ELDO as the simulation engine. The queue that hold the netlists was built to allow the parallelization of the simulations. The following schema presented in Figure 4.14, shows how the script behaves until there are no more netlists to run.

Output.dat NGSpice

Measures Output_Crn0.dat Dictionary

Output_Crn1.dat

…

Output_CrnN.dat Queue

…

Original netlist Original

Netlist corner 2 corner Netlist Netlist 1 corner Netlist 0 corner Netlist

Thread A

Thread B Main Thread

Thread C ACEI_OUT.dat Thread D

Figure 4.14: Developed ACEI workflow

Basically, having a queue filled with netlists (original netlist plus netlists adapted according to the corners), each thread will pick up a netlist from the queue and executes NGSpice. The outputs obtained in each simulation will then be parsed to a dictionary, whose keys are the names of the performance measures and the values are the corresponding values. This dictionary will hold all the measures from all netlists simulated. As soon as all netlists are simulated, all threads will join the main thread, which will go over the measures dictionary and write the output file, according to the structure defined.

In Figure 4.15, the method that each thread performs is presented. Note that the simObj is a tuple which is composed by an index, a netlist name and corner name. When all netlists are simulated, the measures of each simulation are stored in a dictionary and then added to a list, which will hold the measures of all simulations performed.

Figure 4.15: Method executed by each thread to simulate netlists in parallel

4.2.4 Generate Output File

The outputs of each simulation are registered in a list of dictionaries. Each dictionary holds the measures of each simulation. The dictionary keys are the names of the measures and the values are the corresponding outputs. The measures of each simulation are recorded in a certain index of the list which, in case of corners simulation, corresponds to the order of the corners in corners.inc file. An example of the output given by NGSpice, with the measures obtained from the AC and OP analyses is shown in Figure 4.16.

Figure 4.16: NGSpice Output

38 When all netlists are executed, the main thread will go through the list and write the output file, printing each measure name and its corresponding value, as shown in Figure 4.17:

Figure 4.17: Methods to write the output file which will be AIDA's input

The output file, generated by the interface developed, is presented in Figure 4.18. In this example, five corners were run and so, as explained before, all measures are indicated in the first line, with its labels separated by the Cornr# tag (highlighted with a blue dashed line) and, in the second line, the values of the respective measures are in the same order as its labels and separated by an ascending number starting at 0 (illustrated with an orange dashed line).

Figure 4.18: Output file of ACEI for NGSpice

39 4.3 Conclusions

This chapter describes how each requirement defined in the third chapter was implemented, along with the corresponding methods of the ACEI. Firstly, a demonstration in how to run the ACEI, with or without the option of running corners was presented. Then the replication of the netlists is presented, as well as, how the copied netlists are modified according to the corners. Lastly, the generation of the output file is drawn.

40 Results

In this chapter, the NGSpice integration in AIDA is tested, optimizing two different circuits both in time and frequency domains. Each circuit will be optimized using ELDO and NGSpice as simulators, so that the results can be compared. The POFs obtained for each circuit will be presented and a statistical analysis will be applied to all performance measures obtained in each optimization, comparing both simulators, NGSpice and ELDO.

5.1 Circuits Optimization

The AIDA framework optimizes circuits using multi-objective multi-constraint optimization techniques. Nevertheless, uses commercial simulators, as ELDO or HSPICE to evaluate the circuits performance, which prevents its dissemination among the academic community. The NGSpice integration in AIDA appears as the solution to abovementioned limitation, since is an open-source engine. However, this simulator will only be a powerful tool, if the outputs gathered are similar to the ones obtained with the current AIDA’s simulators.

In order to compare the performance of both simulators, ELDO and NGSpice, two different circuits will run, in each simulator. The circuits selected are presented in Figure 5.1 and Figure 5.2, along with the testbenches used for both circuits in Figure 5.3.

Figure 5.1: Folded Voltage-Combiners Biased Amplifier circuit [44]

Figure 5.2: Dynamic Voltage-Combiners Biased OTA circuit [45]

Figure 5.3: Testbenches for both circuits

42 The testbench for AC and OP analyses is the circuit on top of Figure 5.3 (Frequency Domain). The OP measures are gathered in open-loop once in closed-loop, the feedback itself will reinforce the behavior at the operating point. The analysis in time domain is performed in closed-loop, as represented in the circuit in the bottom of Figure 5.3. In order to simplify the analysis, the gain is unitary, since the injected signals have sufficiently high amplitude, having no need to add a scale factor to the analysis.

The corners simulated are presented in Figure 5.4 and Figure 5.5, for circuits in Figure 5.1 and Figure 5.2, respectively.

Figure 5.4: Corners.inc file optimizing Folded Voltage-Combiners Biased Amplifier Circuit

Figure 5.5: Corners.inc file optimizing Dynamic Voltage-Combiners Biased OTA Circuit

The design variables for each circuit, are shown in Table 5.1 and Table 5.2, along with their minimum and maximum values and the step applied. The number of generations for the typical library and for corners are also presented in Table 5.3 and Table 5.4.

43 Table 5.1: Design Variables - Folded Voltage- Table 5.2: Design Variables - Dynamic Voltage- Combiners Biased Amplifier Circuit Combiners Biased OTA Circuit

Variables Min Value Step Max Value Variables Min Value Step Max Value wpmbiasp wp5 2.00E-06 1.00E-07 2.98E-04 2.60E-06 1.00E-07 1.00E-04 wp5 wp3 2.00E-06 1.00E-07 2.98E-04 2.60E-06 1.00E-07 1.00E-04 wp4 wp1 2.00E-06 1.00E-07 2.98E-04 2.60E-06 1.00E-07 1.00E-04 wp1 wp0 2.00E-06 1.00E-07 2.98E-04 2.60E-06 1.00E-07 1.00E-04 wp0 wn7 2.00E-06 1.00E-07 2.98E-04 2.60E-06 1.00E-07 1.00E-04 wnmbiasp wn5 2.00E-06 1.00E-07 2.98E-04 2.60E-06 1.00E-07 1.00E-04 wnmbiasn wn3 2.00E-06 1.00E-07 2.98E-04 2.60E-06 1.00E-07 1.00E-04 wn8 wn2 2.00E-06 1.00E-07 2.98E-04 2.60E-06 1.00E-07 1.00E-04 wn6 wn1 2.00E-06 1.00E-07 2.98E-04 2.60E-06 1.00E-07 1.00E-04 wn4 nfp5 1.00E+00 2.00E+00 1.60E+01 2.60E-06 1.00E-07 1.00E-04 wn0 nfp3 1.00E+00 2.00E+00 1.60E+01 2.60E-06 1.00E-07 1.00E-04 nfpmbiasp nfp1 1.00E+00 2.00E+00 1.60E+01 1 2 16 nfp5 nfp0 1.00E+00 2.00E+00 1.60E+01 1 2 16 nfp4 nfn7 1.00E+00 2.00E+00 1.60E+01 1 2 16 nfp1 nfn5 1.00E+00 2.00E+00 1.60E+01 1 2 16 nfp0 nfn3 1.00E+00 2.00E+00 1.60E+01 1 2 16 nfnmbiasp nfn2 1.00E+00 2.00E+00 1.60E+01 1 2 16 nfnmbiasn nfn1 1.00E+00 2.00E+00 1.60E+01 1 2 16 nfn8 lp1 3.60E-07 1.00E-08 2.36E-06 1 2 16 nfn6 lp0 3.60E-07 1.00E-08 2.36E-06 1 2 16 nfn4 ln7 3.60E-07 1.00E-08 2.36E-06 1 2 16 nfn0 ln5 3.60E-07 1.00E-08 2.36E-06 1 2 16 lpmbiasp ln3 3.60E-07 1.00E-08 2.36E-06 1.20E-07 1.00E-08 5.00E-05 lp5 ln1 3.60E-07 1.00E-08 2.36E-06 1.20E-07 1.00E-08 5.00E-05 lp4 1.20E-07 1.00E-08 5.00E-05

lp1 1.20E-07 1.00E-08 5.00E-05 lp0 1.20E-07 1.00E-08 5.00E-05 lnmbiasp 1.20E-07 1.00E-08 5.00E-05 lnmbiasn 1.20E-07 1.00E-08 5.00E-05 ln8 1.20E-07 1.00E-08 5.00E-05 ln6 1.20E-07 1.00E-08 5.00E-05

ln4 1.20E-07 1.00E-08 5.00E-05

ln0 1.20E-07 1.00E-08 5.00E-05

nfp7 1 2 16 wp7 2.60E-06 1.00E-07 1.00E-04 lp7 1.20E-07 1.00E-08 5.00E-05

44 Table 5.3: Optimization options – Folded Voltage-Combiners Biased Amplifier Circuit

Number of generations Population Size

Typical 300 256

Corners 200 128

Table 5.4: Optimization options - Dynamic Voltage-Combiners Biased OTA Circuit

Number of generations Population Size

Typical 300 128

Corners 300 128

5.2 NGSpice vs ELDO

The comparison between ELDO and NGSpice can be done establishing a metric capable of comparing both simulators directly. This metric can be the average execution time of each simulator, for each circuit. Note that the comparison made is not directly between simulators, i.e., ELDO versus NGSpice, since the latter only can present the same results as ELDO combined with the interface developed, as mentioned before. All circuits were simulated in the same computer for both simulators. The results of both circuits are presented in the following tables:

Table 5.5: Runtimes for Folded Voltage-Combiners Biased Amplifier circuit

Table 5.6: Runtimes for Dynamic Voltage-Combiners Biased OTA circuits

The tables above register fifteen runtimes for both tools (ELDO and ACEI invoking NGSpice), simulating each circuit, for the typical library and for corners, performing AC and OP analysis. The results are consistent for all circuits, i.e., the average runtime for the typical library using ELDO as simulator is always less then when invoking the ACEI to run them in NGSpice. However, regarding the corners, the ACEI is always faster than ELDO.

45 These results also reflect that when invoking the ACEI, the average runtimes of running only the typical solution and all corners are quite similar. This is explained by the structure of the ACEI, since the difference between running only the typical solution and the typical plus the corners, is the replication of the netlists, once the NGSpice for the corners are invoked in parallel, avoiding the wasting of time running corner by corner. Note that all these results are obtained using version 28 of the NGSpice, since with older versions do not output accurate results.

The work developed throughout this thesis is especially important considering its impact on AIDA’s dissemination. Before NGSpice, there were two main constraints which inhibited its divulgation, namely the costs associated with the simulation engine AIDA supports and the limited number of licenses provided. In addition, although ELDO allows to simulate circuits in parallel, this parallelism is limited by the number of licenses available.

5.3 AIDA – Circuits Optimization

The following subsections present the circuits optimization in AIDA, starting by the project setup. Then AIDA’s outputs will be presented and the results will be compared statistically. AIDA-C’s output is a set of Pareto optimal circuits that are feasible, meaning that the solutions obtained comply with all the constraints and represent the tradeoffs between the different optimization objectives.

5.3.1 Project Setup

As soon as a project is opened, the GUI pops up, as represented in Figure 5.6. Firstly, the project is validated in order to verify the setup integrity, which includes validating the design.xml file, pressing the button marked with a green circle in Figure 5.6. After that, the optimization is ready to run, i.e., the button highlighted in orange should be pressed.

Figure 5.6: AIDA GUI – Validation and Run buttons

46 During the optimization process, AIDA provides its evolution, monitoring it using plots, which will be updated during the optimization and also provide information about its current state, as shown in Figure 5.7. This plot is denominated AIDA-C Convergence plot, which shows the number of non-dominated solutions. This information is relevant to evaluate the number of different solutions found and the sum of normalized constraint violations for the best element, which indicates how far the best solution is from complying with all the specifications. Reaching zero means that one or more feasible solutions were found [34]. Note that, in Figure 5.7, the red solutions are infeasible, and the green solutions are feasible.

Figure 5.7: AIDA-C Convergence Plot

5.3.2 Circuits Optimization

Firstly, both circuits were optimized, performing analyses both in frequency and time domains, for each simulator. As AIDA optimizes circuits using a genetic algorithm based on a stochastic process and hashmaps, although each optimization starts with the same seed, the design variables simulated will differ among simulations and simulators. This implies that the measures obtained by each simulator will differ, which does not allow to compare directly the outputs gathered, since circuits with different design variables are being simulated.

Taking this into account, the only way to compare both simulators is to simulate the same points optimized in AIDA with ELDO in NGSpice and vice-versa, and compare the measures obtained, not only for the typical library, but also for some corners.

When multiple objectives are considered, the output cannot be one single solution due to not being possible to define a solution better than another, since it is not a matter of one single performance measure being better. Instead, what is obtained is a set of optimal design trade-off solutions, commonly designated as a POF (Pareto Optimal Front). These solutions are non-dominated solutions, which are the feasible solutions which do not have any other solution better than the current one in a certain objective function without worsening another objective function.

47 5.3.2.1 Pareto Optimal Front Obtained

The objectives defined for both circuits were maximizing both the Gain DC and the GBW and minimizing the IDD. The following figures show the POFs obtained simulating both circuits, which are the optimal points considering the objectives defined, according to the Pareto Criterion.

As mentioned above, the points simulated while optimizing the circuits using ELDO were then simulated in NGSpice and vice-versa, so that the results would be comparable. Note that the number of the corner that was simulated is in the same order as the respective corners.inc files, i.e., the corner 0 is the first corner of each corners.inc file and so on, for each circuit.

• POFs obtained simulating ELDO points in both simulators:

Figure 5.8: POFs obtained simulating ELDO points (Folded Voltage-Combiners Biased Amplifier Circuit)

Figure 5.9: POFs obtained simulating ELDO points (Dynamic Voltage-Combiners Biased OTA Circuit)

48 • POFs obtained simulating NGSpice points in both simulators:

Figure 5.10: POFs obtained simulating NGSpice points (Folded Voltage-Combiners Biased Amplifier Circuit

Figure 5.11: POFs obtained simulating NGSpice points (Dynamic Voltage-Combiners Biased OTA Circuit)

In each graphic, the POFs in multiple colours are the points which were optimized in AIDA by the original simulator and the blue POFs are the ones obtained using the other simulator. The graphics in Figure 5.8 and Figure 5.9 present the POFs obtained for each circuit, considering that the points simulated in ELDO were also simulated in NGSpice, meaning that the POFs in multiple colours are the ones obtained using ELDO as AIDA’s simulation engine and the blue ones are when NGSpice simulated the same points. On the other hand, the graphics in Figure 5.10 and Figure 5.11 represent the POFs, for each circuit, which result from simulating NGSpice points in both simulators, which entails that the POFs in multiple colours are the ones using NGSpice as simulator and the blue ones are when ELDO simulates the same points.

49 All POFs presented above prove that if the optimizations were performed simulating the same points, the outputs obtained from both simulators, ELDO and NGSpice, would be very similar, since when analysing these graphics, most of the blue points are overlapping the other solutions, not only for the typical library, but also for all corners.

5.3.2.2 Statistical Analysis

In order to strengthen these conclusions, a statistical analysis over all the performance measures obtained will be presented. The values of the performance measures gathered from both simulators are paired samples, since these values are obtained for the same point. For each simulation of these circuits (typical library plus corners), all measures will be compared performing a statistical analysis. For each measure, in the first place, the relative error of each measure will be determined, i.e., the absolute value of the differences between the outputs of both simulators are obtained. Considering the points generated when optimizing the circuits using ELDO, for each measure, the denominators of the mentioned relative errors are ELDO’s outputs, while for the points generated using NGSpice as AIDA’s evaluation engine, the denominators of the referred relative errors are NGSpice’s outputs.

Following that, 95% confidence intervals for the mean value of the mentioned relative errors were performed, in order to evaluate with high probability, the variations of the errors between the simulators, for each measure. As all the samples associated with each measure and each simulation of the circuit have high dimension, in statistical terms (n > 30), the respective sample mean of the relative errors of each one of them (푋̅) has an asymptotically normal distribution due to the Central Limit Theorem, so the variable, 푋̅−휇 (5.1) 푍 = 푆 ~̇ 푁(0,1), √푛 can be used to construct the 95% random confidence interval for the mean value (µ) of the relative errors:

]X̅ − 1.96 S ; X̅ + 1.96 S [, (5.2) √푛 √푛 where S is the sample standard deviation of the relative errors. For each observed sample of the relative errors, a concrete 95% confidence interval is obtained:

]x̅ − 1.96 s ; x̅ + 1.96 s [, (5.3) √푛 √푛 being x̅ and s the point estimates of the sample mean and standard deviation, respectively. All the 95% concrete confidence intervals obtained for each measure and for each simulation of both circuits are presented in four tables. As these intervals are obtained from random intervals of high confidence level (95%), there is a high probability that they contain the real mean value of the relative errors between the measures. To obtain the 95% confidence intervals, a R [35] script was developed.

50 The results of Table 5.7 and Table 5.9 come from points generated during AIDA’s optimization using ELDO as the simulation engine, which were then used in NGSpice, for circuits represented in Figure 5.1 and Figure 5.2, respectively. On the other hand, in Table 5.8 and Table 5.10, the results are drawn from points generated during AIDA’s optimization using NGSpice as simulator, and then applied in ELDO, for the same circuits. Note that for the circuit presented in Figure 5.1, eight corners are considered, while for the other one, in Figure 5.2, only four corners run.

Generally, all the results presented prove that the relative errors between both simulators, ELDO and NGSpice, are negligible since, with high probability, the upper limits of all deterministic confidence intervals obtained, for all performance measures are less than 13% and 0.3% for circuits in Figure 5.1 and Figure 5.2, respectively, since these intervals are based on 95% random confidence intervals. In fact, if infinite deterministic intervals were construct based on samples of the same size, it is expected that 95% of those intervals real contain the true mean value of the relative errors between both simulators, ELDO and NGSpice.

The maximum upper limit of the intervals obtained for the relative errors of circuit in Figure 5.1 is higher due to the slewrate measure. However, these differences are acceptable since, in ELDO, to calculate the slewrate the user only needs to invoke a command and the simulator handles how this measure is calculated. Thus, although the measure values are similar, there is no way to know exactly how this measure is obtained in ELDO, meaning that meaning that this measure’s value can be slightly different. Looking at the other performance measures, the upper limits of the relative errors are negligible, less than 0.1%.

Considering the results presented, the integration of NGSpice in AIDA is validated since both graphs and 95% confidence intervals prove that the performance measures obtained are very similar. These results are extremely important to ensure that, from now on, AIDA can be disseminated without any constraints which are imposed by commercial simulators, namely the limited number of licenses available and the costs associated.

51 Table 5.7: 95% Confidence Intervals for Relative Errors - ELDO points (Folded Voltage-Combiners Biased Amplifier Circuit)

Measures Typical Corner 0 Corner 1 Corner 2 Corner 3 Corner 4 Corner 5 Corner 6 Corner 7 delta_mnm1 ]0.055%;0.069%[ ]0.009%;0.012%[ ]0.011%;0.015%[ ]0.013%;0.018%[ ]0.014%;0.019%[ ]0.009%;0.014%[ ]0.009%;0.014%[ ]0.013%;0.018%[ ]0.008%;0.012%[ delta_mnm2 ]0.035%;0.043%[ ]0.007%;0.009%[ ]0.006%;0.008%[ ]0.005%;0.007%[ ]0.005%;0.007%[ ]0.005%;0.007%[ ]0.006%;0.008%[ ]0.006%;0.009%[ ]0.004%;0.006%[ delta_mnm3 ]0.055%;0.07%[ ]0.002%;0.009%[ ]0.004%;0.012%[ ]0.005%;0.02%[ ]0.005%;0.018%[ ]0.003%;0.011%[ ]0.008%;0.027%[ ]0.003%;0.013%[ ]0.002%;0.009%[ delta_mnm4 ]0.053%;0.068%[ ]0.002%;0.009%[ ]0.004%;0.012%[ ]0.005%;0.02%[ ]0.005%;0.018%[ ]0.003%;0.011%[ ]0.009%;0.027%[ ]0.003%;0.013%[ ]0.002%;0.008%[ delta_mnm5 ]0.098%;0.122%[ ]0.001%;0.004%[ ]0.001%;0.005%[ ]0.001%;0.004%[ ]0.004%;0.01%[ ]0.003%;0.009%[ ]0.001%;0.005%[ ]0.002%;0.01%[ ]0.002%;0.007%[ delta_mnm6 ]0.09%;0.113%[ ]0.001%;0.004%[ ]0.002%;0.006%[ ]0.001%;0.004%[ ]0.003%;0.01%[ ]0.002%;0.009%[ ]0.001%;0.005%[ ]0.003%;0.01%[ ]0.002%;0.007%[ delta_mnm7 ]0.101%;0.12%[ ]0%;0.003%[ ]0.003%;0.008%[ ]0.003%;0.008%[ ]0.005%;0.012%[ ]0.003%;0.007%[ ]0.002%;0.007%[ ]0.002%;0.006%[ ]0.001%;0.005%[ delta_mnm8 ]0.099%;0.119%[ ]0.001%;0.004%[ ]0.003%;0.008%[ ]0.003%;0.008%[ ]0.005%;0.012%[ ]0.003%;0.008%[ ]0.003%;0.008%[ ]0.002%;0.006%[ ]0.001%;0.005%[ delta_mpm0 ]0.06%;0.074%[ ]0.001%;0.002%[ ]0.001%;0.003%[ ]0.001%;0.004%[ ]0.002%;0.006%[ ]0.001%;0.003%[ ]0.001%;0.003%[ ]0.001%;0.003%[ ]0.001%;0.003%[ delta_mpm1 ]0.071%;0.087%[ ]0.001%;0.003%[ ]0%;0.002%[ ]0.001%;0.003%[ ]0.001%;0.005%[ ]0%;0.001%[ ]0%;0.001%[ ]0%;0.002%[ ]0.001%;0.004%[ delta_mpm3 ]0.055%;0.069%[ ]0.006%;0.009%[ ]0.016%;0.021%[ ]0.01%;0.014%[ ]0.029%;0.039%[ ]0.025%;0.033%[ ]0.006%;0.009%[ ]0.01%;0.015%[ ]0.014%;0.018%[ delta_mpm4 ]0.058%;0.073%[ ]0.006%;0.009%[ ]0.016%;0.022%[ ]0.01%;0.014%[ ]0.029%;0.039%[ ]0.025%;0.032%[ ]0.006%;0.01%[ ]0.01%;0.015%[ ]0.013%;0.018%[ delta_mpm5 ]0.033%;0.042%[ ]0.002%;0.009%[ ]0.002%;0.006%[ ]0.002%;0.004%[ ]0.003%;0.009%[ ]0.004%;0.008%[ ]0.002%;0.008%[ ]0.001%;0.009%[ ]0.003%;0.012%[ delta_mpm6 ]0.034%;0.045%[ ]0.002%;0.009%[ ]0.003%;0.008%[ ]0.002%;0.005%[ ]0.003%;0.009%[ ]0.004%;0.008%[ ]0.002%;0.008%[ ]0.002%;0.01%[ ]0.003%;0.012%[ fom ]0.046%;0.057%[ ]0%;0.002%[ ]0.001%;0.003%[ ]0.002%;0.004%[ ]0.001%;0.005%[ ]0.001%;0.003%[ ]0.001%;0.002%[ ]0.003%;0.006%[ ]0.003%;0.007%[ gbw ]0.089%;0.111%[ ]0.001%;0.005%[ ]0.001%;0.004%[ ]0%;0.003%[ ]0.001%;0.005%[ ]0.001%;0.004%[ ]0.002%;0.006%[ ]0.002%;0.007%[ ]0.005%;0.01%[ gdc ]0.03%;0.037%[ ]0%;0.002%[ ]0%;0.001%[ ]0%;0.001%[ ]0%;0.002%[ ]0%;0.001%[ ]0%;0.001%[ ]0%;0.001%[ ]0%;0.001%[ gps ]0.037%;0.06%[ ]0%;0.002%[ ]0.001%;0.002%[ ]0%;0.001%[ ]0%;0.004%[ ]0.001%;0.008%[ ]0%;0.002%[ ]0%;0.002%[ ]0%;0.002%[ idd ]0.041%;0.05%[ ]0%;0.002%[ ]0%;0.002%[ ]0%;0.002%[ ]0%;0.002%[ ]0%;0.001%[ ]0%;0.002%[ ]0%;0.001%[ ]0%;0.002%[ outswing ]0.171%;0.209%[ ]0%;0.004%[ ]0.001%;0.007%[ ]0%;0.005%[ ]0%;0.006%[ ]0%;0.005%[ ]0.003%;0.009%[ ]0%;0.005%[ ]0%;0.005%[ pm ]0.027%;0.033%[ ]0.001%;0.003%[ ]0.001%;0.002%[ ]0.001%;0.002%[ ]0.001%;0.002%[ ]0%;0.001%[ ]0%;0.001%[ ]0.049%;0.055%[ ]0.044%;0.05%[ psrr ]0.031%;0.04%[ ]0%;0.001%[ ]0.001%;0.002%[ ]0%;0.001%[ ]0%;0.001%[ ]0%;0.001%[ ]0%;0.001%[ ]0%;0.001%[ ]0%;0.001%[ slewrate ]7.234%;8.855%[ ]2.99%;3.981%[ ]5.929%;7.434%[ ]8.982%;11.189%[ ]10.631%;12.885%[ ]5.152%;6.507%[ ]9.472%;11.076%[ ]8.112%;10.192%[ ]6.395%;7.992%[ vov_mnm1 ]0.027%;0.034%[ ]0.002%;0.004%[ ]0.002%;0.004%[ ]0.002%;0.004%[ ]0.002%;0.004%[ ]0.003%;0.005%[ ]0.003%;0.005%[ ]0.002%;0.003%[ ]0.001%;0.003%[ vov_mnm2 ]0.027%;0.033%[ ]0.001%;0.003%[ ]0.003%;0.004%[ ]0.003%;0.005%[ ]0.003%;0.005%[ ]0.002%;0.004%[ ]0.002%;0.004%[ ]0.003%;0.005%[ ]0.003%;0.005%[ vov_mnm3 ]0.036%;0.058%[ ]0.002%;0.004%[ ]0.001%;0.003%[ ]0.002%;0.004%[ ]0.003%;0.005%[ ]0.003%;0.005%[ ]0.001%;0.003%[ ]0.002%;0.004%[ ]0.001%;0.003%[ vov_mnm4 ]0.035%;0.052%[ ]0.002%;0.004%[ ]0.002%;0.004%[ ]0.002%;0.004%[ ]0.003%;0.005%[ ]0.003%;0.005%[ ]0.002%;0.004%[ ]0.002%;0.004%[ ]0.002%;0.004%[ vov_mnm5 ]0.155%;0.192%[ ]0.001%;0.002%[ ]0.002%;0.008%[ ]0%;0.006%[ ]0.001%;0.005%[ ]0.001%;0.005%[ ]0.001%;0.004%[ ]0.002%;0.008%[ ]0.001%;0.008%[ vov_mnm6 ]0.156%;0.191%[ ]0.001%;0.002%[ ]0.002%;0.008%[ ]0.001%;0.007%[ ]0.001%;0.006%[ ]0.001%;0.005%[ ]0.001%;0.004%[ ]0.001%;0.007%[ ]0.001%;0.007%[ vov_mnm7 ]0.13%;0.161%[ ]0%;0.004%[ ]0%;0.004%[ ]0.001%;0.005%[ ]0.001%;0.005%[ ]0.001%;0.005%[ ]0%;0.005%[ ]0.001%;0.006%[ ]0%;0.004%[ vov_mnm8 ]0.13%;0.161%[ ]0%;0.004%[ ]0%;0.004%[ ]0.001%;0.005%[ ]0.001%;0.005%[ ]0.001%;0.005%[ ]0%;0.005%[ ]0.001%;0.006%[ ]0%;0.004%[ vov_mpm0 ]0.096%;0.122%[ ]0.002%;0.006%[ ]0.002%;0.008%[ ]0.003%;0.008%[ ]0%;0.004%[ ]0.001%;0.004%[ ]0.001%;0.004%[ ]0%;0.003%[ ]0.001%;0.004%[ vov_mpm1 ]0.141%;0.181%[ ]0.004%;0.012%[ ]0%;0.003%[ ]0.001%;0.006%[ ]0.002%;0.01%[ ]-0.001%;0.003%[ ]-0.001%;0.003%[ ]0%;0.004%[ ]0.001%;0.007%[ vov_mpm3 ]0.15%;0.182%[ ]0.003%;0.011%[ ]0.002%;0.009%[ ]0.001%;0.006%[ ]0.003%;0.009%[ ]0.001%;0.005%[ ]0.001%;0.007%[ ]0.001%;0.005%[ ]0.002%;0.008%[ vov_mpm4 ]0.15%;0.182%[ ]0.003%;0.011%[ ]0.002%;0.009%[ ]0.001%;0.006%[ ]0.003%;0.009%[ ]0.001%;0.005%[ ]0.001%;0.007%[ ]0.001%;0.005%[ ]0.002%;0.008%[ vov_mpm5 ]0.046%;0.057%[ ]0.001%;0.004%[ ]0.001%;0.003%[ ]0.001%;0.003%[ ]0.001%;0.002%[ ]0.001%;0.003%[ ]0%;0.002%[ ]0.001%;0.003%[ ]0.001%;0.004%[ vov_mpm6 ]0.047%;0.058%[ ]0.001%;0.004%[ ]0.001%;0.003%[ ]0.001%;0.003%[ ]0.001%;0.003%[ ]0.001%;0.003%[ ]0%;0.002%[ ]0.001%;0.003%[ ]0.001%;0.003%[

52 Table 5.8: 95% Confidence Intervals for Relative Errors - NGSpice points (Folded Voltage-Combiners Biased Amplifier Circuit)

Measures Typical Corner 0 Corner 1 Corner 2 Corner 3 Corner 4 Corner 5 Corner 6 Corner 7 delta_mnm1 ]0.011%;0.011%[ ]0.009%;0.013%[ ]0.011%;0.015%[ ]0.007%;0.012%[ ]0.011%;0.016%[ ]0.006%;0.011%[ ]0.006%;0.011%[ ]0.015%;0.019%[ ]0.011%;0.015%[ delta_mnm2 ]0.006%;0.006%[ ]0.007%;0.01%[ ]0.007%;0.01%[ ]0.006%;0.009%[ ]0.006%;0.008%[ ]0.007%;0.01%[ ]0.004%;0.007%[ ]0.006%;0.008%[ ]0.005%;0.008%[ delta_mnm3 ]0.001%;0.007%[ ]0.005%;0.013%[ ]0.002%;0.005%[ ]0.001%;0.004%[ ]0.004%;0.016%[ ]0.002%;0.007%[ ]0.005%;0.014%[ ]0.008%;0.023%[ ]0.004%;0.013%[ delta_mnm4 ]0.001%;0.007%[ ]0.005%;0.013%[ ]0.002%;0.005%[ ]0.001%;0.004%[ ]0.003%;0.016%[ ]0.002%;0.007%[ ]0.005%;0.014%[ ]0.009%;0.023%[ ]0.004%;0.013%[ delta_mnm5 ]0.001%;0.002%[ ]0.001%;0.004%[ ]0.003%;0.009%[ ]0.003%;0.008%[ ]0.004%;0.01%[ ]0.003%;0.007%[ ]0.002%;0.008%[ ]0.003%;0.016%[ ]0.003%;0.009%[ delta_mnm6 ]0.001%;0.002%[ ]0.001%;0.005%[ ]0.003%;0.009%[ ]0.003%;0.008%[ ]0.004%;0.01%[ ]0.003%;0.007%[ ]0.002%;0.007%[ ]0.003%;0.016%[ ]0.003%;0.009%[ delta_mnm7 ]0.002%;0.003%[ ]0.001%;0.005%[ ]0.001%;0.005%[ ]0.003%;0.008%[ ]0.004%;0.01%[ ]0.001%;0.005%[ ]0%;0.002%[ ]0.002%;0.008%[ ]0.001%;0.004%[ delta_mnm8 ]0.002%;0.003%[ ]0.001%;0.005%[ ]0.001%;0.004%[ ]0.003%;0.008%[ ]0.004%;0.01%[ ]0.002%;0.006%[ ]0%;0.002%[ ]0.002%;0.008%[ ]0.001%;0.004%[ delta_mpm0 ]0%;0.001%[ ]0%;0.002%[ ]0.002%;0.005%[ ]0%;0.002%[ ]0.001%;0.004%[ ]0.001%;0.003%[ ]0.001%;0.003%[ ]0.002%;0.006%[ ]0%;0.001%[ delta_mpm1 ]0%;0%[ ]0%;0.002%[ ]0%;0.002%[ ]0%;0.002%[ ]0.001%;0.005%[ ]0%;0.001%[ ]0%;0.001%[ ]0%;0.002%[ ]0%;0.002%[ delta_mpm3 ]0.014%;0.015%[ ]0.006%;0.01%[ ]0.017%;0.024%[ ]0.011%;0.015%[ ]0.041%;0.053%[ ]0.032%;0.04%[ ]0.005%;0.009%[ ]0.014%;0.02%[ ]0.013%;0.018%[ delta_mpm4 ]0.014%;0.015%[ ]0.006%;0.01%[ ]0.017%;0.024%[ ]0.011%;0.015%[ ]0.042%;0.054%[ ]0.033%;0.041%[ ]0.005%;0.009%[ ]0.014%;0.021%[ ]0.013%;0.019%[ delta_mpm5 ]0.002%;0.003%[ ]0.001%;0.009%[ ]0.002%;0.009%[ ]0.001%;0.003%[ ]0.003%;0.006%[ ]0.003%;0.005%[ ]0.002%;0.006%[ ]0.002%;0.008%[ ]0.003%;0.009%[ delta_mpm6 ]0.002%;0.003%[ ]0.002%;0.011%[ ]0.002%;0.009%[ ]0.001%;0.003%[ ]0.003%;0.006%[ ]0.003%;0.006%[ ]0.002%;0.005%[ ]0.002%;0.008%[ ]0.003%;0.009%[ fom ]0%;0.001%[ ]0.001%;0.003%[ ]0.001%;0.004%[ ]0.002%;0.004%[ ]0.002%;0.005%[ ]0.001%;0.005%[ ]0.001%;0.002%[ ]0.005%;0.008%[ ]0.006%;0.01%[ gbw ]0%;0.001%[ ]0%;0.004%[ ]0.001%;0.004%[ ]0.001%;0.004%[ ]0.002%;0.006%[ ]0.001%;0.004%[ ]0.002%;0.007%[ ]0.002%;0.006%[ ]0.007%;0.012%[ gdc ]0%;0%[ ]0%;0.002%[ ]0%;0.001%[ ]0%;0%[ ]0%;0.001%[ ]0%;0.001%[ ]0%;0.001%[ ]0%;0.002%[ ]0%;0.002%[ gps ]0%;0%[ ]0.001%;0.004%[ ]0%;0.001%[ ]0%;0.001%[ ]0%;0.003%[ ]0%;0.004%[ ]0.001%;0.005%[ ]0%;0.002%[ ]0%;0.003%[ idd ]0%;0%[ ]0%;0.002%[ ]0%;0.001%[ ]0%;0.001%[ ]0%;0.001%[ ]0%;0.002%[ ]0%;0.002%[ ]0%;0.001%[ ]0%;0.002%[ outswing ]0%;0%[ ]0.001%;0.007%[ ]0.002%;0.008%[ ]0.001%;0.006%[ ]0%;0.005%[ ]0.001%;0.008%[ ]0%;0.005%[ ]-0.001%;0.002%[ ]0.002%;0.009%[ pm ]0.001%;0.001%[ ]0.001%;0.003%[ ]0.001%;0.002%[ ]0.001%;0.002%[ ]0%;0.001%[ ]0.001%;0.002%[ ]0.001%;0.003%[ ]0.05%;0.056%[ ]0.046%;0.051%[ psrr ]0%;0%[ ]0%;0%[ ]0%;0.001%[ ]0%;0%[ ]0%;0.001%[ ]0%;0.001%[ ]0%;0.003%[ ]0%;0.001%[ ]0%;0%[ slewrate ]6.471%;8.056%[ ]1.738%;2.426%[ ]5.42%;7.14%[ ]7.885%;9.445%[ ]8.583%;10.522%[ ]6.187%;7.666%[ ]10.596%;12.527%[ ]7.757%;9.342%[ ]6.016%;7.596%[ vov_mnm1 ]0.003%;0.003%[ ]0.001%;0.003%[ ]0.002%;0.004%[ ]0.001%;0.003%[ ]0.002%;0.003%[ ]0.002%;0.004%[ ]0.002%;0.004%[ ]0.002%;0.004%[ ]0.004%;0.006%[ vov_mnm2 ]0.003%;0.003%[ ]0.002%;0.003%[ ]0.002%;0.004%[ ]0.003%;0.005%[ ]0.002%;0.004%[ ]0.002%;0.003%[ ]0.002%;0.003%[ ]0.003%;0.005%[ ]0.003%;0.004%[ vov_mnm3 ]0.002%;0.003%[ ]0.001%;0.003%[ ]0.001%;0.003%[ ]0.003%;0.005%[ ]0.002%;0.005%[ ]0.002%;0.004%[ ]0.002%;0.004%[ ]0.002%;0.003%[ ]0.002%;0.004%[ vov_mnm4 ]0.002%;0.003%[ ]0.001%;0.003%[ ]0.001%;0.003%[ ]0.002%;0.005%[ ]0.002%;0.005%[ ]0.002%;0.004%[ ]0.002%;0.004%[ ]0.002%;0.003%[ ]0.002%;0.004%[ vov_mnm5 ]0%;0.001%[ ]0%;0.003%[ ]0.002%;0.008%[ ]0.001%;0.008%[ ]0.002%;0.008%[ ]0.002%;0.006%[ ]0%;0.003%[ ]0.001%;0.006%[ ]0.003%;0.011%[ vov_mnm6 ]0%;0.001%[ ]0%;0.003%[ ]0.001%;0.007%[ ]0.001%;0.008%[ ]0.002%;0.008%[ ]0.002%;0.007%[ ]0%;0.003%[ ]0.001%;0.005%[ ]0.004%;0.012%[ vov_mnm7 ]0.001%;0.001%[ ]0.002%;0.009%[ ]0.002%;0.008%[ ]0.002%;0.007%[ ]0.001%;0.005%[ ]0.002%;0.006%[ ]0%;0.005%[ ]0.001%;0.005%[ ]0.001%;0.006%[ vov_mnm8 ]0.001%;0.001%[ ]0.002%;0.009%[ ]0.002%;0.008%[ ]0.002%;0.007%[ ]0.001%;0.005%[ ]0.002%;0.006%[ ]0%;0.005%[ ]0.001%;0.005%[ ]0.001%;0.006%[ vov_mpm0 ]0%;0%[ ]0%;0.003%[ ]0.003%;0.009%[ ]0.001%;0.007%[ ]0%;0.003%[ ]0%;0.003%[ ]0%;0.003%[ ]0%;0.004%[ ]0.002%;0.007%[ vov_mpm1 ]0%;0.001%[ ]0.001%;0.005%[ ]0.001%;0.007%[ ]0.001%;0.007%[ ]0.002%;0.008%[ ]0%;0.005%[ ]0%;0.005%[ ]0.003%;0.009%[ ]0.003%;0.011%[ vov_mpm3 ]0.002%;0.003%[ ]0.002%;0.01%[ ]0.003%;0.01%[ ]0.001%;0.008%[ ]0.002%;0.008%[ ]0.001%;0.007%[ ]0.001%;0.008%[ ]0.002%;0.009%[ ]0.001%;0.008%[ vov_mpm4 ]0.002%;0.003%[ ]0.002%;0.01%[ ]0.003%;0.01%[ ]0.001%;0.008%[ ]0.002%;0.008%[ ]0.001%;0.007%[ ]0.001%;0.008%[ ]0.002%;0.009%[ ]0.001%;0.008%[ vov_mpm5 ]0.001%;0.001%[ ]0.001%;0.004%[ ]0.001%;0.003%[ ]0.001%;0.003%[ ]0.002%;0.004%[ ]0.001%;0.003%[ ]0.001%;0.004%[ ]0%;0.002%[ ]0.001%;0.003%[ vov_mpm6 ]0.001%;0.001%[ ]0.002%;0.004%[ ]0.001%;0.003%[ ]0.001%;0.003%[ ]0.002%;0.004%[ ]0.001%;0.003%[ ]0.001%;0.004%[ ]0%;0.002%[ ]0.001%;0.003%[

Table 5.9: 95% Confidence Intervals for Relative Errors - ELDO points (Dynamic Voltage-Combiners Biased OTA Circuit)

Measures Typical Corner 0 Corner 1 Corner 2 Corner 3 delta_mnm0 ]0%;0%[ ]0.001%;0.003%[ ]0%;0.002%[ ]0.002%;0.007%[ ]0.001%;0.005%[ delta_mnm1 ]0%;0%[ ]0.001%;0.003%[ ]0%;0.002%[ ]0.002%;0.007%[ ]0.001%;0.005%[ delta_mnm4 ]0.007%;0.009%[ ]0.007%;0.014%[ ]0.006%;0.013%[ ]0.006%;0.013%[ ]0.004%;0.009%[ delta_mnm5 ]0.007%;0.009%[ ]0.007%;0.014%[ ]0.006%;0.013%[ ]0.006%;0.013%[ ]0.004%;0.009%[ delta_mnm6 ]0%;0%[ ]0%;0.001%[ ]0%;0.002%[ ]0%;0.002%[ ]0%;0%[ delta_mnm7 ]0%;0%[ ]0%;0.001%[ ]0%;0.002%[ ]0%;0.002%[ ]0%;0%[ delta_mnm8 ]0%;0.001%[ ]0.002%;0.009%[ ]0.001%;0.007%[ ]0%;0.006%[ ]0.004%;0.013%[ delta_mnm9 ]0%;0.001%[ ]0.002%;0.009%[ ]0.001%;0.007%[ ]0%;0.006%[ ]0.004%;0.013%[ delta_mnmbiasn ]0.001%;0.002%[ ]0.003%;0.01%[ ]0.002%;0.007%[ ]0.003%;0.01%[ ]0.002%;0.007%[ delta_mnmbiasp ]0%;0%[ ]0%;0.001%[ ]0.001%;0.002%[ ]0%;0%[ ]0%;0.00001%[ delta_mpm0 ]0.147%;0.194%[ ]0.118%;0.166%[ ]0.115%;0.145%[ ]0.221%;0.311%[ ]0.215%;0.27%[ delta_mpm1 ]0%;0.001%[ ]0.001%;0.005%[ ]0%;0.004%[ ]0.002%;0.007%[ ]0.002%;0.006%[ delta_mpm2 ]0%;0.001%[ ]0.001%;0.005%[ ]0%;0.004%[ ]0.002%;0.007%[ ]0.002%;0.006%[ delta_mpm3 ]0%;0.001%[ ]0%;0.002%[ ]0.001%;0.002%[ ]0.001%;0.005%[ ]0.001%;0.004%[ delta_mpm4 ]0.003%;0.005%[ ]0%;0.002%[ ]0%;0.001%[ ]0.005%;0.008%[ ]0%;0.002%[ delta_mpm5 ]0.037%;0.053%[ ]0.003%;0.012%[ ]0.027%;0.034%[ ]0.013%;0.028%[ ]0.012%;0.017%[ delta_mpm6 ]0.037%;0.053%[ ]0.003%;0.012%[ ]0.027%;0.034%[ ]0.013%;0.028%[ ]0.012%;0.017%[ delta_mpmbiasp ]0%;0%[ ]0%;0.003%[ ]0%;0.004%[ ]0%;0.004%[ ]0%;0.003%[ fom ]0.017%;0.02%[ ]0.086%;0.097%[ ]0.11%;0.125%[ ]0.101%;0.116%[ ]0.122%;0.136%[ gbw ]0.017%;0.019%[ ]0.092%;0.097%[ ]0.114%;0.12%[ ]0.103%;0.109%[ ]0.126%;0.132%[ gdc ]0%;0%[ ]0%;0.002%[ ]0%;0.001%[ ]0%;0.002%[ ]0%;0.002%[ iddol ]0%;0%[ ]0%;0.001%[ ]0.001%;0.005%[ ]0.001%;0.006%[ ]0%;0.003%[ pm ]0.016%;0.019%[ ]0.054%;0.06%[ ]0.08%;0.086%[ ]0.06%;0.066%[ ]0.086%;0.092%[ sdnoise ]0.107%;0.157%[ ]0.13%;0.197%[ ]0.147%;0.219%[ ]0.114%;0.171%[ ]0.15%;0.218%[ vov_mnm0 ]0.001%;0.001%[ ]0.001%;0.003%[ ]0.001%;0.003%[ ]0.001%;0.002%[ ]0%;0.002%[ vov_mnm1 ]0.001%;0.001%[ ]0.001%;0.003%[ ]0.001%;0.003%[ ]0.001%;0.002%[ ]0%;0.002%[ vov_mnm4 ]0.002%;0.003%[ ]0.001%;0.004%[ ]0.001%;0.004%[ ]0.003%;0.007%[ ]0.002%;0.005%[ vov_mnm5 ]0.002%;0.003%[ ]0.001%;0.004%[ ]0.001%;0.004%[ ]0.003%;0.007%[ ]0.002%;0.005%[ vov_mnm6 ]0%;0%[ ]0%;0.001%[ ]0%;0.001%[ ]0%;0.002%[ ]0%;0.002%[ vov_mnm7 ]0%;0%[ ]0%;0.001%[ ]0%;0.001%[ ]0%;0.002%[ ]0%;0.002%[ vov_mnm8 ]0%;0.001%[ ]0.002%;0.009%[ ]-0.001%;0.003%[ ]0.002%;0.009%[ ]-0.001%;0.003%[ vov_mnm9 ]0%;0.001%[ ]0.002%;0.009%[ ]-0.001%;0.003%[ ]0.002%;0.009%[ ]-0.001%;0.003%[ vov_mnmbiasn ]0.001%;0.002%[ ]0.002%;0.009%[ ]0.002%;0.01%[ ]0.002%;0.009%[ ]0.002%;0.01%[ vov_mnmbiasp ]0%;0%[ ]0%;0.004%[ ]0.001%;0.008%[ ]0%;0.004%[ ]0.001%;0.008%[ vov_mpm0 ]0%;0.001%[ ]0%;0.006%[ ]0.001%;0.008%[ ]0%;0.006%[ ]0.001%;0.007%[ vov_mpm1 ]0%;0.001%[ ]0%;0.006%[ ]0.001%;0.007%[ ]0.001%;0.008%[ ]0%;0.006%[ vov_mpm2 ]0%;0.001%[ ]0%;0.006%[ ]0.001%;0.007%[ ]0.001%;0.008%[ ]0%;0.006%[ vov_mpm3 ]0%;0.001%[ ]0%;0.006%[ ]0.001%;0.008%[ ]0%;0.006%[ ]0.001%;0.007%[ vov_mpm4 ]0.001%;0.001%[ ]0%;0.004%[ ]0.002%;0.004%[ ]0%;0.001%[ ]0%;0.002%[ vov_mpm5 ]0.01%;0.015%[ ]0.008%;0.013%[ ]0.002%;0.006%[ ]0.008%;0.012%[ ]0%;0.001%[ vov_mpm6 ]0.01%;0.015%[ ]0.008%;0.013%[ ]0.002%;0.006%[ ]0.008%;0.012%[ ]0%;0.001%[ vov_mpmbiasp ]0.001%;0.001%[ ]0.001%;0.005%[ ]0%;0.001%[ ]0.001%;0.003%[ ]0%;0.002%[

Table 5.10: 95% Confidence Intervals for Relative Errors - NGSpice points (Dynamic Voltage-Combiners Biased OTA Circuit)

Measures Typical Corner 0 Corner 1 Corner 2 Corner 3 delta_mnm0 ]0%;0%[ ]0%;0.002%[ ]0%;0.002%[ ]0%;0.003%[ ]0.001%;0.003%[ delta_mnm1 ]0%;0%[ ]0%;0.002%[ ]0%;0.002%[ ]0%;0.003%[ ]0.001%;0.003%[ delta_mnm4 ]0.007%;0.008%[ ]0.006%;0.012%[ ]0.004%;0.009%[ ]0.007%;0.013%[ ]0.004%;0.009%[ delta_mnm5 ]0.007%;0.008%[ ]0.006%;0.012%[ ]0.004%;0.009%[ ]0.007%;0.013%[ ]0.004%;0.009%[ delta_mnm6 ]0%;0%[ ]0%;0.001%[ ]0%;0.001%[ ]0%;0.002%[ ]0%;0.001%[ delta_mnm7 ]0%;0%[ ]0%;0.001%[ ]0%;0.001%[ ]0%;0.002%[ ]0%;0.001%[ delta_mnm8 ]0%;0%[ ]0.001%;0.006%[ ]0.001%;0.005%[ ]0.005%;0.012%[ ]0.001%;0.007%[ delta_mnm9 ]0%;0%[ ]0.001%;0.006%[ ]0.001%;0.005%[ ]0.005%;0.012%[ ]0.001%;0.007%[ delta_mnmbiasn ]0.002%;0.003%[ ]0.001%;0.005%[ ]0.002%;0.007%[ ]0.001%;0.005%[ ]0.002%;0.007%[ delta_mnmbiasp ]0%;0%[ ]0%;0.001%[ ]0%;0.002%[ ]0%;0.001%[ ]0%;0.002%[ delta_mpm0 ]0.13%;0.174%[ ]0.121%;0.159%[ ]0.096%;0.128%[ ]0.22%;0.296%[ ]0.179%;0.238%[ delta_mpm1 ]0%;0.001%[ ]0.001%;0.005%[ ]0.001%;0.003%[ ]0%;0.004%[ ]0.002%;0.005%[ delta_mpm2 ]0%;0.001%[ ]0.001%;0.005%[ ]0.001%;0.003%[ ]0%;0.004%[ ]0.002%;0.005%[ delta_mpm3 ]0%;0.001%[ ]0%;0.002%[ ]0%;0.002%[ ]0.001%;0.004%[ ]0%;0.003%[ delta_mpm4 ]0.003%;0.004%[ ]0%;0.003%[ ]0%;0.002%[ ]0.005%;0.009%[ ]0%;0.002%[ delta_mpm5 ]0.03%;0.044%[ ]0.009%;0.02%[ ]0.03%;0.037%[ ]0.024%;0.04%[ ]0.015%;0.02%[ delta_mpm6 ]0.03%;0.044%[ ]0.009%;0.02%[ ]0.03%;0.037%[ ]0.024%;0.04%[ ]0.015%;0.02%[ delta_mpmbiasp ]0%;0%[ ]0%;0.004%[ ]0.001%;0.005%[ ]0%;0.003%[ ]0%;0.003%[ fom ]0.016%;0.018%[ ]0.087%;0.098%[ ]0.119%;0.132%[ ]0.1%;0.113%[ ]0.124%;0.137%[ gbw ]0.017%;0.019%[ ]0.096%;0.102%[ ]0.117%;0.123%[ ]0.107%;0.113%[ ]0.127%;0.134%[ gdc ]0%;0%[ ]0%;0.002%[ ]0%;0.001%[ ]0%;0.002%[ ]0.001%;0.003%[ iddol ]0%;0%[ ]0%;0.002%[ ]0.002%;0.005%[ ]0%;0.003%[ ]0.002%;0.006%[ pm ]0.015%;0.017%[ ]0.059%;0.064%[ ]0.081%;0.087%[ ]0.063%;0.068%[ ]0.087%;0.094%[ sdnoise ]0.114%;0.166%[ ]0.116%;0.162%[ ]0.118%;0.168%[ ]0.116%;0.161%[ ]0.123%;0.168%[ vov_mnm0 ]0.001%;0.001%[ ]0.001%;0.003%[ ]0.001%;0.003%[ ]0.001%;0.003%[ ]0.001%;0.003%[ vov_mnm1 ]0.001%;0.001%[ ]0.001%;0.003%[ ]0.001%;0.003%[ ]0.001%;0.003%[ ]0.001%;0.003%[ vov_mnm4 ]0.002%;0.003%[ ]0.001%;0.003%[ ]0.003%;0.007%[ ]0.001%;0.004%[ ]0.002%;0.005%[ vov_mnm5 ]0.002%;0.003%[ ]0.001%;0.003%[ ]0.003%;0.007%[ ]0.001%;0.004%[ ]0.002%;0.005%[ vov_mnm6 ]0%;0%[ ]0%;0.001%[ ]0%;0.002%[ ]0%;0.001%[ ]0%;0.002%[ vov_mnm7 ]0%;0%[ ]0%;0.001%[ ]0%;0.002%[ ]0%;0.001%[ ]0%;0.002%[ vov_mnm8 ]0%;0.001%[ ]0.003%;0.011%[ ]0%;0.004%[ ]0.003%;0.011%[ ]0%;0.004%[ vov_mnm9 ]0%;0.001%[ ]0.003%;0.011%[ ]0%;0.004%[ ]0.003%;0.011%[ ]0%;0.004%[ vov_mnmbiasn ]0.001%;0.002%[ ]0.003%;0.01%[ ]0%;0.005%[ ]0.003%;0.01%[ ]0%;0.005%[ vov_mnmbiasp ]0%;0%[ ]0.002%;0.009%[ ]0.001%;0.007%[ ]0.002%;0.009%[ ]0.001%;0.007%[ vov_mpm0 ]0.001%;0.002%[ ]0%;0.005%[ ]0.001%;0.008%[ ]0.001%;0.006%[ ]0.002%;0.008%[ vov_mpm1 ]0%;0.001%[ ]0.001%;0.006%[ ]0.001%;0.007%[ ]0.001%;0.008%[ ]0%;0.005%[ vov_mpm2 ]0%;0.001%[ ]0.001%;0.006%[ ]0.001%;0.007%[ ]0.001%;0.008%[ ]0%;0.005%[ vov_mpm3 ]0.001%;0.002%[ ]0%;0.005%[ ]0.001%;0.008%[ ]0.001%;0.006%[ ]0.002%;0.008%[ vov_mpm4 ]0.001%;0.001%[ ]0.001%;0.004%[ ]0.001%;0.003%[ ]0.001%;0.005%[ ]0%;0.002%[ vov_mpm5 ]0.009%;0.012%[ ]0.006%;0.01%[ ]0.003%;0.005%[ ]0.007%;0.01%[ ]0%;0.001%[ vov_mpm6 ]0.009%;0.012%[ ]0.006%;0.01%[ ]0.003%;0.005%[ ]0.007%;0.01%[ ]0%;0.001%[ vov_mpmbiasp ]0.001%;0.001%[ ]0.002%;0.006%[ ]0.001%;0.002%[ ]0.001%;0.003%[ ]0%;0.002%[

55 5.4 Conclusions

This chapter compares the results obtained when optimizing two different circuits in AIDA, using both simulators, NGSpice and ELDO. The POFs obtained for each circuit, simulating the same points in both simulators showed that the points of both simulators coincide. However, to compare quantitatively these results, a statistically analysis was performed. For that, 95% confidence intervals of the relative errors of all performance measures were obtained, proving that the differences between both simulators, for both circuits, are negligible reinforcing that NGSpice can be integrate in AIDA.

56 Conclusions

This chapter resumes all the work performed, focusing on the main barriers overcome to achieve the proposed goal, along with the implemented solution. The future work is also presented so that the implemented solution can be improved.

6.1 Achievements

This thesis aims to integrate NGSpice as AIDA’s evaluation engine. To address this goal, an interface to connect both AIDA and the simulator was developed. However, to structure the implemented solution several steps were accomplished.

Firstly, the simulator, namely the NGSpice, had to be tested in order to define how each measure can be obtained. These tests included discover the commands to get all measures, according to the analysis performed, and comparing the output values with ELDO outputs, for the same circuits, in order to understand if the values match with each other.

After that, the main obstacle overcome was running corners, since the NGSpice native solution invoking altermod command is not the best approach, since increases the user complexity when using NGSpice as simulator. The proposed solution was to replicate the original netlist, as much times as the number of corners to run, according to the corners.inc file, which is part of AIDA’s project folder. These netlists are run in parallel so that the execution time of following this approach was not too time consuming.

In addition, considering that NGSpice erases from memory all measures got from previous analysis whenever a new analysis invoked, an AIDA feature will be used to fill this gap. Basically, instead of calculating measures that depends on other measures gathered from different analyses in the netlist, the user only has to write down the corresponding formula, in the design.xml file, which is part of the AIDA’s project.

All the research and tests performed, using both simulators (NGSpice and ELDO), validate the integration of NGSpice in AIDA. The interface that translates NGSpice outputs to AIDA is working, and multiple optimizations were run. The results obtained were compared both qualitative and quantitatively. The graphics presented confirm that, if the optimizations run over the same points, the POFs obtained would be very similar. In addition, looking at the 95% confidence intervals obtained for all performance measures, for both circuits, there is no doubt that the outputs of both simulators are very similar.

Considering the results presented, the main goal was accomplished and, from now on, AIDA will not depend on any commercial simulator to optimize any circuit, since NGSpice is an open source simulation engine, without the constraint of having limited licenses, which allows to disseminate AIDA among all community.

57 6.2 Future Work

The NGSpice version used in this thesis is the 28. The main limitations of this version when integrating this simulator in AIDA were highlighted along this thesis. Nevertheless, since this is an open source simulator which is always being improved, new versions will arise and probably new solutions for these limitations will appear and no longer have to be bypassed in the ACEI. The structure of NGSpice’s output file can also vary and if is a simpler solution, the ACEI can also be adapted to adjust to the new output structure.

Furthermore, despite corners are being run in a parallel system, i.e., multiple processors communicating with each other, using a shared memory, a distributed computing system approach can be developed so that each simulation runs in a different processor, without sharing the same memory, which turns the system more scalable due not dealing with shared memory problems. In short, there will be always opportunities to improve this interface since not only NGSpice, but also AIDA are being constantly improved.

Finally, there is also one feature that could be developed to easier the designer’s experience when building the netlist. This tool could be a GUI that, receiving the circuit description along with the corresponding testbench, could complete the latter writing the necessary commands to invoke the analysis selected by the designer. This interface would have to have a screen where the user could define the analyses to be performed and the performance measures to be obtained. Having all this information, the interface only had to use the correct syntax to invoke the simulations and get the select measures, according to the simulator in which the netlist will run.

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62 Appendix A

NGSpice Guide to Use With AIDA

This guide was developed to allow users to understand how to use NGSpice as AIDA’s evaluation engine. Firstly, the directives most commonly used in NGSpice are presented along with examples to apply them. The importance of using control sections are briefly explained and the syntax of the commands used, inside and outside them, are drawn. In addition, the user can understand how to apply each analysis in NGSpice. Finally, some examples are provided in order to enrich the user experience, since the manual is not clear enough, especially in how to obtain some measures from the analyses performed.

A.1 NGSpice Commands

• First line: the first line is the title and is the only comment line that does not to be preceded by the special character *.

Example:

• Last line: the last line of the netlist is always composed by the .end command.

• Control sections:

o Using these sections users are able to run a script, the netlist, without having to perform the interactions with NGSpice using the shell; o Their main advantage is that variables and measures obtained inside these sections are stored in a vector and can be analysed further, in the following lines of the script, or as input of another commands, while getting measures outside a control section do not store them, inhibiting their subsequent use; o However, if the netlist contains a control section, the batch mode (invoking -b when starting NGSpice) cannot be used, since the outcome may be unpredictable.

Once in most of the circuits there are measures used to obtain other measures, in the same netlist, a control section has to be used to get them, which implies that NGSpice has to be invoked in the interactive mode.

63 A.1.1 Commands Used Outside of Control Section

• .TITLE : this command, when invoked, overrides the first line of the netlist. • * <comment>: with this character, the asterisk, the line is marked as comment. • $ + space or //: allows to add any comment in a line of code. o Example: • .MODEL: allows to use devices and models of available in NGSpice. o Example: • .SUBCKT: defines a sub circuit. Each sub circuit is delimited by the .subckt and .ends cards. The defined group of elements of each sub circuit is automatically inserted wherever the sub circuit is referenced. o Example: • .GLOBAL: nodes preceded by this card are available to all circuits and sub circuits. o Example: • .INCLUDE: allows to reuse portions of circuit descriptions in multiple files. o Example: • .LIB: includes a library in the input file. o Example: Note: the library file has to have the library name selected and each library declared inside the file have to be delimited by two tags: .LIB and .ENDL. • .PARAM: assigns values to identifiers. Expressions must be in braces or in single quotes. o Example: • .FUNC: defines a function that will be replaced by the respective expression when referenced. o Example: 64 • .TEMP: defines the circuit temperature in degrees Celsius. With this card, the temperature defined with an .OPTION line is overridden. o Example: • .IF Conditions: allows, for example, to select parameters according to the conditions that holds. o Example: Note: only one .ELSEIF is allowed in each block. .SUBCKT, .INC, .LIB and .PARAM are components that are currently not supported in if statements. A.1.2 Analysis Commands The simulator variables (.OPTIONS) allows to change simulation parameters, such as accuracy, speed, etc. All available options are described in pages 248-262, in NGSpice Manual [3]. The following analyses are to be performed inside a control section and that is the reason why they do not have the dot character before the command. • AC Analysis: AC (DEC | OCT | LIN) N Fstart Fstop DEC – decade variation and N is the number of points per decade; OCT – octave variation and N is the number of points per octave; LIN – linear variation and N is the number of points; Fstart and Fstop – starting and stop frequencies respectively. o Example: • DC Analysis: DC Source Vstart Vstop Vincr [ Source2 Vstart2 Vstop2 Vincr2 ] Source – name of an independent voltage or current source, a <a href="/tags/Resistor/" rel="tag">resistor</a> or the circuit temperature; Vstart – start value; Vstop – stop value; Vincr – incrementing value. o Example: 65 In the example above, a voltage source VIN will sweep from 0.25 to 0.5 Volts, with steps of 0.25 Volts. • NOISE Analysis: NOISE v(output, <,ref>) src (DEC | OCT | LIN) pts fstart fstop + <pts_per_summary> DEC – decade variation and N is the number of points per decade; OCT – octave variation and N is the number of points per octave; LIN – linear variation and N is the number of points; output – node at which the total output noise is desired; ref – if specified then the voltage v(output) – v(ref) is calculated. The default value is the ground; src – name of the independent source to which input noise is referred; pts, fstart, fstop – AC type parameters that define the frequency range; pts_per_summary – optional parameter. When specified the noise contribution of each noise generator is produced every pts_per_summary frequency points. o The noise analysis generates two different plots: Voltage or Current Noise Spectral Density: two vectors over frequency ▪ onoise_spectrum: output noise divided by √퐻푧; ▪ inoise_spectrum: equivalent input noise which is equal to the output noise divided by the gain of the circuit. Total integrated noise: two vectors over frequency (two scalars) ▪ onoise_total: output noise voltage; ▪ inoise_total: equivalent input noise which is equal to the output noise divided by the gain of the circuit. o Example: • OP Analysis: OP Determines the operating point of the circuit with <a href="/tags/Inductor/" rel="tag">inductors</a> shorted and <a href="/tags/Capacitor/" rel="tag">capacitors</a> opened. This analysis is always performed before any transient, AC, Noise or Pole-Zero analysis, which implies that only needs to be performed when none of the analyses mentioned are previously performed. 66 A.1.3 Commands to Obtain Measures Inside Section • meas: the meas command is used to analyse the outputs given either by transient, AC or DC analyses. When invoked, this command prints the measure to the standard output. o Example: More examples are given in the Manual [3], in section 15.4. • let: the let command creates a new vector and assigns a value to it. Using it allows, for example, to iterate over loops or to perform operations over measures, as calculating overdrives or margins. o Example: • print: when print is invoked, the vectors specified are printed to the standard output. o Example: • quit: this is a crucial command that has to be present in the last .control section of each netlist, right before the .endc command, since NGSpice will be in interactive mode and since the ACEI is the only program that will invoke the simulator, there is no way of exiting the interactive mode better than exiting automatically putting a quit statement in the script (netlist). o Example: Using the quit command AIDA can use NGSpice as evaluation engine using the interactive mode, although the ACEI does not have to interact with it. The ACEI will run a script and get the standard output as a file that the ACEI will parse and get the measures needed. 67 A.2 Examples The following parts of netlists exemplify how measures can be gathered from the analyses performed. • AC and OP measures: as mentioned before, when an AC analysis is performed, the OP analysis is also done by default, meaning that only one analysis has to be explicitly invoked. Sets the temperature to twenty-five Celsius degrees Sets the units to degrees so that, for example, the phase margin is measured in degrees Gets the measures after AC analysis, in this example obtains the gain, the gain- bandwidth product and the phase margin Gets the overdrive of the respective device and then prints it to the standard output Gets the margin of the respective device and then prints it to the standard output 68 • Noise: in order to obtain the noise, after invoking the respective analyses, a loop has to be performed to get the noise at the desired frequency. The noise analysis, as mentioned before, generates four different vectors: two with the voltage or current noise spectral density and another two scalars with the total integrated noise. NGSpice has also a vector of frequencies and the noise vectors have a noise value for each of these frequencies. To get the noise at the desired frequency, firstly the frequency vector has to be iterated to find at which index is the that value of frequency. Having that index, a print statement can be used to get the value from the noise vector. Run Noise Analysis Defines a variable to iterate over the following while loop While loop to iterate over the frequency vector, to find at which index is the frequency with value equals to the GBW measure find above After getting the index desired, the noise value, at that index, can be assigned to a variable to be printed to the standard output Quits the program because, in interactive mode, the program allows the user to interact with the program, which, in this case, is not the objective, since is AIDA that will call NGSpice 69 Note: if the GBW measure was done out of the control section, the GBW value won’t be available to use further, in this case in the while loop, since, as mentioned before, outside the control section these values are not stored in memory. • Transient measures: when performing the transient analysis, the OP analysis is also performed. The following example demonstrates how the slew rate can be obtained. Maximum and minimum voltage values, in rising flank Add a negligible value to maximum and minimum voltage values, since when using the values itself in trise_new and tfall_new measures throws an error Measures the rise and fall times (between the maximum and minimum voltage values and vice-versa) Slew Rate calculation, i.e., measures the quotient between the difference among the obtained voltages (marked in a red dashed line) and the rise time Transient Analysis 70 Appendix B Scripts Developed In this appendix the python script of the ACEI developed is presented, along with the R script used to obtain the 95% confidence intervals for each performance measure. Both scripts can be found in [33]. B.1 ACEI Developed The ACEI developed is a python script which has methods to invoke the simulator in parallel for multiple netlist and collecting their corresponding outputs containing the performance measures values. In order to run corners, the netlists have to be replicated and modified according to the them. In Table B.1, each method which composes the script is presented, including the respective input and output parameters and also a brief description of its purpose. In order to run the script two different commands can be provided, depending on whether corners will run or not. The order of the inputs is the following, in which the netlist.cir is the name of the netlist to simulate and the output-file.dat is the name of the output file which will hold all the performance measures and their corresponding values: - Run corners: acei-ngspice.py –corners netlist.cir output-file.dat; - Run only the netlist given: acei-ngspice.py netlist.cir output-file.dat. 71 Table B.1: ACEI Methods Method Inputs Outputs Description netlist – netlist to run Invokes NGSpice to simulate the runSimulation corner – corner - specified netlist designation Dictionary containing the Parses NGSpice’s output to a corner – current netlist performance measures dictionary which contains the names parseMeasures designation obtained from the and values of all performance simulation measures measures – dictionary containing the performance measures Writes the performance measures writeKeys - outFile – output file names to the output file which will be AIDA’s output measures – dictionary containing the performance measures Writes the performance measures writeValues - outFile – output file values to the output file which will be AIDA’s output measures - dictionary Writes the output file which will be getOutputFile containing the - AIDA’s output performance measures Removes files from previous removePreviousFiles - - NGSpice executions Removes the output files from removeOutputFiles - - NGSpice executions Removes design variables files removeDesignVarIncFiles - - replicated removeNetlists - - Remove netlists replicated q – queue that will hold If corner options is given as input, buildNetlistsWithCorners the original and the - replicates the netlists according to replicated netlists the corners.inc file filename – name of the original file New file which is a copy copyFile nameToAdd – name to Replicates a file of the original one given add to the original netlist file filename – file to be changed toReplace – block of Changes a file, finding a pattern and changeFile text to exchange when - change it for the new value pattern is found pattern – pattern to be found in the given file simObj – netlist taken Runs NGSpice for the specified from the queue netlist and parses the output values simulation measures – dictionary - to the performance measures containing the dictionary performance measures q – queue that holds the netlists to be simulated Runs all netlists until the queue is processNetlists measures – dictionary - empty containing the performance measures Main method which fills the queue with the original netlist plus the copied files, launch threads to main - - simulate each netlist in parallel and joins all threads to write the output file which is AIDA’s input 72 B.2 R Script The script developed to perform the statistical analysis is presented beloew, in which 95% confidence intervals for the relative errors of each performance measure are obtained. Basically, the script opens two files, one for each simulator, in which each column has the values for all points simulated for a specific measure. Then, for each one of that measures, the confidence intervals are calculated and a file with the outputs containing the results is written. R Script usage: Rscript.exe ConfidenceIntervals.R file1Path file2Path outputFile cornersNumber Figure B.1: R Script to obtain 95% confidence intervals for the relative errors of all performance measures 73 </div> </article> </div> </div> </div> <script type="text/javascript" async crossorigin="anonymous" src="https://pagead2.googlesyndication.com/pagead/js/adsbygoogle.js?client=ca-pub-8519364510543070"></script> <script src="https://cdnjs.cloudflare.com/ajax/libs/jquery/3.6.1/jquery.min.js" crossorigin="anonymous" referrerpolicy="no-referrer"></script> <script> var docId = 'f708b6b1db11915feb946bdcfd8aa89b'; var endPage = 1; var totalPage = 89; var pfLoading = false; window.addEventListener('scroll', function () { if (pfLoading) return; var $now = $('.article-imgview .pf').eq(endPage - 1); if (document.documentElement.scrollTop + $(window).height() > $now.offset().top) { pfLoading = true; endPage++; if (endPage > totalPage) return; var imgEle = new Image(); var imgsrc = "//data.docslib.org/img/f708b6b1db11915feb946bdcfd8aa89b-" + endPage + (endPage > 3 ? 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