A Systemc Transaction Level Model for the MIPS R3000 Processor
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SETIT 2007 4th International Conference: Sciences of Electronic, Technologies of Information and Telecommunications March 25-29, 2007 – TUNISIA A SystemC Transaction Level Model for the MIPS R3000 Processor Yon Jun Shin and Sofiène Tahar Ali Habibi* Concordia University MIPS Technologies 1455 de Maisonneuve West, Montreal, Quebec H3G 1M8, Canada 1225 Charleston Rd., Mountain View, CA, 94041, USA {yon shin,tahar}@ece.concordia.ca [email protected] Abstract: Processor cores in embedded applications build today the cornerstone of System-on-Chip designs. Among the most successful RISC (Reduced Instruction Set Computer) cores are the MIPS processors used in applications such as DVD, automotive, broadband access, networking, etc. In this paper, we design and verify a Transaction Level Modeling (TLM) architecture of the MIPS R3000 in SystemC. The TLM in SystemC is adopted so that abstract data types can be used for higher (abstract) level modeling and faster simulation. The processor is implemented such that the instruction and data caches contain all the necessary instructions and data to eliminate complex memory access management, respectively. To simulate the processor, we provide a script that automatically generates the machine instruction code from assembly language. Key words: SystemC, MIPS Processor, Transaction Level Modeling. simulate and test a system in early stages of the design cycle. Due to rapidly changing product cycles and INTRODUCTION required time to introduce in the market, SystemC, as System-on-Chip (SoC) is a popular technology an IEEE standard, becomes even more attractive used in embedded applications these days. Electronic language when it comes to system-level design due to components that are laid out on a PCB (Printed Circuit reuse of intellectual property (IP) blocks. Board) to make systems not too long ago can be now integrated in a single piece of silicon to be produced in a chip. As a system is developed on a single chip, it The basic idea of Transaction Level Modeling not only requires hardware components but also (TLM) is to establish communication through function software components that have to be developed. calls that represent transactions rather than signals as Hence hardware description languages such as VHDL at the Register Transfer Level (RTL). In this paper, we or Verilog show their limitations when used in SoC adopt the OSCI interpretation of TLM including development. Alternative languages for integrating Programmers View (PV), which contains no timing; both hardware and software development were sought Programmers View with Timing (PVT), which adds after and several languages have been introduced such timed protocols and can analyze latency or as SystemC [Gro02] and SystemVerilog [Sys06]. But throughput; and Cycle Accurate, which is accurate to recent acceptance of SystemC as an IEEE standard the clock edge but does not model internal registers [IEE05], it became the premier choice for SoC [OSI06]. development language. MIPS processors are very popular processor cores SystemC was developed by Open SystemC in SoC applications due to their effectiveness in terms Initiative (OSCI) on top of C++ which is a mature and of simplicity, processing power, and low power one of the widely used software development consumption. In this paper, we design and verify a languages. With the modeling of hardware behavior as TLM architecture in SystemC of the MIPS R3000 library in C++, both software and hardware can now processor. As a high level abstract model, TLM be modeled in a single language, making it easy to enables both hardware and software to be developed * This work was done while the first author was at - 1 - Concordia University SETIT2007 concurrently at an early design stage hence making it and Logic Unit) operations and save the result back to an effective way for new product development. rd. These instructions require not only opcode but also function field to further specify the operations. Most of the R-type ALU instructions have “000000” as There can be found in the open literature two opcode field deferring the operation decision to the related work on SystemC modeling of MIPS function field. processors. For instance, the company CoWare has developed a library of SystemC based models for Electronic System Level (ESL) design [CoW06]. The I-type instructions take immediate constant value library contains several processors from the MIPS and as one of the operands. The result of the ALU ARM families. The second is a work of Madsen et al. operation is saved back to rt as well. [Jor03], who developed a MIPS R2000 processor in SystemC and implemented it in Xilinx Spartan II FPGA. Their SystemC model was at the Register J-type instructions, which is Jump instruction, uses Transfer Level (RTL). In contract to the above, in this 26 bit address field to get the target address. paper, we are interested in a TLM design for the processor that can be used either as a testbench or a model to guide the implementation of a synthesizable 1.2. MIPS Pipeline Stages core MIPS R3000. Each instruction is stored in instruction cache in the order of execution and fetched at every clock The rest of the paper is organized as follows. cycle. It goes through 5 pipeline stages to be Section 1 introduces the MIPS R3000 architecture. completed. The 5 stages that each instruction goes Section 2 describes details of the MIPS R3000 through are: instruction fetch (IF), instructions decode SystemC TLM design steps. Section 3 presents (ID), execute (EX), data memory (MEM), and write- experimental results we conducted for evaluating the back (WB). model. Finally, Section 4 concludes the paper. 1. MIPS R3000 Processor MIPS R3000 processor is a 5 stage pipelined processor that implements 32-bit MIPS instruction set architecture (ISA). It was introduced in 1988 and contained 0.11 million transistors on 66.12mm2 die size with 1.2 µm process technology [HP02]. It also contained instruction cache and data cache with sizes of 64k byte each and was running between 20 to 40MHz consuming 4W of power. Due to small power consumption and heat characteristics of embedded MIPS implementations, low cost, widely available Figure 2. MIPS Pipeline Structure [Bre02] development tools, and simple architecture, etc., this processor is a good candidate to be used in SoC. The Instruction Fetch stage fetches the instruction from instruction memory (instruction cache) in the address given by the program counter (PC) and updates its value for next instruction. Fetched instructions are then passed on to the ID stage. Figure 1. MIPS R3000 Instruction Format The Instruction Decode stage decodes the instruction and accesses the General Purpose Register (GPR) for the operands (two for ALU operations) in the EXE stage. Also immediate values are sign- 1.1. MIPS Instruction Format extended to be 32 bit vector and Jump target address and Branch condition as well as target addresses are MIPS instructions have 3 different formats, determined in this stage. If the branch condition is namely R, I, and J type instructions. Figure 1 shows met, then the program counter will be updated with the format of each 32 bit instruction type [HP02]. R- the target address and the new PC will be used as next type instructions access two general purpose registers instruction address to be fetched. rs, rt and use them as operands of ALU (Arithmetic - 2 - SETIT2007 modeled, system verification can be started early in the development stage. TLM also emphasizes on The Execute stage “executes” the instruction. In functionality rather than actual implementation, it fact, all ALU operations are done in this stage. The enables faster simulation speed than pin-based model ALU is the Arithmetic and Logic Unit and performs [Ghe05]. operations such as addition, subtraction, logical AND, logical OR, etc. In the EXE stage, the address for memory access for load or store instructions is also First, two classes of SystemC modules calculated. (sc_module), moduleA and moduleB are generated. Each module can pass transactions through an interface, and it has to be defined for communication The Memory Access stage performs any memory between two modules. Once the interface class is access required by the current instruction. So, for defined with transaction function that can be used in loads, it would access a memory location and load the it, a port of type interface is declared in one of the value onto GPR. For stores, it would store an operand module and the interface member functions are into memory address specified in the instruction. implemented in the other module. The SystemC code in Figure 4 is an example of how to implement Transaction Level Model using interface. The Write-Back stage writes the result of instruction back to register file. Careful attention is needed to write the register file before it is read by First, two classes of sc_module, moduleA and another instruction. moduleB are created. Each module has its own process therefore can work concurrently. Once the modules are created, class of interface, moduleA_moduleB_if is Figure 2 provides a general description of how the created with member function(s) declared in it. 5 stage pipeline is structured. Figure 3 shows how the Interface can be directly connecting two modules or sequence of instructions is executed through the can have intermediate channel between two modules. pipeline in each cycle. The main advantage of pipeline Interface is directly connected between the two architecture is that theoretically at each clock cycle, modules in the above example. moduleA declares a each pipeline block is processing an instruction. sc_port of type moduleA_moduleB_if and the member Therefore the throughput of the processor becomes 1 function moduleA_moduleB_function will be called at each clock cycle ignoring the initial latency to fill through moduleA_moduleB_port to pass parameters to up the pipeline for 5 clock cycles.