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18-741 Advanced Computer Architecture Lecture 1: Intro And 18-447 Computer Architecture Lecture 7: Microprogrammed Microarchitectures Prof. Onur Mutlu Carnegie Mellon University Spring 2012, 2/8/2012 Reminder: Homeworks Homework 1 Grades out on Blackboard Homeworks will be handed out next class Homework 2 Due February 13 ISA concepts, ISA vs. microarchitecture, microcoded machines 2 Lab Assignment 1 Graded Your grade is in your handin directory: grade.txt Test cases will be released 3 Lab 1 Grade Distribution 18 16 14 12 10 8 6 4 Number of Students Number 2 0 0 100 150 200 250 300 350 400 450 500 550 555 Lab 1 Grade Average 457 Median 493 Max 555 Min 0 Max Possible Score 555 Total number of students 55 4 Lab 1 Simulation Time 5 Aside: Simulator Design Accuracy Functional accuracy: Does the simulator accurately model what the ISA specifies Timing accuracy: Does the (timing) simulator accurately model how many cycles the hardware design would actually take Speed 6 Reminder: Lab Assignment 2 Lab Assignment 1.5 Verilog practice Not to be turned in Lab Assignment 2 Due Friday, Feb 17, at the end of the lab Individual assignment No collaboration; please respect the honor code 7 Reminder: Extra Credit for Lab Assignment 2 Complete your normal (single-cycle) implementation first, and get it checked off in lab. Then, implement the MIPS core using a microcoded approach similar to what we are discussing in class. We are not specifying any particular details of the microcode format or the microarchitecture; you should be creative. For the extra credit, the microcoded implementation should execute the same programs that your ordinary implementation does, and you should demo it by the normal lab deadline. 8 Readings for Today P&P, Revised Appendix C Microarchitecture of the LC-3b Appendix A (LC-3b ISA) will be useful in following this P&H, Appendix D Mapping Control to Hardware Optional Maurice Wilkes, “The Best Way to Design an Automatic Calculating Machine,” Manchester Univ. Computer Inaugural Conf., 1951. 9 Readings for Next Lecture Pipelining P&H Chapter 4.5-4.8 10 Oracle/Sun UltraSPARC T4 Talk Today! Dr. Jared Smolens, PhD CMU 2007 4-5pm CIC 4th Floor Panther Hollow conference room T4: A highly-threaded server-on-a-chip with native support for heterogeneous computing http://www.ece.cmu.edu/~calcm/doku.php?id=seminars:se minar_12_02_08 Microarchitecture of Oracle’s newest processor 8 cores, 8 hardware threads in each core Out-of-order execution Shared L3 cache; private L1 and L2 caches Two memory controllers 11 Review: Last Lecture Finished single-cycle microarchitectures Microarchitecture design principles Basic performance evaluation (execution time equation) What does it mean to design for the common case (or bread and butter design)? If memory takes 90% of execution time … How does the single cycle microarchitecture make “critical path design” difficult? Remember the performance equation that consists of three components… How can you improve each component in a multi-cycle microarchitecture? 12 Review: Microarchitecture Design Principles Critical path design Find the maximum combinational logic delay and decrease it Bread and butter (common case) design Spend time and resources on where it matters i.e., improve what the machine is really designed to do Common case vs. uncommon case Balanced design Balance instruction/data flow through hardware components Balance the hardware needed to accomplish the work How does a single-cycle microarchitecture fare in light of these principles? 13 Review: Multi-Cycle Microarchitectures Goal: Let each instruction take (close to) only as much time it really needs Idea Determine clock cycle time independently of instruction processing time Each instruction takes as many clock cycles as it needs to take Multiple state transitions per instruction The states followed by each instruction is different 14 Review: Multi-Cycle Microarchitecture AS = Architectural (programmer visible) state at the beginning of an instruction Step 1: Process part of instruction in one clock cycle Step 2: Process part of instruction in the next clock cycle … AS’ = Architectural (programmer visible) state at the end of a clock cycle 15 Review: Performance Analysis Execution time of an instruction {CPI} x {clock cycle time} Execution time of a program Sum over all instructions [{CPI} x {clock cycle time}] {# of instructions} x {Average CPI} x {clock cycle time} Single cycle microarchitecture performance CPI = 1 Clock cycle time = long Multi-cycle microarchitecture performance CPI = different for each instruction Now, we have Average CPI hopefully small two degrees of freedom to optimize independently Clock cycle time = short 16 A Microprogrammed Multi-Cycle Microarchitecture 17 Review: The Instruction Processing Cycle Fetch Decode Evaluate Address Fetch Operands Execute Store Result 18 A Basic Multi-Cycle Microarchitecture Instruction processing cycle divided into “states” A stage in the instruction processing cycle can take multiple states A multi-cycle microarchitecture sequences from state to state to process an instruction The behavior of the machine in a state is completely determined by control signals in that state The behavior of the entire processor is specified fully by a finite state machine In a state (clock cycle), control signals control How the datapath should process the data How to generate the control signals for the next clock cycle 19 Review: Microprogrammed Control Terminology Control signals associated with the current state Microinstruction Act of transitioning from one state to another Determining the next state and the microinstruction for the next state Microsequencing Control store stores control signals for every possible state Store for microinstructions for the entire FSM Microsequencer determines which set of control signals will be used in the next clock cycle (i.e. next state) 20 A Simple LC-3b Control and Datapath 21 An LC-3b State Machine Patt and Patel, App C, Figure C.2 Each state must be uniquely specified Done by means of state variables 31 distinct states in this LC-3b state machine Encoded with 6 state variables Examples State 18,19 correspond to the beginning of the instruction processing cycle Fetch phase: state 18, 19 state 33 state 35 Decode phase: state 32 22 C.2. THE STATE MACHINE 5 18, 19 MAR <! PC PC <! PC + 2 33 MDR <! M R R 35 IR <! MDR 32 1011 RTI BEN<! IR[11] & N + IR[10] & Z + IR[9] & P To 11 1010 To 8 ADD [IR[15:12]] To 10 BR AND 0 1 XOR DR<! SR1+OP2* JMP [BEN] 0 set CC TRAP JSR SHF LEA STW STB 1 LDB LDW 22 To 18 5 DR<! SR1&OP2* PC<! PC+LSHF(off9,1) set CC 9 12 To 18 DR<! SR1 XOR OP2* To 18 PC<! BaseR set CC To 18 15 4 To 18 MAR<! LSHF(ZEXT[IR[7:0]],1) [IR[11]] 0 1 28 20 MDR<! M[MAR] R7<! PC R7<! PC PC<! BaseR R R 21 30 PC<! MDR R7<! PC To 18 PC<! PC+LSHF(off11,1) 13 To 18 DR<! SHF(SR,A,D,amt4) set CC To 18 14 2 6 7 3 To 18 DR<! PC+LSHF(off9, 1) set CC MAR<! B+off6 MAR<! B+LSHF(off6,1) MAR<! B+LSHF(off6,1) MAR<! B+off6 To 18 29 25 23 24 NOTES MDR<! M[MAR[15:1]’0] MDR<! M[MAR] MDR<! SR MDR<! SR[7:0] B+off6 : Base + SEXT[offset6] PC+off9 : PC + SEXT[offset9] R R R R 27 16 17 *OP2 may be SR2 or SEXT[imm5] 31 DR<! MDR ** [15:8] or [7:0] depending on DR<! SEXT[BYTE.DATA] M[MAR]<! MDR M[MAR]<! MDR** set CC set CC MAR[0] R R R R To 18 To 18 To 18 To 19 Figure C.2: A state machine for the LC-3b LC-3b State Machine: Some Questions How many cycles does the fastest instruction take? How many cycles does the slowest instruction take? Why does the BR take as long as it takes in the FSM? What determines the clock cycle? Is this a Mealy machine or a Moore machine? 24 LC-3b Datapath Patt and Patel, App C, Figure C.3 Single-bus datapath design At any point only one value can be “gated” on the bus (i.e., can be driving the bus) Advantage: Low hardware cost: one bus Disadvantage: Reduced concurrency – if instruction needs the bus twice for two different things, these need to happen in different states Control signals (26 of them) determine what happens in the datapath in one clock cycle Patt and Patel, App C, Table C.1 25 C.4. THE CONTROL STRUCTURE 11 IR[11:9] IR[11:9] DR SR1 111 IR[8:6] DRMUX SR1MUX (a) (b) IR[11:9] N Logic BEN Z P (c) Figure C.6: Additional logic required to provide control signals LC-3b to operate correctly with a memory that takes multiple clock cycles to read or store a value. Suppose it takes memory five cycles to read a value. That is, once MAR contains the address to be read and the microinstruction asserts READ, it will take five cycles before the contents of the specified location in memory are available to be loaded into MDR. (Note that the microinstruction asserts READ by means of three control signals: MIO.EN/YES, R.W/RD, and DATA.SIZE/WORD; see Figure C.3.) Recall our discussion in Section C.2 of the function of state 33, which accesses an instruction from memory during the fetch phase of each instruction cycle. For the LC-3b to operate correctly, state 33 must execute five times before moving on to state 35. That is, until MDR contains valid data from the memory location specified by the contents of MAR, we want state 33 to continue to re-execute.
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