Tin (Sn) - An Unlikely Ally to Extend Moore’s Law for Silicon CMOS?
Thesis by Aftab Mustansir Hussain
In Partial Fulfillment of the Requirements
For the Degree of
Masters of Science
King Abdullah University of Science and Technology, Thuwal,
Kingdom of Saudi Arabia
December, 2012 2 Examination Committee Approval Form
The thesis of Aftab Mustansir Hussain is approved by the examination committee.
Committee Chairperson: Dr. Muhammad Mustafa Hussain
Committee Member: Dr. Ian Foulds
Committee Member: Dr. Aram Amassian 3
Copyright 2012
Aftab Mustansir Hussain
All Rights Reserved 4
ABSTRACT
There has been an exponential increase in the performance of silicon based semicon- ductor devices in the past few decades. This improvement has mainly been due to di- mensional scaling of the MOSFET. However, physical constraints limit the continued growth in device performance. To overcome this problem, novel channel materials are being developed to enhance carrier mobility and hence increase device performance. This work explores a novel semiconducting alloy - Silicon-tin (SiSn) as a channel ma- terial for CMOS applications. For the first time ever, MOS devices using SiSn as channel material have been demonstrated. A low cost, scalable and manufacturable process for obtaining SiSn by di↵usion of Sn into silicon has also been explored. The channel material thus obtained is electrically characterized by fabricating MOSCAPs and Mesa-shaped MOSFETs. The SiSn devices have been compared to similar devices fabricated using silicon as channel material. 5
ACKNOWLEDGEMENTS
All praise is to Allah the almighty. I would like to express my deepest gratitude towards my supervisor and mentor Dr. Muhammad M. Hussain for the constant motivation, support and guidance. This work would not have been possible without his guidance. I also heartily thank Dr. Casey Smith and Kelly Rader for their invaluable advice and support throughout the course of this project. I would also like to extend special thanks to Dr. Aram Amassian and Dr. Ian Foulds for taking out the time to review this thesis. Finally, I am grateful to my parents, my wife, my brother and friends for their moral support. 6
TABLE OF CONTENTS
Examination Committee Approval 2
Copyright 3
Abstract 4
Acknowledgements 5
List of Symbols 8
List of Figures 9
List of Tables 11
1 Introduction 12
2Di↵usion of Sn into Silicon 15 2.1 Tin di↵usivity into silicon ...... 15 2.2 Di↵usion conditions ...... 17 2.3 Electrical characterization ...... 18 2.4 Physical characterization ...... 20 2.5 Discussion ...... 22
3 Device Fabrication 24 3.1 SiSnMOSCAPfabrication ...... 24 3.2 SiSnMesa-shapedMOSFETfabrication ...... 29
4 Results and Discussion 35 4.1 SiSnMOSCAPcharacterization ...... 35 4.1.1 MOSCAPTheory...... 35 4.1.2 Experimental details ...... 39 4.1.3 MOSCAPResults...... 42 7 4.1.4 Discussion ...... 51 4.2 SiSnMOSFETcharacterization ...... 52 4.2.1 Experimental details ...... 52 4.2.2 MOSFETResults...... 53 4.2.3 Discussion ...... 60
5 Conclusion 62
6 Future Work 65
References 66
Appendices 73 8
LIST OF SYMBOLS
Relative dielectric constant with respect to vacuum. Ea Activation energy of di↵usion. D0 Pre-exponent term for di↵usion calculation (Di↵usion constant at infinite temperature). ⇢ Resistivity. 19 q Electronic charge (1.602 10 C). µ Carrier mobility. ⇥ ✓B Bragg’s angle of di↵raction. Wavelength of incident X-Ray. ✏ Crystal lattice strain. a Crystal lattice constant. EC Conduction band energy. EV Valence band energy. EF Fermi energy level. EG Semiconductor bandgap. M Metal workfunction. S Semiconductor workfunction. S Semiconductor electron a nity. Qf Fixed oxide charge. Qt Trapped oxide charge. Qm Mobile oxide charge. Qit Interface trapped charge. Cox Accumulation capacitance. tox Dielectric thickness.
✏Al2O3 Permittivity of Al2O3.
✏SiO2 Permittivity of SiO2. VFB MOSCAP flatband voltage. Dit Semiconductor-dielectric interface defect density. Clf Low frequency inversion capacitance. Chf High frequency inversion capacitance. ⌘ Ideality factor for the MOS device. µlin Linear field e↵ect mobility. µsat Saturation field e↵ect mobility. 9
LIST OF FIGURES
2.1 Measured resistivity values for SiSn samples annealed at 500 Cand 750 C. The mean and standard deviation values are represented using aboxchart...... 19 2.2 2✓ XRD peaks for SiSn sample annealed at 750 C. (Inset: XRD peaks for heavily-Sb-doped silicon [42].) ...... 20
3.1 MOSCAPmasklayout...... 25 3.2 Sn depostion on silicon wafer and anneal...... 25 3.3 Fieldoxidedeposition...... 26 3.4 Fieldoxidepatterning...... 27 3.5 Dielectric deposition...... 28 3.6 Gate metal lift-o↵...... 28 3.7 MOSFETmasklayers...... 29 3.8 Sn di↵usion into silicon ...... 30 3.9 Device isolation...... 31 3.10 Source/drain contact pad formation...... 31 3.11 Dielectric deposition...... 32 3.12 Dielectric patterning...... 33 3.13 Gate metal definition...... 33 3.14 a) A circular MOSCAP of 25 µm diameter. The pad oxide etched using the active layer mask is clearly seen below the gate metal. b) A circular MOSCAP of 250 µm diameter along with the contact pad. . 34 3.15 a) A MOSFET with 8 µm wide fins at 1:2 pitch. b) Tilt SEM image of the source pad contacting the SiSn fins. The gap between the fins istheexposedburiedoxide(BOX)oftheSOI...... 34
4.1 Band structure of MOSCAP for no applied gate voltage...... 36 4.2 Flatbandconditionforann-typeMOSCAP...... 37 4.3 Various modes of operation for an ideal n-type MOSCAP...... 38 4.4 Normalized capacitances for measured SiSn MOSCAPs...... 41 10 4.5 FrequencyresponseofSiSnMOSCAPs...... 41 4.6 Normalized capacitances for SiSn and Si MOSCAPs...... 42 4.7 Linear fit for the depletion region of SiSn and Si MOSCAP...... 43 4.8 Estimation of flatband voltage of SiSn and Si MOSCAPs...... 45 4.9 Estimation of interface defect density of SiSn and Si MOSCAPs. . . . 47 4.10 Hysteresis in CV characteristics of SiSn and Si MOSCAPs. The ab-
solute di↵erence between forward (Cf )andreverse(Cr)capacitances
has been plotted as a function of Vg...... 48 4.11 Comparision of I V characteristics for SiSn and Si MOSFETs. . . 53 d g 4.12 Estimation of threshold voltage from I V characteristics of SiSn and d g SiMOSFETs...... 54 4.13 Estimation of subthreshold slope from I V characteristics of SiSn d g andSiMOSFETs...... 55 4.14 Estimation of linear mobility from I V characteristics of SiSn and d g SiMOSFETs...... 57 4.15 Estimation of saturation mobility from I V characteristics of SiSn d g andSiMOSFETs...... 58 4.16 Variation of saturation drain current of SiSn MOSFETs with e↵ective channelwidth...... 60 11
LIST OF TABLES
2.1 Thebasicatomicpropertiesofsiliconandtin...... 15 2.2 Comparison of reported activation energies of di↵usion of tin into silicon. 16
4.1 Comparison of basic capacitance values for SiSn and Si MOSCAPs. . 50 4.2 Comparison of the calculated parameters for SiSn and Si MOSCAPs. 51 4.3 Comparison of the calculated parameters for SiSn and Si MOSFETs. 60
5.1 Comparison of basic MOSFET parameters for SiSn values obtained in this work and the reported GeSn values. (NR: Not Reported) . . . . 63 12
Chapter 1
Introduction
The semiconductor industry has seen an exponential increase in device performance over the past two decades. This rapid growth in technology was first predicted by the co-founder of Intel Corporation, Gordon Moore in his 1965 talk [1]. The trend has been popularly termed as the Moore’s law, and has mainly been a result of the constant scaling down of the dimensions of the silicon based transistor - the basic building block of CMOS technology. The advances in fabrication technology have scaled down transistor dimensions so much that the continuation of the Moore’s law with scaling will be physically impossible in the coming decade [2]. The reduction in transistor channel dimensions results in numerous problems such as short channel e↵ects, high gate leakage, high power dissipation, etc. To continue the exponential growth in transistor performance over the coming years, various approaches have been attempted. These e↵orts include, but are not limited to, use of strained silicon [3], use of high-/metal gate [4], change in the structure of the traditional planar transistor into three dimensional (3D) non-planar multi-gate FET (MugFET) [5]. Straining the silicon lattice to increase carrier mobility was introduced at the start of the past decade. Application of compressive and tensile strain on the channel as a way of mobility enhancement has been of key importance for sub-90 nm process node. The devices employing strained silicon channel have already made their way into IC products. The silicon channel was strained in these devices using a process-induced 13 strain technology [6]. This approach included several techniques such as stress liner technique [7, 8, 9], stress memorization technique [10, 11, 12, 13] and SiGe embedded source/drain [14, 15, 16]. In case of strained silicon, SiGe was generally embedded in pMOSFET source/drain to provide a compressive strain on the channel and enhance carrier mobility. Germanium has an electronegativity of 2.00 (Pauling scale) [17]. It is close to that of silicon - 1.90 [17]. The atomic radius of germanium is 125 pm and that of silicon is 110 pm [18]. Both, silicon and germanium belong to the same group, IVa, of the periodic table and display similar valencies. They crystallize in the diamond cubic crystal structure. Thus, according to Home Ruthery rules [19], they are capable of forming solid state solutions at all concentrations. According to Vegard’s law [20], the lattice constant of these solid solutions can be engineered to any value between that of silicon (5.431 A˚) and germanium (5.657 A˚)bycontrolling the relative concentration of the species in the solution. Thus, the silicon lattice can be e↵ectively strained by introducing germanium into the lattice. In past studies of strained Si, a thin layer of epitaxially grown SiGe was embedded in the source drain regions to enhance device performance [14, 15, 16]. SiGe was not directly used as the semiconducting medium in these devices. It was only incorporated into the regular silicon MOSFETs to strain the channel area and obtain performance improvement. It should be noted that SiGe mixture itself retains its semiconducting properties [21]. Further, apart from the lattice strain, the band structure of silicon also gets a↵ected by the incorporation of germanium into the lattice [21]. The band structure and semiconducting nature of other group IV alloys such as SiSn and GeSn have also been studied in the past [22, 23, 24]. These studies were theoretical analyses of the structure of the conduction band and valence band for various compositions of these alloys. However, the use of group IV alloy semiconduc- tors as channel materials has only recently gained significance. Several works have been dedicated to the fabrication of MOSFETs using group IV alloys SiGe and GeSn 14 [25, 26, 27, 28, 29, 30]. In these studies, the semiconducting alloy was grown by either gas phase epitaxy or molecular beam epitaxy. These processes increase the cost of production significantly. In case of GeSn growth, gallium substrates were used as the starting point, further increasing the processing cost. To the best of the author’s knowledge, no transistors or other MOS devices have been demonstrated in the past using SiSn as a channel material. In this work, SiSn has been studied as a channel material by fabrication and characterization of MOS devices. The SiSn channel is obtained from a low cost process of di↵usion of Sn atoms into bulk silicon (100) wafers. The work is built on the idea that the incorporation of tin will strain the silicon lattice and reduce the band gap of silicon [22, 23, 24]. Silicon wafers with di↵used tin have been used to make Mesa-shaped MOSFETs and MOSCAPs. In these devices, the strained SiSn structure acts as the channel material itself. The resulting devices have been electrically characterized for performance evaluation. 15
Chapter 2
Di↵usion of Sn into Silicon
2.1 Tin di↵usivity into silicon
Tin belongs to group IVa of the Periodic table. Tin crystallizes into two allotropic forms known as ↵-tin and -tin [31]. It is a malleable and ductile metallic element when it crystallizes in a body centered tetragonal lattice ( -tin) [32]. The other allotrope is known to crystallize in diamond cubic lattice like silicon and germanium. This allotrope of tin (↵-tin) is a grey semiconductor with zero direct bandgap [33]. Tin has an electronegativity of 1.93 and an atomic radius of 145 pm [17, 18]. The basic properties of tin and silicon have been summarized in Table 2.1.
Silicon Tin Atomic radius 110 pm 145 pm Electronegativity 1.90 1.93 Crystal structure Diamond cubic crystal Diamond cubic crystal (↵-tin) Valency 4 2, 4
Table 2.1: The basic atomic properties of silicon and tin.
The Hume Rothery rules used to access solid state solubility, state that for com- plete solid solubility [19]:
The di↵erence between atomic radii of the solute and the solvent should be less than 15 %. 16 The crystal structure of the solute and solvent should be the same.
The solute and solvent should have the same valency.
The solute and solvent should have similar electronegativity.
The di↵erence between the atomic radii for silicon and tin is 31.8 %. The di↵erence in atomic radii of Si and Sn implies that they might not form solid solutions in all concentrations. However, since the other three criteria are met, there may be partial solubility of tin in silicon. With such a large size, tin is expected to di↵use through avacancy-assistedmechanism. Some studies have shown the di↵usion of tin into silicon at elevated temperatures. These studies have mainly concentrated on the concentration profile and depth of dif- fusion at various temperatures, thus determining the activation energy of di↵usion. However, there exists a significant di↵erence in the reported values of activation ener- gies of di↵usion in these works. Table 2.2 compares the reported activation energies for these works.
2 Year Temperature range ( C) Ea (eV) D0 (cm /s) REF [34] 1968 1050 - 1200 4.25 32 REF [35] 1974 1100 - 1200 3.5 0.054 REF [36] 1995 500 - 1200 4.91 0.09 (5 4) 103 ± ± ⇥ REF [37] 1997 900 - 1075 4.8 0.3 (1.4 3.6) 103 ± ± ⇥ REF [38] 2010 550 - 700 1.2 5.8
Table 2.2: Comparison of reported activation energies of di↵usion of tin into silicon.
The di↵erences in activation energy of di↵usion leads a wide range of expected di↵usion lengths for a given anneal condition. In the recent study by A. E. Dolbak, et al. [38], a thin film of tin, deposited over a silicon wafer using thermal evaporation, was used as the source of tin atoms. The reported depth of uniform di↵usion is of the order of millimeters. Since the source of tin atoms in our work was also a thin film of tin (deposited using DC sputtering), the di↵usion conditions in the here have been based on this paper. 17 2.2 Di↵usion conditions
Tin has a relatively low melting point of 231.9 C (505.05 K). However, the boiling point of tin is 2270 C(2543K).Thisissu ciently high to allow for high anneal temperatures during di↵usion. The vapor pressure of tin at temperatures below 1000
3 Cislessthan10 Torr [39]. This provides an opportunity for vacuum annealing of tin at high temperatures for di↵usion. As a source of tin atoms for di↵usion, a thin film of tin was deposited on a clean silicon surface. An SOI wafer was used for this purpose since the thickness of the top silicon layer is very small. The buried SiO2 would provide a barrier for tin di↵usion, since the lattice structure of SiO2 di↵ers from that of tin, and the tin atom is too large for interstatial sites in SiO2. The wafer surface was cleaned using sonicated baths of Acetone, Isopropanol and deionized water. Tin was then deposited on the clean SOI wafer using RF sputtering. The deposition was done using Argon plasma (10 sccm) at 5 mTorr pressure. The Argon plasma was achieved using an RF power source. The deposition rate was kept at 0.5 A˚/sec. The deposition was done for 10 seconds to obtain a thickness of 5 A˚. This small thickness of tin layer was chosen to reduce the number of Sn atoms available for di↵usion, and hence to avoid doping the silicon sample degenerately. The silicon samples with Sn thin film were then annealed at two di↵erent tem- peratures, 500 Cand750 C, for 20 minutes. An inert Argon ambient with a steady gas flow of 120 sccm was maintained during anneal. The temperature ramp was done from room temperature to the di↵usion temperature in 1 minute. The samples were kept at the di↵usion temperature for 20 minutes to allow a uniform distribution of Sn atoms. The temperature was then gradually decreased to room temperature in 30 minutes. The gradual cooling of the sample ensured that there were no resid- ual thermal stresses on the wafer and the observed stress was only because of the incorporation of tin into the silicon lattice. 18 An expected value of the concentration of Sn in the top silicon layer of SOI can be calculated based on the atomic densities of the two elements and the thickness of the layers. If the di↵usion of all Sn atoms is assumed to be uniform throughout the top silicon layer, the percentage concentration of Sn in silicon is obtained as:
⇢SntSn ASn Sn(%) = (2.1) ⇢ ⇣t ⇢⌘t Sn Sn + Si Si ASn ASi ⇣ ⌘ Where, ⇢ is the density, t is the thickness and A is the atomic weight of the respective element. From the above equation, the expected concentration of Sn for a perfectly uniform distribution was calculated as 0.464 %. This ideal and uniform distribution, however, is not obtained in practice in case of limited source, solid state di↵usion. The concentration of the di↵using species varies with the depth of di↵usion according to a Gaussian profile. The peak of the Gaussian is obtained at the surface of the sample, where the concentration of the di↵using species is maximum. The mean value and variance of the concentration distribution profile depend on the di↵usion conditions. The calculated value for a perfectly uniform distribution of tin gives a lower bound for the concentration of tin at the wafer surface, assuming that all the tin atoms have di↵used into the silicon lattice.
2.3 Electrical characterization
The initial electrical characterization of the annealed samples was done using electrical resistivity measurement. The resistivity was measured using a standard four-point probe. Figure 2.1 shows the as-measured resistivity of the samples for the two anneal conditions. 19
Figure 2.1: Measured resistivity values for SiSn samples annealed at 500 Cand750 C. The mean and standard deviation values are represented using a box chart.
The resistivity of top silicon layer in the SOI wafer is 10-20 ⌦-cm, as given by the manufacturer. Thus, the incorporation of Sn reduces the resistivity of the silicon surface. The resistivity of a semiconductor is calculated using the following equation [40, 41]: 1 ⇢ = (2.2) q(Neµe + Nhµh)
Where, ⇢ is the resistivity of the semiconductor, q is the electronic charge, Ne and Nh are the electron and hole densities and µe and µh are the electron and hole mobilities. Since Sn does not act as either a donor or an acceptor impurity for silicon, the change in resistivity due to the inclusion of Sn has to be because of change in carrier mobility. This can be attributed to the straining of the silicon lattice due to Sn incorporation. 20 2.4 Physical characterization
The sample annealed at 750 C was then characterized using X-ray Di↵raction (XRD) to measure the strain in the silicon lattice due to Sn di↵usion. The 2✓ versus intensity plot for the sample is as shown in Figure 2.2.
Figure 2.2: 2✓ XRD peaks for SiSn sample annealed at 750 C. (Inset: XRD peaks for heavily-Sb-doped silicon [42].)
As seen in Figure 2.2, the Bragg peak for the SiSn sample was broad. Further, asmallsidepeakcouldbeobservedclosetothemainpeak.AsplitintheBragg peak indicates that the sample surface had several crystal phases. These phases with various interplanar distances create a strain in the lattice. The di↵erence in Bragg angles ( ✓B)ofthetwopeakswasestimatedtobe0.18degrees(648arcsec).The split in peak for SiSn closely matched the pattern for heavily-doped silicon [42], as shown in the inset for Figure 2.2. The peak split was compared to that for Sb, since the atomic size of Sn and Sb are similar. Thus, they would cause a similar amount 21 of strain in the lattice for a given atomic concentration. According to Bragg’s law of di↵raction [43]:
n d = (2.3) 2sin✓
Where, d is the distance between two atomic planes, is the wavelength of the X-Ray source used for XRD, ✓ is the angle between the incident X-Ray and the normal to the sample plane, and n is an integer. A standard copper K↵ source ( =1.5418 A˚) was used for the XRD measurement. Using this value for , from equation 2.3, the interplanar distance for the the main peak was calculated as 5.434 A˚. Since the orientation of the original silicon lattice was (100), this can be assumed to be the lattice constant for the crystal. This is slightly higher than the silicon lattice constant of 5.431 A˚ [44]. This shows that there was strain in the silicon lattice due to the incorporation of Sn atoms. The split in the peak of SiSn sample can be used to determine the strain on the silicon lattice. Di↵erentiating Bragg’s equation, we get: