Tin (Sn) - An Unlikely Ally to Extend Moore’s Law for Silicon CMOS? Thesis by Aftab Mustansir Hussain In Partial Fulfillment of the Requirements For the Degree of Masters of Science King Abdullah University of Science and Technology, Thuwal, Kingdom of Saudi Arabia December, 2012 2 Examination Committee Approval Form The thesis of Aftab Mustansir Hussain is approved by the examination committee. Committee Chairperson: Dr. Muhammad Mustafa Hussain Committee Member: Dr. Ian Foulds Committee Member: Dr. Aram Amassian 3 Copyright 2012 Aftab Mustansir Hussain All Rights Reserved 4 ABSTRACT There has been an exponential increase in the performance of silicon based semicon- ductor devices in the past few decades. This improvement has mainly been due to di- mensional scaling of the MOSFET. However, physical constraints limit the continued growth in device performance. To overcome this problem, novel channel materials are being developed to enhance carrier mobility and hence increase device performance. This work explores a novel semiconducting alloy - Silicon-tin (SiSn) as a channel ma- terial for CMOS applications. For the first time ever, MOS devices using SiSn as channel material have been demonstrated. A low cost, scalable and manufacturable process for obtaining SiSn by di↵usion of Sn into silicon has also been explored. The channel material thus obtained is electrically characterized by fabricating MOSCAPs and Mesa-shaped MOSFETs. The SiSn devices have been compared to similar devices fabricated using silicon as channel material. 5 ACKNOWLEDGEMENTS All praise is to Allah the almighty. I would like to express my deepest gratitude towards my supervisor and mentor Dr. Muhammad M. Hussain for the constant motivation, support and guidance. This work would not have been possible without his guidance. I also heartily thank Dr. Casey Smith and Kelly Rader for their invaluable advice and support throughout the course of this project. I would also like to extend special thanks to Dr. Aram Amassian and Dr. Ian Foulds for taking out the time to review this thesis. Finally, I am grateful to my parents, my wife, my brother and friends for their moral support. 6 TABLE OF CONTENTS Examination Committee Approval 2 Copyright 3 Abstract 4 Acknowledgements 5 List of Symbols 8 List of Figures 9 List of Tables 11 1 Introduction 12 2Di↵usion of Sn into Silicon 15 2.1 Tin di↵usivity into silicon . 15 2.2 Di↵usion conditions . 17 2.3 Electrical characterization . 18 2.4 Physical characterization . 20 2.5 Discussion . 22 3 Device Fabrication 24 3.1 SiSnMOSCAPfabrication . 24 3.2 SiSnMesa-shapedMOSFETfabrication . 29 4 Results and Discussion 35 4.1 SiSnMOSCAPcharacterization . 35 4.1.1 MOSCAPTheory......................... 35 4.1.2 Experimental details . 39 4.1.3 MOSCAPResults......................... 42 7 4.1.4 Discussion . 51 4.2 SiSnMOSFETcharacterization . 52 4.2.1 Experimental details . 52 4.2.2 MOSFETResults......................... 53 4.2.3 Discussion . 60 5 Conclusion 62 6 Future Work 65 References 66 Appendices 73 8 LIST OF SYMBOLS Relative dielectric constant with respect to vacuum. Ea Activation energy of di↵usion. D0 Pre-exponent term for di↵usion calculation (Di↵usion constant at infinite temperature). ⇢ Resistivity. 19 q Electronic charge (1.602 10− C). µ Carrier mobility. ⇥ ✓B Bragg’s angle of di↵raction. λ Wavelength of incident X-Ray. ✏ Crystal lattice strain. a Crystal lattice constant. EC Conduction band energy. EV Valence band energy. EF Fermi energy level. EG Semiconductor bandgap. φM Metal workfunction. φS Semiconductor workfunction. χS Semiconductor electron affinity. Qf Fixed oxide charge. Qt Trapped oxide charge. Qm Mobile oxide charge. Qit Interface trapped charge. Cox Accumulation capacitance. tox Dielectric thickness. ✏Al2O3 Permittivity of Al2O3. ✏SiO2 Permittivity of SiO2. VFB MOSCAP flatband voltage. Dit Semiconductor-dielectric interface defect density. Clf Low frequency inversion capacitance. Chf High frequency inversion capacitance. ⌘ Ideality factor for the MOS device. µlin Linear field e↵ect mobility. µsat Saturation field e↵ect mobility. 9 LIST OF FIGURES 2.1 Measured resistivity values for SiSn samples annealed at 500 Cand 750 C. The mean and standard deviation values are represented using aboxchart................................. 19 2.2 2✓ XRD peaks for SiSn sample annealed at 750 C. (Inset: XRD peaks for heavily-Sb-doped silicon [42].) . 20 3.1 MOSCAPmasklayout........................... 25 3.2 Sn depostion on silicon wafer and anneal. 25 3.3 Fieldoxidedeposition. 26 3.4 Fieldoxidepatterning. 27 3.5 Dielectric deposition. 28 3.6 Gate metal lift-o↵............................. 28 3.7 MOSFETmasklayers. .......................... 29 3.8 Sn di↵usion into silicon . 30 3.9 Device isolation. 31 3.10 Source/drain contact pad formation. 31 3.11 Dielectric deposition. 32 3.12 Dielectric patterning. 33 3.13 Gate metal definition. 33 3.14 a) A circular MOSCAP of 25 µm diameter. The pad oxide etched using the active layer mask is clearly seen below the gate metal. b) A circular MOSCAP of 250 µm diameter along with the contact pad. 34 3.15 a) A MOSFET with 8 µm wide fins at 1:2 pitch. b) Tilt SEM image of the source pad contacting the SiSn fins. The gap between the fins istheexposedburiedoxide(BOX)oftheSOI. 34 4.1 Band structure of MOSCAP for no applied gate voltage. 36 4.2 Flatbandconditionforann-typeMOSCAP. 37 4.3 Various modes of operation for an ideal n-type MOSCAP.. 38 4.4 Normalized capacitances for measured SiSn MOSCAPs. 41 10 4.5 FrequencyresponseofSiSnMOSCAPs. 41 4.6 Normalized capacitances for SiSn and Si MOSCAPs. 42 4.7 Linear fit for the depletion region of SiSn and Si MOSCAP. 43 4.8 Estimation of flatband voltage of SiSn and Si MOSCAPs. 45 4.9 Estimation of interface defect density of SiSn and Si MOSCAPs. 47 4.10 Hysteresis in CV characteristics of SiSn and Si MOSCAPs. The ab- solute di↵erence between forward (Cf )andreverse(Cr)capacitances has been plotted as a function of Vg................... 48 4.11 Comparision of I V characteristics for SiSn and Si MOSFETs. 53 d − g 4.12 Estimation of threshold voltage from I V characteristics of SiSn and d − g SiMOSFETs................................ 54 4.13 Estimation of subthreshold slope from I V characteristics of SiSn d − g andSiMOSFETs. ............................ 55 4.14 Estimation of linear mobility from I V characteristics of SiSn and d − g SiMOSFETs................................ 57 4.15 Estimation of saturation mobility from I V characteristics of SiSn d − g andSiMOSFETs. ............................ 58 4.16 Variation of saturation drain current of SiSn MOSFETs with e↵ective channelwidth................................ 60 11 LIST OF TABLES 2.1 Thebasicatomicpropertiesofsiliconandtin. 15 2.2 Comparison of reported activation energies of di↵usion of tin into silicon. 16 4.1 Comparison of basic capacitance values for SiSn and Si MOSCAPs. 50 4.2 Comparison of the calculated parameters for SiSn and Si MOSCAPs. 51 4.3 Comparison of the calculated parameters for SiSn and Si MOSFETs. 60 5.1 Comparison of basic MOSFET parameters for SiSn values obtained in this work and the reported GeSn values. (NR: Not Reported) . 63 12 Chapter 1 Introduction The semiconductor industry has seen an exponential increase in device performance over the past two decades. This rapid growth in technology was first predicted by the co-founder of Intel Corporation, Gordon Moore in his 1965 talk [1]. The trend has been popularly termed as the Moore’s law, and has mainly been a result of the constant scaling down of the dimensions of the silicon based transistor - the basic building block of CMOS technology. The advances in fabrication technology have scaled down transistor dimensions so much that the continuation of the Moore’s law with scaling will be physically impossible in the coming decade [2]. The reduction in transistor channel dimensions results in numerous problems such as short channel e↵ects, high gate leakage, high power dissipation, etc. To continue the exponential growth in transistor performance over the coming years, various approaches have been attempted. These e↵orts include, but are not limited to, use of strained silicon [3], use of high-/metal gate [4], change in the structure of the traditional planar transistor into three dimensional (3D) non-planar multi-gate FET (MugFET) [5]. Straining the silicon lattice to increase carrier mobility was introduced at the start of the past decade. Application of compressive and tensile strain on the channel as a way of mobility enhancement has been of key importance for sub-90 nm process node. The devices employing strained silicon channel have already made their way into IC products. The silicon channel was strained in these devices using a process-induced 13 strain technology [6]. This approach included several techniques such as stress liner technique [7, 8, 9], stress memorization technique [10, 11, 12, 13] and SiGe embedded source/drain [14, 15, 16]. In case of strained silicon, SiGe was generally embedded in pMOSFET source/drain to provide a compressive strain on the channel and enhance carrier mobility. Germanium has an electronegativity of 2.00 (Pauling scale) [17]. It is close to that of silicon - 1.90 [17]. The atomic radius of germanium is 125 pm and that of silicon is 110 pm [18]. Both, silicon and germanium belong to the same group, IVa, of the periodic table and display similar valencies. They crystallize in the diamond cubic crystal structure. Thus, according to Home Ruthery rules [19], they are capable of forming solid state solutions at all concentrations. According to Vegard’s law [20], the lattice constant of these solid solutions can be engineered to any value between that of silicon (5.431 A˚) and germanium (5.657 A˚)bycontrolling the relative concentration of the species in the solution. Thus, the silicon lattice can be e↵ectively strained by introducing germanium into the lattice. In past studies of strained Si, a thin layer of epitaxially grown SiGe was embedded in the source drain regions to enhance device performance [14, 15, 16].