ICEP2009 International Conference on Electronics Packaging April 14(Tue) -16(Thu), 2009 Kyoto International Conference Center, Kyoto, Japan

Advanced Program ICEP2009 International Conference on Electronics Packaging April 14(Tue) -16(Thu), 2009 Kyoto International Conference Center, Kyoto, Japan

The International Conference on Electronics and 45 technical sessions which include 17 core sessions that focus on Packaging (ICEP), of 2009 will be held from April recent trends and new areas of technology. The technical sessions 14th to April 16th at the Kyoto Kokusaikaikan, (the include more than 170 technical papers regarding packaging Kyoto International Conference Center), in Kyoto, technologies such as SiP/PoP, 3D packaging, and TSV/WLP, as well as Japan. Automotive Electronics concerns and information on Materials and University/Plant tours are planned to various Process issues. More than 20 student posters will also be presented. The places including RITSUMEIKAN University’s Micro-system Center conference promises to be a great event with something for everyone. and SR Center, as well as the TORAY Engineering Co., Ltd., Individuals who come to the conference will learn practical and (Equipment), SONY Mobile Display Corporation (LTPS; Low- profitable information and be able to participate in open discussions and Temperature Poly-Silicon), OMRON Corporation Electronic face-to face communication. Components Company Micro-devices (MEMS), and KYOCERA SLC We, the organization committee, are going to change the conference’s Technologies Corporation (PWB). These tours are planned on April focus to address what new paradigm shift is necessary in order to face 17th and are free of charge. Because the number of participants is current situations. We are looking forward to welcoming you to the limited, advanced registration is required. (early registration will be conference. given priority) Optional tours around Kyoto City are also available for a “Join us and let’s discuss JISSO together.”, “Let’s challenge for global reasonable fee. solutions.” and “Yes, we can!” The main focus of the ICEP2009 is “Collaboration”. The conference will focus on the collaboration between Science, Engineering and Technology as well as collaboration between other different technologies. Hideyuki Nishida The conference’s technical program will include three guest speakers ICEP2009 General Chairperson

Kyoto International Conference Center Access Sponsored by: Karasuma Line “Kyoto sta.” to “Kokusaikaikan sta.” Japan Institute of Electronics Packaging (JIEP) about 20 minutes. IEEE CPMT Society Japan Chapter From the 4th exit, 5 minutes on foot.

Contact: Secretariat of ICEP 2009 JIEP, 3-12-2 Nishiogi-kita, Suginami-ku Tokyo 167-0042, Japan http://www.jiep.or.jp/icep/ April 14 ICEP2009 Advanced Program Room A Room B1 Room B2 Room K 09:00 [14K-1] Energy / Environment 1. The IP Landscape for Photovoltaics C.E.Bauer, R.A.Fillion, H.J.Neuhaus (TechLead) (10:00) (10:00) (10:00) /USA [14A-1] High Performance Flip-Chip [14B1-1] Embedded Substrate Ⅰ [14B2-1] Optoelectronics Ⅰ 2. Developing Direct Methanol Fuel Cell from Packaging 1. WLP-IC Embedded Multi-layer Polyimide Wiring 1. Adaptive Quad 10-Gbps Optical I/O Module for Basic Research Results; Process View 1. Packaging Technologies for High Performance Board Power-Minimized Interconnection A.Suominen1, R.Jokinen2, M.Fonsell2, Computing System (Session Invite) S.Okude (Fujikura)/Japan R.Kuribayashi, I.Hatakeyama, D.Inami, T.Hino, A.Tuominen1 (1University of Turku, 2Turku J.Inasaka (NEC)/Japan T.Sugimoto, K.Kurata (NEC)/Japan University of Applied Sciences) /Finland 2. Development of Embedded Passive / Active 2. Spatial/Transient Thermal Resistance for High Devices Technology for Simultaneous Pressing 2. Low-Loss, Chip-Based Optical Interconnects on 3. Developing Direct Methanol Fuel Cell from Performance FC Packages (Session Invite) Process Waveguide-Integrated SLC Basic Research Results; Technical Aspects 1 1 1 2 2 1 2 K.Yazawa (SONY)/Japan H.Kamiya (DENSO)/Japan S.Nakagawa , H.Numata , Y.Taira , K.Kobayashi , R.Jokinen , A.Suominen , M.Fonsell , K.Terada2, M.Fukui2 (1IBM, 2Kyocera SLC A.Tuominen1, (1University of Turku, 2Turku 3. Facing Issues for Next Generation High Density 3. IMB Technology for Embedded Active and Technologies)/Japan, University of Applied Sciences)/Finland Passive Components in SiP, SiB and Single IC Build Up Package Fabrication and the 3. Embedded Micromirror Fabricated by Using 4. Innovative Jisso Structure by Skeleton Circuit Package Applications Alternative Solutions (Session Invite) Liquid Immersion Exposure for Thin Film Optical Structure S.Koyama (Shinko Electric Industries)/Japan R.Tuominen, T.Waris, J.Mettovaara (Imbera H.Hayashi (The University of Tokyo) /Japan Electronics)/Finland Interconnects K.Shimizu, T.Muranishi, J.Inoue, K.Nishio, (10:40) 4. Power Integrity Optimization for a High- K.Kintaka, Y.Awatsuji, S.Ura (Kyoto Institute of performance Microprocessor in Low-cost Technology)/Japan (10:50) Systems [14K-2] Lead Free / Environment 11:15 S.Suminaga, H.Mori, T.Nishio (IBM Japan) /Japan 1. Effect of Mn Addition on Properties of Sn-Ag- Cu-In Quaternary Lead-free Solder Alloy 11:25 (11:40) [14B1-2] Embedded Substrate Ⅱ [14B2-2] Optoelectronics Ⅱ A.-M.Yu1, J.-K.Kim1, J.-H.Lee2, M.-S.Kim3 (1Korea 1. Feasibility Study of Designing RF Band-pass 1. Multimode Polymer Optical Waveguide with Institute of Industrial Technology, 2Seoul National Filters Using Embedded Passives Technique Graded-Index Rectangular Cores for Optical University of Technology, 3Inha University)/Korea on Organic Substrate Printed Circuit Broad K.-C.Chin (Industrial Technology Research T.Kosugi (Keio University)/Japan 2. Inhibition of Cracking in Cu6Sn5 Intermetallic Institute)/Taiwan Compounds at Sn-Cu Lead-Free Solders and 2. Reflowable Surface Mount Optical Encoder Cu Substrate Interfaces 1 2 1 2. Experimental Study of High Speed J.Hane, Y.Kuroda, H.Fujita, T.Ito, I.Komazaki, K.Nogita , S.Suenaga , S.D.McDonald , 1 1 2 1 Transmission Performance of Substrate with E.Yamamoto (Olympus)/Japan H.Tsukamoto , J.Read , T.Nishimura ( The 2 Embedded Active Device University of Queensland, Nihon Superior) M.Tanaka (Dai Nippon Printing)/Japan 3. Reliability Improvement of Optical Devices by /Australia, Japan Using Newly Developed Highly Moisture 3. Impact Strength of Sn-Cu (-Ni) Lead-Free Solder 3. Fabrication of Thin-Film Capacitors Using Durable Optical Adhesives Ball Grid Arrays Placed on Cu Substrates Aerosol CVD for High Performance Ceramic S.Mitachi (Tokyo University of Technology) H.Tsukamoto1, T.Nishimura2, S.Suenaga2, Package Applications /Japan S.D.McDonald1, J.Read1, K. Nogita1 (1The S.Wang, A.Hattori, Y.Ozeki, W.Zhang, H.Ogawa University of Queensland, 2Nihon Superior) (Noda Screen)/Japan /Australia, Japan 4. Microstructure and Mechnical Properties of Sn- Bi Eutectic Solder S.Sakuyama (Fujitsu Laboratories)/Japan

(12:30) 12:40 12:40 Lunch time Lunch time Lunch time Lunch time

Poster Session Poster Session Poster Session Poster Session

13:40 Japanese Noh Drama (Room A)

13:55 Welcome Ceremony & Awarding Ceremony ICEP2008 14:25 (Room A) 14:25 Invited Speeches (Room A)

1. Packaging Technology Roadmap - An IBM Perspective Peter Brofman (IBM)

2. Memory Packaging Strategy with Sophisticated Technology Takayuki Watanabe (Akita Elpida Memory)

3. Photovoltaic as An Energy Solution Tetsuroh Muramatsu (Sharp) 17:35

18:00 Welcome Reception (Banquet Hall “Swan”) 20:00 April 15 ICEP2009 Advanced Program Room A Room B1 Room B2 Room K

09:00 [15A-1] Advanced Packaging Ⅰ [15B1-1] Embedded Substrate Ⅲ [15B2-1] Interconnections Ⅰ [15K-1] Electrical Solutions Ⅰ 1. A Reliability Test on PBGA Packaging Through 1. Novel Approach in Design and Test of 1. Effect of the Formation of the Intermetallic 1. Effects of Uni-axial Mechanical Stress on the Piezoresistive Stress Sensor Embedded Capacitors in Organic-based Commpounds between a Tin Bump and an Scattering Parameters of Metal-oxide- C.H.Liu1, H.Chung1, D.W.Yang1, K.F.Tseng2, Substrate for Highly Compact RF Systems-in- Electroplated Copper Thin Film on Both semiconductor Field Effect Transistors B.J.Lwo1 (1National Defense University, 2Chin- Package Devices Mechanical and Electrical Properties of the Y.Han1, M.Koganemaru2, T.Ikeda3, N.Miyazaki3, Min Institute of Technology)/Taiwan C.Romero, J.Lim, Y.H.Yoon, T.Kim, S.Yi Jointed Structures Y.Kiyotaka4, W.Choi4, H.Tomokage4 (1Fukuoka (Samsung Electro Mechanics)/Korea S.Jeong, K.Suzuki, H.Miura (Tohoku University) Industry Science & Technology Foundation, 2. Evaluation of the Effect of Packaging Process /Japan 2Fukuoka Industrial Technology Center, 3Kyoto Parameters on Semiconductor Devices with 2. Electrodeposition of High-k Titania Thin Films University, 4Fukuoka University)/Japan Low-k Conductive Layers for Embedded Capacitors 2. Comparison of Thermal Fatigue Life of SAC 1 2 1 T. Yamada , M.Masumoto , O.Horiuchi , B.K.Roy, J.Cho (State University of New York Solder Joints and SnPb Solder Joints with 2. Bandwidth Simulation for High Speed Memory 2 1 H.Tomokage ( Fukuoka Industry, Science & Binghamton)/USA Various Stress Ranges C.-P.Chen, J.-H.Cheng, W.-J.Fan, N.-C.Lin, 2 Technology Foundation, Fukuoka S.W.R.Lee, C.Yang, Y.S.Chan (Hong Kong University T.-F.Su (Powertech Technology)/Taiwan University)/Japan 3. The Nanotransfer Technology of the PZT of Science and Technology)/Hong Kong 3. The Solder Blister Control for Lead Frame Capacitor for the Application of Embedded 3. Thermomigration in Eutectic SnPb Solder Joint 3. Preliminary Study and Design of CMOS Diode Packages Substrate Y.Tao1, Q.Cheng1, G,-R.Tang1, B.Wang1, B.An1, for Electrostatic Discharge Protection J.W.Chen1, S.Lee1, B.Appelt2, A.Tseng2 S.Makino, M.Ichiki, R.Maeda, T.Suga (The F.-S.Wu1, Y.-P.Wu1,2 (1Huazhong University of N.F.Muhammad, A.Ibrahim, A.R.Ahmad, (1Advanced Semiconductor Enginrrring, University of Tokyo, AIST, JST-CREST)/Japan Science and Technology, 2Wuhan National M.R.Yahya (Telekom Research & Development) 2ASE(US))/Taiwan, USA (10:15) Laboratory for Optoelectronics)/China /Malaysia 4. First Generation of Stretchable No-Light (10:25) 4. Concave Shape in Gold-Solder Interconnection 4Electrical Characterization of Micro Spring Emitting Display Based on Stretchable [15B1-2] LED System Probe Card for Wafer Level Testing Electronic Technologies for Textile Application 1. Refraction Index, Transmittance and Shape J.-Y.Park, E.-J.Choi, S.-C.Lee, Y.-B.Sun (Kyonggi H.-Y. Chang (Advanced Semiconductor 10:40 A.Fabrice (IMEC)/Belgium Dependence of Light Extraction from Near- University)/Korea Engineering)/Taiwan ultraviolet Light-emitting Diode 10:50 [15A-2] Advanced Packaging Ⅱ H.Hayashi (Yamaguchi University)/Japan [15B2-2] Interconnections Ⅱ 5. A Target Impedance Profile of Power 1. Low-Temperature Wafer Bonding by Ar-Beam 1. Development of Ultrasonic Flip-Chip Bonding Distribution System Considering On-Chip Model Surface Activation 2. Luminous and Thermal Characteristics of High Interconnection Technologies for COB Modules N.Takahashi1, K.Kagawa2, K.Hoshino3 (1IBM Y.-H.Wang, S.Taniyama, T.Suga (The University Power Near-ultraviolet LED Packages with K.Marusaki (Sharp)/Japan Japan, 2ATE Service, 3Shibaura Institute of of Tokyo)/Japan Various Chip Arrangemants Technology)/Japan K.Kamon (Yamaguchi University)/Japan 2. Chip-on Flex(COF) BondingTechnologyUsing (11:05) 2. Wafer-to-Wafer Alignment Using Moire Pattern Tin Bumps and Non-Conductive Adhesives and its Interests for 3D Integration 3. Analysis of Thermal Performance for High (NCAs) for CMOS Image Sensor Device (11:15) C.Wang, T.Suga (The University of Tokyo) Power Light Emitting Diodes Lighting Modulus K.-M.Harr1, D.-H.Kim1, Y.-M.kim1, H.-Y.Cho1, [15K-2] Electrical Solutions Ⅱ /Japan W.-H.Chi, T.-L.Chou, C.-N.Han, S.-Y.Yang, C.-B.Lee2, J.-G.Kim2, S.Yi2, Y.-H.kim1 (1Hanyang 1. The Possibility of JISO using Micro Contact K.N.Chiang (National Tsing Hua University) University, 2Samsung Electro-Mechnics)/Korea S.Yoshida, S.Murata, K.Soeta (ALPS 3. A Multilayer Process for 3D-Molded- /Taiwan Electric)/Japan Interconnect-Devices to Enable the Assembly 3. Evaluating the Performance of Thermosetting of Area Array Based Package Types 4. Thick Film Pastes for the Manufacture of Low Resins under Ultrasonic Bonding Process 2. High-speed Intra-Body Transmission System T.Leneke (Otto-von-Guericke University of Cost, Insulated Aluminum Substrates for Use as S.H.Huang1, H.C.Chen1, C.L.Chung1, S.L.Fu1, Using 2 - 28 MHz OFDM Modulation Magdeburg)/Germany Integrated Heat Sinks for High Intensity LEDs S.C.Ho2, A.H.Liu2, Y.J.Lee2 (1I-Shou University, F.Koshiji, S.Takenaka, K.Sasaki (The University K.Takarabe (ESL Nippon)/Japan 2ChipMOS Technologies)/Taiwan of Tokyo)/Japan 4. 3D Packaging: up to 30 GHz for Integrated Antenna Front-Ends 5. The Behavior of Thermal and UV Degradiation 4. An Anisotropic Conductive Adhesive Improved 3. RFID and its Applications in Tourism C.Drevon1, B.Bonnet1, P.Monfraix1, R.Chiniard1, between LED Encapsulation and their Devices by Carbon Nanotubes and Its Application on T.Hu (Aizu University)/Japan C.Val2, H.Legay1, P.Couderc2, J.-L.Cazaux1 C.-W.Hsu, C.-H.Lin, H.-T.Li, S.-C.Huang, RFID Tag Inlays Packaging (1Thales Alenia Space, 23DPlus) /France K.-C.Chen (Industrial Technology Research X.-H.Cai1, B.An1, F.-S.Wu1, Y.-P.Wu1,2 (1Huazhong Institute)/Taiwan University of Science and Technology, 2Wuhan 12:30 National Laboratory for Optoelectronics)/China 12:30 Lunch time Lunch time Lunch time Lunch time 13:30 Poster Session Poster Session Poster Session Poster Session 13:30 [15A-3] 3D/TSV Ⅰ [15B1-3] Printed Electronics Ⅰ [15B2-3] Interconnections Ⅲ [15K-3] Mechanical Solutions 1. Integration of Compliant Bump with Through-Si- 1. Printable Electronics on Flexible Substrate by 1. The Semi-experiment Analysis of the Wire Sweep of a 1. Measurement of Three-dimensional Surface Via Technology and Its Application Back-Side Inkjet Technology (Session Invite) Wire Bond during the Transfer Molding Process Displacement Using the Digital Image Illuminated CMOS Image Sensor(Session S.Nishi (Konicaminolta IJ Technologies)/Japan H.-K.Kung1, H.-S.Chen1, H.-C.Hsu2 (1Cheng Shiu Correlation with AFM Images Invite) University, 2I-Shou University)/Taiwan N.Shishido, T.Ikeda, N.Miyazaki (Kyoto T.Asano1, N.Watanabe2, I.Tsunoda2, Y.Takao1, 2. Palm Top Sized Super Fine Inkjet System and University)/Japan K.Tanaka3, T.Higashimachi4, Y.Yamaji5, M.Aoyagi5, Mask Less Direct Patterning (Session Invite) 2. Micro-bumping Technology by PPS Method T.Kyotani6, H.Arao7, Y.Kimiya8, K.Fukunaga8, K.Murata, K.Shimizu (Advanced Industrial K.Tsuruta (Senju Metal Industry)/Japan 2. Multi-angle View Visual Inspection of Solder A.Ikeda1, Y.Kuroki1, T.Tsurushima1 (1Kyushu Science and Technology)/Japan Joints with Neural Networks University, 2Fukuoka Industry Science & 3. Flip Chip Assembly on 50-um-pitch Pads M.Matsushima (Osaka University)/Japan Technology Foundation, 3Kyushu Sangyo 3. Electric Conductive Film Formations by Ink-jet Soldered with Precoat by Powder Sheet University, 4Sojo University, 5AIST, 6PMT, 7JGC using Individually Dispersed Nanoparticle Ink H.Noma (IBM Japan)/Japan 3. Package Warpage Simulation Using FEM Catalysts and Chemicals, 8Yoshidama Surface formed by Gas Evaporation Method (Session Visco-Elastic and Cure Degree Coupling Finishing) /Japan Invite) 4. Investigation on Wet-Chemical Surface- I.Hirata (NEC)/Japan 2. 3D Packaging and Interconnect Technologies at M.Oda (ULVAC)/Japan Cleaning of Au Bump for Low-Temperature CEA-Leti Minatec (Session Invite) Chip Stack-Bonding Using Compliant Bump 4. Numerical Simulation of Variable Frequency 1 2 1 1 M.Scannell (CEA-Leti)/France 4. Inkjet Printing of Silver Nanopaste for Printed T.Mori , N.Watanabe , T.Asano ( Kyushu Microwave Curing of Underfill Materials Electronics (Session Invite) University, 2Fukuoka Industry Science & T.Tilford1, K.I.Sinclair2, C.Bailey1, 3. TSV and Wafer Level Packaging Approaches S.Abe (Harima Chemicals)/Japan Technology Foundation)/Japan M.P.Y.Desmulliez2 (1University of Greenwich, to 3D Packaging 2Heriot-Watt University)/UK E.J.Vardaman (TechSearch International)/USA 5. Silver and Copper Nanoparticles and Their 5. Formation of Micro Au Bump Array for Flip-Chip 4. Thermal Characterization of a Three- Application to Wring Formation and Joining Bonding using Electroless Au Deposition 5. Substrate Trapezoidal Trace Shape Modeling 1 1,2 1 1 dimensional (3D) Chip Stack (Session Invite) T.Yokosima , K.Nomura , Y.Yamaji , K.Kikuchi , L.C.Kim, B.J.Kai (Intel Microelectronic)/Malaysia 1 1 1,2 3 K.Matsumoto, Y.Taira (IBM)/Japan M.Nakamoto (Osaka Municipal Technical H.Nakagawa , K.Koshiji , M.Aoyagi , R.Iwai , Research Institute)/Japan T.Tokuhisa3, M.Kato3 (1National Institute of 5. Bonding Strength Estimation of BCB Dielectric Advanced Industrial Science and Technology, Film in 3D Stacked IC Packages 2Tokyo University of Science, 3Kanto M.-C.Hsieh, C.-Y. Cheng, W.Lee, R.-M. Tain Chemical)/Japan (Industrial Technology Research Institute) 15:35 /Taiwan 15:45 [15A-4] 3D/TSV Ⅱ [15B1-4] Printed Electronics Ⅱ [15B2-4] Interconnections Ⅳ [15K-4] Thermal Management Ⅰ 1. Inter Chip Fill for 3D Chip Stack 1. Advantages of Ink-Jet Printing in LTCC 1. Room Temperature Sintering and Bonding with 1. Thermal Design of RGB LED Modules A.Horibe, F.amada, J.Knickerbocker, C.Feger Production Technology (Session Invite) Ag Nanoparticle Paste A.Andonova, N.Kafadarova (Technical (IBM)/Japan Y.Kawamura (KOA)/Japan D.Wakuda, K.-S.Kim, K.Suganuma (Osaka University Sofia)/Bulgaria University)/Japan 2. Comprehensive Thermomechanical Lifetime 2. Die-cracking Evaluation of Silicon Chip Coverd 2. Embedded Passives with High Precision and Calculation of a Soldered Assembly with Polymer Film for 3D Chip Stacking Wide Range Build on Plastic Substrates 2. Fablication of Large-scale Nanoparticle Array G.Massiot, M.Grieu, O.Maire, C.Munier (EADS Packages M.Nakayama (NY Industries)/Japan using Combination of Self-assembly and 2-step C.-J.Wu1, M.C.Hsieh2, K.N.Chiang1 (1National Transfer France)/France 2 Tsing-Hua Univercity, Industrial Technology 3. Advanced Fine Line Thick Film Conductors K.Sugano, T.Ozaki, R.Hiraoka, T.Tsuchiya, 3. Experimental Simulative Analysis for Thermal Research Institute)/Taiwan with High Conductivity and Solderability Build O.Tabata (Kyoto University)/Japan Performances of Vertical Stacked Die 3. Characterisation of Through Silicon Via (TSV) by Screen-printing 3. Direct Bonding to Aluminum Utilizing Silver- Packages Processes Utilising Mass Metrology D.K. Numakura (DKN Research)/USA oxide Particles C.-K.Yu, C.-K.Liu, S.-L.Kuo, M.-J.Dai, Y.-L.Chao, L.Cunnane, A.Kiermasz, G.Ditmer (Metryx) /UK Y.Yasuda, E.Ide, T.Morita (Hitachi)/Japan C.-Y.Hsu, R.-M.Tain (Industrial Technology 17:00 Research Institute)/Taiwan 17:10 [15A-5] 3D/TSV Ⅲ [15B1-5] Printed Electronics Ⅲ [15B2-5] Interconnections Ⅴ [15K-5] Thermal Management Ⅱ 1. Cost Effective PVD Solution which Enable TSV 1. Fabrication of RF Circuit Structures on a PCB 1. Quantitative Measurement of Air-gap of 1. Radiation Cooling Effects on LSI Chip Integration in the Emerging 3-D Market Material by Inkjet Printing and Electroless Silicon/Silicon Interfaces Temerpature with an Alumina Heat Sink of B.Ninan, A.Wang (Tango Systems)/UK Plating M.M.R.Howlader, M.G.Kibria, F.Zhang, T. Suga High Infrated Emmisivity Material A.Sridhar1, M.Perik2, J.Reiding2 (1University of (McMaster University)/Canada K.Shinagawa1, M.Nishimura2, S.Hirokawa1, 2. Delivering High Reliability from a Wafer-Scale, Twente, 2Saxion Hogeschool)/The Netherlands Y.Muto1 (1Canon Marketing Japan, 2NISHIMURA Chip-Sized Package Incorporating a Through 2. Evalution of Electric Contact Phenomena under PORCLEAN)/Japan Silicon Via Solution 2. Effects of Cold Crystallization on Morphology Small Contact Load M.Kriman (Tessera)/Israel and Thermal Charctterstic of Poly (9, 9-di-n- O.Mukhtar (Osaka University)/Japan 2. Emissivity Stability Investigation of Substrates octyl-2, 7-fluorene)(PFO) and Layers in Microelectronics 3. Development of Interconnect Technology in 25 B.-Y.Su1, H.C.Chen1, C.L.Chung1, S.L.Fu1, 3. True 3D Through Hole Interconnections V.Videkov, A.Andonova, N.Kafadarova Micron Pitch for Low Cost CoC(Chip on Chip) C.-Y.Ou2 (1I-Shou University, 2Research Alliance H.Wakioka (Fujikura)/Japan (Technical University Sofia)/Bulgaria T.Norimatsu (Fujitsu Microelectronics)/Japan Taiwan TFT LCD Assciation)/Taiwan 3. Precursor Monitoring Approach for Reliability (18:25) 4. Open Lead Detection Circuit for QFP ICs Using Assessment of Cooling Fans 3. Pattering of ITO Microwire Using Laser-induced Logic Gates as Open Sensors T.Shibutani1, H.Oh2, M.Pecht2 (1Yokohama National Thermal Printing Method M.Hashizume (University of Tokushima)/Japan University, 2University of Maryland)/Japan, USA S.Iwasaki1, T.Sano1, S.Katsura2, K.Yoshida3, A.Nakayama4, A.Hirose1 (1Osaka University, 4. Design and Optimization of 3D Manifold of 2Nippon Denki Kagaku, 3General Technology, Microchannel Heat Sink using the Porous 4Ion Technology Center)/Japan Media Approach (18:25) L.F.Yau (Nationa University of Malaysia) 18:50 /Malaysia April 16 ICEP2009 Advanced Program Room A Room B1 Room B2 Room K

09:00 [16A-1] SiP/PoP Advanced Assembly Ⅰ [16B1-1] Material Ⅰ [16B2-1] MFG/Process Ⅰ [16K-1] RF / RFID Ⅰ 1. PoP Technology for Mobile Phone 1. Low-temperature Curable and Electrically 1. Design of Experiment (DOE) Study for the 1. Experimental Study of the Isolation Manufacturing Ð Past, Present and Future Conductive Paste for Touch Panels and LCD Optimization of Lapping Process of GaAs Wafer Performance of 0.18-um CMOS RF Bond Pad (Session Invite) Panels for Wireless Device Application M.A.Ismail, N.F.I.Muhammad, A.I.A.Rahim, Y.Wada (Nokia Japan)/Japan J.Bai, R.Chu, S.Gupta (Henkel Japan)/Japan N.H.Ghazali, N.A.Omar, N.A.Ngah, A.Dolah, M.R.Yahya, A.F.A.Mat (Telekom Research & M.R.Yahya (Telekom Research & Development) Development)/Malaysia 2. 3D Technology Roadmap and the Global 2. The Effect of Conductive Particle Parameters /Malaysia Competition (Session Invite) on Electronical Conductvity in Anisotropic 2. The Thin Type Electromagnetic Wave H.Nakajima (NEC Electronics)/Japan Conductive Film Joints 2. A Forming Method of Cavity Structure with Absorption Wall Having Optical Ray Passage J.-H.Kuang, C.-M.Hsu (National Sun Yat-Sen LTCC Substrate Using Photo Resist Film Property 3. Flip Chip SiP and Advances (Session Invite) Universtity)/Taiwan Y.Akagi (Nihon University)/Japan Y.Okano (Musashi Institute of Technology)/Japan H.Shimamoto (Renessas)/Japan 3. Study of the Filler Effect on the Effective 3. Inductive Modeling of Laser Trimming of Film Thermal Conductivity of Thermal Conductive Resistors 3. Development of System that Recognizes 4. (Session Invite) Adhesive J.Autonov (The Ulyanovsk State Technical Conglomerate RF-ID Tag in UHF Band A New Novel Dual Face Package Y.Zhang1, C.Yue1, J.Liu1,2, Z.Cheng2, J.-Y.Fan1 University)/Russia M.Ochiai (Musashi Institute of M.Ishihara (Kyushu Institure of Technology) (1Shanghai University, 2Chalmers University of Technology)/Japan /Japan Technology)/China, Sweden 4. Influence of Deformation of Single Crystalline Copper on its Surface Activated Bonding at 4. Development of Small Tunable Antenna for 4. Thermal Conductivity of Electrically Conductive Room Temperature Multi-frequency Band Adhesives Containing Fillers with Multi-modal R.Takagishi, M.Akaike, T.Suga (The University of H.Fukasawa (Musashi Institute of Technology) Paricle Size Distibutions Tokyo)/Japan /Japan M.Inoue1, J.Liu2,3 (1Osaka University, 2Chalmers University of Technology, 3Shanghai University) 10:40 /Japan, Sweden, China 10:50 [16A-2] SiP/PoP Advanced Assembly Ⅱ [16B1-2] MEMS / TSV Key Technologies [16B2-2] MFG/Process Ⅱ [16K-2] RF / RFID Ⅱ 1. Gold Stud Bumps for Hight Performance Flip 1. Micropump with Cross-junction Channels for 1. Studies on Low-temperature Direct Bonding 1. Development of the Meosurement System of Chip Packages Application in Gas Rate Sensor Methods of PMMA and COP Using Surface Sheet Resistance at Microwave Frequency W.Chen1, K.Shen1, A.Wang1, Y.Lai1, B.Appelt2, V.T.Dau, K.Tanaka, S.Sugiyama (Ritsumeikan Pretreatment Range Using DFFC A.Tseng2 (1Advanced Semiconductor University)/Japan H.Shinohara, J.Mizuno, S.Shoji (Waseda T.Tosaka, A.Nishitaka, K.Fukunaga, Y.Yamanaka Enginrrring, 2ASE(US))/Taiwan, USA University)/Japan (NICT)/Japan 2. An Investigation into Deep RIE-based Through- 2. Evaluation of High Frequency Characteristics of 2. Novel Compact Connector for PoP and BoB Si-Via(TSV) Microfabrication for 3-D System-in- 2. High Reliability Encapsulant Liquid Resin for FPC during Bending Applications package(SiP) Integration SIP - The Simultaneous Process of over Mold T.Tanaka (Nitto Denko)/Japan K.-S.Choi1, H.-C.Bae1, D.-S.Jun1, J.-T.Moon1, M.Miao1,2, Y.Jin1, H.Liao1, L.Zhao1, Y.Zhu1, X.Sun1 and Underfill by VPES(Vacuum Printing K.-B.Cha2, D.-Y.Kim2, Y.-I.Jun1 (1Electonics and (1Peking University, 2Beijing Information Science Encapsulation Systems) 3. Utilizing Scalable Model to Fast Synthesize Telecommnucations Resarch Institute, and Technology University)/China K.Nagai, Y.Ishikawa, A.Okuno (SANYU REC) High Performance RF Integrated Passive 2Unisemicon)/Korea /Japan Circuits Applited to SiP Module 1 1 1 1 3. Cu Fill Properties in the High Aspect Ratio C.-C.Wang , H.-A.Yang , J.Chen , T.-C.Lin , 1 2 3 1 3. Wettability and Reliability on Double Side Through Si Via Hole by Electroless Plating 3. A Novel Metal-to-metal Bonding Process C.-T.Chiu , S.-M.Wu , C.-W.Kuo , C.-P.Hung 1 Assembly with MPS-C2 Flip Chip Technology 1 2 2 3 - ( Advanced Semiconductor Engineering, F.Inoue , K.Yamamoto , S.Tanaka , Z.Wang , Utilizing Low-temperature Sinterability of Ag2O 2 3 H.Noma, Y.Oyama, H.Nishiwaki, M.Takami, S.Shingubara1 (1Kansai Uninersity, 2National derived Ag Nanoparticles National University of Kaohsiung, National Sun T.Takatani, K.Toriyama, Y.Orii (IBM Japan) Institute of Communication Technology, N.Takeda1, H.Tatsumi1, Y.Akada1, T.Ogura *1, Yat-Sen University)/Taiwan /Japan 3Shaanxi Normal University)/Japan, China E.Ide2, T.Morita2, A.Hirose1 (1Osaka University,2 4. High Performance RF Intergrted Possive Hitachi)/Japan Circuits Design on Glass Wafer 4. Effect of Packaging Process Parameters on the 4. Electrohydrodynamic Micropumps for C.-C.Wang1, H.-A.Yang1, J.Chen1, M.-H.Li2, Damage of Semiconductor Device with Low-k Electronic Chip Cooling Applications (Session 4. Assembly Technique of 0402size Chip on C.-T.Chiu1, S.-M.Wu2, C.-W.Kuo3, C.-P.Hung1 Materials Invite) Flexible Printed Circuits (1Advanced Semiconductor Engineering, M.Masumoto1, O.Horiuchi2, T.Yamada2, P.R.Selvaganapathy, C.Y.Ching(McMaster T.Kitada (Fujikura)/Japan. 2National University of Kaohsiung, 3National Sun J.Morishita3, W.Choi4, H.Tomokage4 (1Texas University)/Canada Yat-Sen University)/Taiwan Instruments, 2Fukuoka Industry, Science & Technology Foundation, 3Walts, 4Fukuoka 5. Band Pass Filter Design and Optimization on University)/Japan High-Resistivity Silicon for 5GHz RF Front End Receiver Y.Tsuchiya (IBIDEN)/Japan

12:30 (12:55) 12:30 Lunch time Lunch time Lunch time Poster Session Poster Session Poster Session 13:30 Lunch time 13:30 [16A-3] Fine MEMSⅠ [16B1-3] Automotive Electronics, Future [16B2-3] MFG/Process Ⅲ Poster Session 1. Nano-mechanical Structure Fabrication Requirements 1. Die Product Assembly on Flex Substrate (13:55) Technology for Highly Integrated, Complex 1. Launch-up of Adopting BGA into Engine ECU T.Onishi (Grand Joint Technology)/Hong Kong MEMS (Tentative) (Session Invite) in Japan (Session Invite) [16K-3] Reliability I. Shimoyama (The University of Tokyo)/Japan H.Ueda (SemiConsult)/Japan 2. Investigation of Flip Chip Bonding with NCF 1. Failure Analyses and Lifetime Parameters for (Tentative) 2. Development of IGBT Power Module with N.Asahi, K.Fujimaru, T.Nishiyama, K.Kasumi, Lifetime Monitor of VIA Structures on Printed K.Matsumura, T.Nonaka (Toray Industries) Circuit Boards 2. High Density Integration Technology with Laser Anodized Metal Substrate (AMS) for Hybrid /Japan M.Fujino, T.Suga (The University of Tokyo) Assisted Inkjet Writing (Session Invite) Electric Vehicle (HEV) Application (Session Invite) /Japan J.Akedo (National Institute of Advanced 3. Flip Chip Bonding with Elasticity Bonding Industrial Science and Technology)/Japan S.Gao, J.Kim, D.Yoo, S.Choi, S.Yi (Samsung Electro-Mechanics)/Korea System (EBS) Method 2. Study on Improving the Drop Impact Reliability 3. Highly Integrated MEMS-Pseudo-SOC R.Kojima (Sony Chemical & Information Device) of Plastic Core Solder Ball Technology (Session Invite) 3. Design Concepts of New Components for Next /Japan R.-D.Sun, N.Okinaga, K.Matsushita, M.Okuda H.Yamada (Toshiba)/Japan Generation Automotive Power Electronics (Sekisui Chemical)/Japan (14:45) (Session Invite) 4. Effect of the Excimer Irradiation Process on the T.Tominaga (CalsonicKansei)/Japan Interconnection of Flip Chip Bonding 3. Solder Joint Lifetime Evaluation of WLP and 1,2 1 1 1 (14:55) K.Sakuma , N.Nagai , J.Mizuno , S.Shoji Cause 4. Ink Jet Marking on Bare Die for Chip 1 2 [16A-4] Fine MEMSⅡ Traceability (Session Invite) ( Waseda University, IBM)/Japan T.Matsuzaki (CASIO COMPUTER)/Japan 1. High Density Packaging Technology Using Low H.Kawaguchi (Toray Engineering)/Japan Temperature Chip Stacking for Fine-MEMS 4. Impact Reliability Studies of Sn-Ag-Cu-Ni BGA (Tentative) (Session Invite) Solder Joints on Electroless Ni-P/Au Surface 15:10 M.Koyanagi, T.Fukushima, T.Tanaka (Tohoku Finish 15:20 University)/Japan (Tentative) [16B1-4] Automotive Electronics, Challenges [16B2-4] Substrate Ⅰ F.Kawashiro (NEC Electronics)/Japan 1. Thermal Management of LED Headlamp 2. Mass-production Technology for Vertical 1. Microstructural and Dielectric Characterization System (Session Invite) 5. Effects of Multiple Reflows on Interfacial Integrated MEMS (Session Invite) of Alumina-Based LTCC Materials S.Gao, S.Shin, Y.Lee, J.Kim, S.Choi, S.Yi 1 1 2 Reactions and Shear Strength of SnAgCu S.Lee (OMRON)/Japan A.Ibrahim , R.Alias , M.H.A.R.M.Ahmad , (Samsung Electro-Mechanics)/Korea C.S.Mahmood2, M.R.Yahya1, A.F.A.Mat1 Sojder Joints with Cu-Zn Wetting Layer 1 2 Y.M.Kim, S.W.Ma, Y.-H.Kim(Hanyang University) 3. Wafer-Level Bonding Technology for Different ( Telekom Research & Development, MTEC) 2. Pb-free High Temperature Solder Joints for /Korea Materials (Session Invite) /Malaysia Power Semiconductor Device (Session Invite) E.Shimizu, T.Suyama, R.Ohta (Olympus)/Japan (16:00) Y.Yamada1, Y.Takaku2, Y.Yagi1, I.Nakagawa3, (16:10) 2. Thermal Conductivity Characterization of Al2O3- T.Atsumi3, M.Shirai3, I.Ohnuma4, K.Ishida4 (16:10) SiO2-PbO-MgO Tape System for High (1Toyota Central Research & Development (16:20) Frequency Substrate [16K-4] Material Ⅱ Laboratories, 2Tohoku University CREST-JST, [16A-5] Assembly Technology for MEMS R.Alias, A.Ibrahim, S.M.Shapee, Z.Ambak, 1. Eco-fabrication of Noble Metal Nanoparticles by 3Toyota Motor, 4Tohoku University)/Japan Metal Oxide and Home Electronics Appliances 1. A Novel Microfabricated Fibrillar Structure Z.M.Yusoff, M.R.Saad (Telekom Research & 1 2 3 1 Development)/Malaysia Y.Hayashi , M.Inoue , I.Narita , H.Takizawa , Inspired from Biological Attachment Systems 3. High Relaibility Solder for Car Electronics 2 1 2 H.Parsaiyan, F.Barazandeh, S.M.Rezaei, K.Suganuma ( Tohoku Univeristy, Osaka (Session Invite) University, 3Kyushu University)/Japan M.S.Hajhashem (Amirkabir University of M.Ueshima (Senju Metal Industry)/Japan 3. Multi-layer Thick Film Circuits with Silver Via Technology)/Iran Holes Built by All Screen-printing Process 4. Drop Impact Reliability and Thermal Cycle J.Rufiange (DKN Research)/USA 2. Preparation and Optical Properties of 30 and 2. Parylene Embedded Metal Interconnects for Resistivity of Low-Ag Content Sn-Ag-Cu (16:35) 60nm Co3O4 Nanowires Stretchable Silicon Electronics Solders (Session Invite) Y.-C.Chen (Feng-Chia University)/Taiwan T.Zoumpoulidis1, M.Bartek1, R.Dekker1,2 (1Delft T.Sasaki (Nippon Steel)/Japan (16:45) 2 University of Technology, Philips Research)/The (17:00) [16B2-5] Substrate Ⅱ 3. Molecular Modification of PCB Substrates: Netherlands 1. Reliability of Rigid to Flex Interconnection after Demonstration of HAST Survivability of Fine- (17:10) Line Patterned Structures 3. Laser Assisted Ink Jet Printing for Fine Ag Reflow [16B1-5] Electrical Solutions Ⅲ K.Kawate (Sumitomo 3M)/Japan S.Shi, T.Wei, Z.Liu, C.Rhodine, W.Kuhr Wiring 1. Novel Highly-Integrated Common-Mode (ZettaCore)/USA A.Endo, J.Akedo (National Institute of Advanced Resonant Filters Based on Multilayer Board Industrial Science and Technology)/Japan 2. Low Transmisson Loss and Excellent Heat Technologies Resistance Material for Muti-layer PCBs 4. Development of Thick Resist for Solder Bump K.Mori (JSR)/Japan 4. Development of Wafer Level CSP for Micro T.Kushta (NEC)/Japan Y.Kitai (Panasonic Electric Works)/Japan Electro Mechanical Systems 2. Bond Pass Filter Embedded System with H.Tenmei1, K.Matsumoto2, M.Nakajima2, 3. Development of High Density All Layer IVH 5. High-speed Power Supply System by Low 2 2 1 2 Probe (SwP) for High Frequency Application Characteristic Impedance Transmission Lines M.Sugita , S.Nagashima ( Hitachi, Hitachi Media K.Matsumoto, R.Saito, W.Choi, H.Tomokage PWB with Cavity Structure Electronics)/Japan K.Honjo (Panasonic Electronic Devices)/Japan Using Metamaterials (Fukuoka University)/Japan 1 1 2 (18:00) K.Hashimoto , Y.Akiyama , T.Kawaguchi , K.Tahara2, K.Otsuka1 (1Meisei University, 2Shin- 5. Low Temperature Wafer Bonding using Metal 3. Reduction of EMI from Differential Signaling Etsu Polymer)/Japan Diffusion Technique System Using Asymmetry Guard Trace 1 2 1 (18:15) H.Kurotaki , H.Shinohara , H.Kobayashi , T.Matsushima1, Y.Toyota1, K.Iokibe1, R.Koga1, 2 2 1 2 J.Mizuno , S.Shoji ( EV Group Japan, Waseda T.Watanabe2, O.Wada3 (1Okayama University, University)/Japan 2Industrial Technology Center of Okayama (18:25) Prefecture, 3Kyoto University)/Japan 4. Prediction of EM Radiation from a Printed Circuit Board Driven by Differential-Signaling Y.Kayano, H.Inoue (Akita University)/Japan 18:50 dSession; Invited Speeches Dr. Peter Brofman Mr. Takayuki Watanabe Dr. Tetsuroh Muramatsu (IBM) (Akita Elpida Memory) (Sharp) Packaging Technology Roadmap The Memory Packaging Strategy with Photovoltaic as An Energy Solution - An IBM Perspective Sophisticated 3D Technology Microelectronic packaging of semiconductor devices This paper will discuss memory package technology Ever since the industrial revolution, human is at a crossroad. Conventional scaling of integrated trend as introducing some new memory package civilization has continued to evolve through the circuitry, which has dominated this industry for over 40 solutions and next generation package. invention and spread of technology, be it means of years, has effectively ended. Innovation in materials, Currently FBGA (Fine Pitch Ball Grid Array) as transportation such as automobiles, ships, and planes, design, and packaging will be the engine that will drive commodity memory package is popular in PC/server or other developments such as communications, the continued performance/cost improvement curve application area etc. On the other hand, packaging broadcasting, and electronics products. In particular, a that our customers have come to expect. In this paper, trend for mobile phone, smart phone or digital ubiquitous society centered around developments like we will examine industry direction in packaging at a consumer application requires smaller, thinner and the Internet and mobile phones has brought the world high level, and then take a detailed look from an IBM more multi-die/package solution as MCP, PoP and SiP closer together. The energy driving all of these perspective. The latter clearly has a mid- to high-end from space or height constraint on application board. developments is solar power and the Earth's minerals. focus, with an emphasis on the server application But these are still evolved or innovated toward much As the world’s population increases and civilization's application space, although IBM does participate in smaller, much thinner and much multi-die package. growth slows down, humankind is facing the depletion both games and ASICs markets. From that perspective, As “Much smaller package technology”, this of fossil fuels and minerals. Today, it has become we observe a triple convergence of challenges: i) candidate is ideally WLCSP(Wafer level Chip Scale crucial that we strive to efficiently create electricity power / thermal management, ii) thermo-mechanical Package). But this CSP is not with big position due to from the sun, wind, water, and heat, and distribute this chip-package interaction, and exponential growth in less size compatibility and standardization issue. electricity evenly throughout the world. Key to this will electrical signal bandwidth. These challenges are made ALCSP(Advanced Laminated CSP) is introduced here be highly efficient solar cells and storage batteries, as more complex by external forces, such as the as suitable CSP for semiconductor memory without well as low-load turbines. In this lecture, we would like requirement toward Pb-free materials; use of energy wafer yield concern on behalf of WLCSP. to talk about the outlook for solar power generation, saving system on/off algorithms, and the like. As “Much thinner package technology”, this requires what must be done to spread its use, and how this can After exploring the drivers behind the triple much thinner die thickness. The thinner package and be done. We will also touch on how electronic convergence, we discuss key examples of technology die are, the more package warpage and memory packaging technology holds the key to supporting solar solutions now being developed to address each of these characteristics instability as refresh time of DRAM are power generation. key challenges, looking at both IBM as well as industry influenced. These might come from mechanical stress approaches. As noted in last year’s keynote address, it due to the difference among thermal expansion is observed that conventional corporate R&D is in characteristics of imbalanced package structure. Here is general ill-prepared to fund the scope of projects some package structure approaches to improve and required to address these challenges. Several minimize package warpage or memory characteristics development business models aimed at addressing this influence. issue will be briefly contrasted. Specifically, IBM and As “Much multi-die package technology”, innovative New York State, US have recently announced plans to new packaging technology with TSV CoC(Chip on launch a collaborative Advanced Packaging Chip technology with Through Silicon Via) will lead Development Center, in coordinate with the College of future advanced packaging on behalf of MCP(Multi Nanoscale Science & Engineering (CNSE) at Albany Chip Package) and SiP(System in Package). Here is State University. The new center will leverage multi- new ultra large capacity DRAM consist of multi party joint development alliances, similar to the highly DRAM cores and interface chip with Copper base TSV successful semiconductor R&D center already interconnection. established at CNSE. Details of the new Center’s mission and status will be discussed.

Oral Session (more than 170 technical papers) 3D/TSV* / Automotive Electronics, Challenges* / Automotive Electronics, Future Requirements* / Embedded Substrate* / High Performance Flip-Chip Packaging* / Fine MEMS* / Assembly Technology for MEMS* / MEMS/TSV Key Technologies* / Printed Electronics* / SiP/PoP Advanced Assembly* / Advanced Packaging / Electrical Solutions / Energy/Environment / Interconnections / LED / Lead Free/Environment / Material / Mechanical Solutions / MFG/Process / Optoelectronics / Reliability / RF/RFID / Substrate / Thermal Management *Core Session Poster Session (20 Posters) P-01 Reliability Evaluations of Flip Chip Packages Using the Digital Image P-11 Comparison of Erosion Rates of SUS304 and SUS316 Stainless Steel Correlation Method and the FEM Analyses by Molten Sn-3Ag-0.5Cu Solder T.Kanno1, N.Shishido1, T.Ikeda1, N.Miyazaki1, H.Tanaka2, T.Hatao2 (1Kyoto K.Sumiyoshi1, I.Shohji1, M.Miyazaki2, (1Gunma University, 2Nagano Oki University, 2Sumitomo Bakelite) Electric) P-02 Packaging Stress-induced Shifts of the Electronic and Optical P-12 Effect of Impurities of Au and Pd on Tensile Properties of Eutectic Sn- Characteristics of Thin Film Devices Used for Opto-Electronic Hybrid- Pb Solder for Aerospace Application Integrated Modules Y.Saito1, I.Shohji1, N.Nemoto2, T.Nakagawa3, N.Ebihara4, F.Iwase5 (1Gunma H.Kishi, K.Suzuki, H.Miura (Tohoku University) University, 2Japan Aerospace Exploration Agency, 3Nippon Avionics, 4NEC P-03 Thermal History Dependence of Mechanical Properties of Electroplated TOSHIBA Space Systems, 5HIREC) Copper Thin Films Used for Thin Film Interconnection P-13 Development of Joining Technology of Al Alloy Plate and Cu Alloy Pipe N.Murata, K.Suzuki, K. Tamakawa, H.Miura (Tohoku University) for Cooling System of Power Module P-04 Numerical Analysis of Transport Phenomena in High Aspect Cavity for I.Oshiro1, I.Shohji1, H.Nara2, N.Otomo2, M.Uenishi2 (1Gunma University, Bumps Formation 2ATAGO MFG) Y.Koyama, Y.Suzuki, N.Okamoto, T.Saito, K.Kondo (Osaka Prefecture P-14 Fabrication of Multiplex Electrodes with Stacked Structure for Nerval University) Interface P-05 The Effect of the New Levelers for Cu Via-filling M.Kato1, Y.Ukita1, Y.Utsumi1, E.Blasius2, K.Masubuchi3 (1University of H.Kuri, N.Okamoto, T.Saito, K.Kondo, M.Bunya, M.Takeuchi (Osaka Hyogo, 2University Karlsruhe, 3The University of Tokyo) Prefecture University) P-15 Modeling of Self-face-alignment Process Using Contact Potential P-06 Fabrication of Copper Circuit Patterns on Glass Substrate Using Difference Photochemical Reduction Process R.Sato, T.Tanemura, G.Lopez, M.Serry, K.Sugano, T.Tsuchiya, O.Tabata R.Nakamichi, K.Akamatsu, H.Nawafune (Konan University) (Kyoto University) P-07 Formation of ULSI Cu Minute Wiring Through Microcontact Printing P-16 An Architecture of Dynamically Reconfigurable Arithmetic Circuit Using Silicone H.Shimada, Y.Hayakawa, A.Kanasugi (Tokyo Denki University) K.Nakajima, K.Akamatsu, H.Nawafune (Konan University) P-17 An Implementation and Verification of Dynamically Reconfigurable P-08 A Rotating Ring Disk Electrode (RRDE) Study of Cuprous Thiolate Systolic Array Accelerant Produced by Copper Dissolution Y.Hayakawa, T.Ishimura, A.Kanasugi (Tokyo Denki University) S.Hattori, D.P.Barkey, K.Kondo, N.Okamoto, T.Saito (Osaka Prefecture P-18 Laser-doppler Velocity Measurements Using An Ultra-compact and University) Thin Microsensor P-09 Improvement of Adhesion Strength between Under Fill Resin and S.Nakamura (The University of Tokyo) Polyimide Substrate Through Conducting Surface Treatment on P-19 MEMS Type Micro Robot with Artificial Intelligence System Substrate Resin H.Suematsu, K.Kobayashi, R.Ishii, A.Matsuda, Y.Sekine, F.Uchikoba (Nihon O.Kato1, Y.Kimura1, M.Chino2, S.Izawa2 (1Kogakuin University, 2Misuzu University) Industries) P-20 Characterization and Properties of Nanometric-sized SnO2/CNT Com- P-10 Filler Motion Dynamics in Resin for Flip Chip Micro Interconnects by posited Materials for Lithium-Battery Anodes Self-organization Assembly W.-D.Yang1, H.-Y.Fang1, M.-S.Wu1, H.-M.Tsai2, C.-S.Hsieh3 (1National Kaohsiung University of K.Ohta, K.Fujimoto, M.Matsushima, K.Yasuda (Osaka University) Applied Sciences, Kaohsiung, 2Chung-Shan Institute of Science & Technology, 3Fooyin University) dPlant Tour (Planned on April 17th) Tour-A RITSUMEIKAN University Biwako-Kusatsu campus Kusatsu City, Shiga Pref. (Close to Minami-Kusatsu Station on JR BIWAKO line) MEMS Laboratory & Synchrotron Radiation Equipment Tour

Tour-B TORAY Engineering Co., Ltd. Ohtsu City, Shiga Pref. (Close to Seta Station on JR BIWAKO line) Assembly Equipment Manufacturing Plant Tour

Tour-C SONY Mobile Display Corporation Yasu City, Shiga Pref. (Close to Yasu Station on JR BIWAKO line) Flat Panel Display Production Plant Tour

Tour-D KYOCERA SLC Technologies Corporation Yasu City, Shiga Pref. (Close to Yasu Station on JR BIWAKO line) High Density Circuit Board & Carrier Production Plant Tour

Tour-E OMRON Corporation ELECTRONIC COMPONENTS COMPANY MICRO DEVICE DIVISION Yasu City, Shiga Pref. (Close to Yasu Station on JR BIWAKO line) MEMS&CMOS Production Plant Tour

Please accept below to attend the tour

[1] Attendee Qualification 1. Must not be Competitor 2. Register with ICEP2009 by March13th, 2009 and Apply to the tour [2] No additional fee is required to attend the tour. [3] You can attend one tour above. At your application, please input your desired order to attend. 30-50 participant will be accepted for each tour in order of registration receipt. [4] Registered information will be sent to visiting Company/University. dRegistration Fees; (Advance by March 31, 2009) Member (JIEP, IEEE)...... 40 000yen [47 000yen] (Including Reception and Proceedings) Non Member ...... 50 000yen [57 000yen] (Including Reception and Proceedings) Student ...... 5 000yen [ 5 000yen] (Including Proceedings) Welcome Reception Only ...... 8 000yen [ ] At door dCommittee General Chair Shigeru Hiura (Toshiba) Finance Committee Hideyuki Nishida (NEP Tech. S&S) Hiroshi Hozoji (Hitachi) Kaoru Hashimoto (Meisei University) Vice General Chair Kinya Ichikawa (Intel) Publication Yasumitsu Orii (IBM Japan) Toru Ikeda (Kyoto University) Masashi Ohshima (Kogyo Tyousakai) Masato Nakamura (Hitachi) Yasushi Kodama (Kyocera SLC Technoligies) Advertising Chair Advisory You Kondoh (Olympus) Katsuko Hirata (SHN Human) Hironori Asai (Toshiba) Kazuhiko Kurata (NEC) Advertising Vice Chair Sei-ichi Denda (Nagano Prefectural Institute of Inoue Masahiro (Osaka University) Satoshi Yanaura (Mitsubishi Electric) Technology) Masaaki Oda (ULVAC) OPC Chair Yoshitaka Fukuoka (WEISTI) Hideo Ohkuma (HTO) Masato Nakamura (Hitachi) Kaoru Hashimoto (Meisei University) Kazuya Okamoto (Osaka University) SOC Chair/OPC Vice Chair Fumio Miyashiro (Yokohama Jisso Consortium) Atsushi Okuno (Sanyu Rec) Miki Mori (Toshiba) Hideyuki Oh-hashi (Mitsubishi Electric) Tetsuya Onishi (Grand Joint Technology Ltd.) OPC Vice Chair Kanji Otsuka (Meisei University) Hitoshi Sakamoto (NEC) Kimihiro Yamanaka (Kyocera SLC Technologies) Yuzo Shimada (NEC) Osamu Shimada (Dai Nippon Printing) OPC Member Tadatomo Suga (The University of Tokyo) Tsuyoshi Shiota (Mitsui Chemicals) Hiroaki Date (Fujitsu Laboratories) Haruo Tabata Tsukasa Shiraishi (Panasonic) Toshio Enami (Sekisui Chemical) Shinichi Wakabayashi (Shinko Electric Industries) Toshio Sudo (Shibaura Institute of Technology) Kenichiro Fujii (NEC) Itsuo Watanabe (Hitachi Chemical) Susumu Sugiyama (Ritsumeikan University) Yoshikazu Hirayama (Toray Engineering) Kishio Yokouchi (Fujitsu Interconnect Technologies) Masato Sumikawa (Sharp) Naotoshi Ikushima (Musashi Engineering) TPC Chair Hajime Tomokage (Fukuoka University) Mitsuya Ishida (IBM Japan) Yasumitsu Orii (IBM Japan) Fumio Uchikoba (Nihon University) Yuki Kawamura (KOA) TPC Vice Chair Hirotaka Ueda (Semi Consult) Yangsoo Lee (Sekisui Chemical) Yasuhiro Ando (Fujikura) Dongdong Wang (Ibiden USA) Koichiro Nagai (Sanyu Rec) Nobuaki Hashimoto (Seiko Epson) Hiroshi Yamada (Toshiba) Yoshio Nogami (Toray Engineering) Shoji Uegaki (ASE Marketing & Service Japan) Shintaro Yamamichi (NEC) Tatsuo Ogawa (Panasonic) TPC Member Kiyokazu Yasuda (Osaka University) Yoshio Tezuka (Nagano Prefectural Institute of Masahiro Aoyagi (National Institute of Advanced Kazuaki Yazawa (SONY) Technology) Industrial Science and Technology) Shinya Yoshida (Tokyo Institute Polytechnic Akira Yamauchi (Bondtech) Tomoyuki Abe (Fujitsu Laboratories) University) Masazumi Amagai (Texas Instruments Japan)

Secretariat of ICEP 2009 JIEP, 3-12-2 Nishiogi-kita, Suginami-ku Tokyo 167-0042, Japan http://www.jiep.or.jp/icep/