Review and Comparison of Clock Jitter Noise Reduction Techniques for Lowpass Continuous-Time Delta-Sigma Modulators

Journal of Low Power Electronics and Applications

Article Review and Comparison of Clock Jitter Noise Reduction Techniques for Lowpass Continuous-Time Delta-Sigma Modulators

Hairong Chang 1,2,† and Hua Tang 2,*

1 Qualcomm Inc., San Diego, CA 92121, USA; [email protected] 2 Department of Electrical Engineering, University of Minnesota Duluth, Duluth, MN 55812, USA * Correspondence: [email protected]; Tel.: +1-218-726-7095 † was with Department of Electrical Engineering, University of Minnesota Duluth.

Received: 10 July 2017; Accepted: 23 August 2017; Published: 6 September 2017

Abstract: It is well known that continuous-time Delta-Sigma modulators are very sensitive to clock jitter effects. In literature, a number of techniques have been proposed to cope with them. In this brief, we present a detailed review and comparison of the reported techniques. While the effectiveness to reduce clock jitter effects may be of most importance in this comparison, we also consider other performance metrics such as circuit complexity and overhead to implement the technique, power consumption overhead of technique, synthesis complexity incurred in system-level design, extensibility of the technique from single-bit to multi-bit operation, and robustness to process variation. When clock jitter is relatively large, the fixed-width pulse feedback technique is most effective to reduce clock jitter effects among all techniques at high sampling frequency, while switched-capacitor-resistor and switched-shaped current techniques have best performance at medium frequency or below.

Keywords: Delta-Sigma modulators; continuous-time; lowpass; clock jitter; clock jitter noise reduction

1. Introduction Oversampling Continuous-time Delta-Sigma Modulators (CTDSM) have been widely used in ADC (Analog-to-Digital Converters) and DAC (Digital-to-Analog Converters) due to their better speed–accuracy tradeoff [1]. However, CTDSM have a few drawbacks, such as performance degradation due to excess loop delay [2], time-constant variation [3,4] and clock jitter effects [5,6]. Excess loop delay may be solved by either return-to-zero DAC feedback techniques [2], or by intentionally delaying the modulator output and adding compensation paths around the modulator loop ﬁlter [2,4]. Process-induced time-constant variation may be minimized by on-chip tuning techniques [3]. Clock jitter has been plaguing CTDSM and many techniques have been proposed in literature [7]. In this paper, we focus on the issue of clock jitter for lowpass CTDSM. We follow the literature of clock jitter in the context of CTDSM and focus on jitter noise reduction techniques in case of Independent Clock Jitter (ICJ) [6]. Suppose the ideal sampling period of a clock is TS. Without jitter, the sampling instants occur at multiples of TS, that is nTS. Due to jitter, the sampling instants become:

tn = nTS + an, n = 0, 1, 2, . . . , N (1) where an is jitter of rising/falling edge of the clock and is typically modeled as i.i.d (independent and identically distributed) Gaussian noise [6]. Its standard deviation is denoted as σCLKJ in this paper. Clock jitter effects in CTDSM have been well studied in literature [6,8–15]. In CTDSM, clock jitter affects the ideal modulator operation in three ways, which is illustrated in Figure1, considering

J. Low Power Electron. Appl. 2017, 7, 22; doi:10.3390/jlpea7030022 www.mdpi.com/journal/jlpea J. J.Low Low Power Power Electron. Electron. Appl. Appl. 20172017, 7,,7 22, 22 2 2of of 11 11 general case of a return-to-zero feedback. First, clock jitter introduces sampling errors at the quantizer the general case of a return-to-zero feedback. First, clock jitter introduces sampling errors at the input due to non-uniform sampling. Second, with respect to the ideal sampling instants, the DAC quantizer input due to non-uniform sampling. Second, with respect to the ideal sampling instants, feedback has a variable delay caused by clock jitter and this is termed as pulse-delay jitter (or pulse- the DAC feedback has a variable delay caused by clock jitter and this is termed as pulse-delay jitter position jitter [12]). Finally, the amount of feedback charge (by the active pulse) is not constant with (or pulse-position jitter [12]). Finally, the amount of feedback charge (by the active pulse) is not constant respect to either the ideal or non-ideal sampling clock cycles, and this is named as pulse-width jitter. with respect to either the ideal or non-ideal sampling clock cycles, and this is named as pulse-width It has been studied that pulse-position jitter incurred at the quantizer input may be regarded jitter. It has been studied that pulse-position jitter incurred at the quantizer input may be regarded insignificant due to noise shaping and high loop gain of the modulator [9,10]. Pulse-delay jitter does insignificant due to noise shaping and high loop gain of the modulator [9,10]. Pulse-delay jitter does not affect the amount of feedback charge by the active pulse, but rather only changes the frequency not affect the amount of feedback charge by the active pulse, but rather only changes the frequency response of the modulator loop filter, therefore is not significant either [10,12]. However, pulse-width response of the modulator loop filter, therefore is not significant either [10,12]. However, pulse-width jitter directly changes the amount of feedback charge from the active pulse, and the error charge is jitter directly changes the amount of feedback charge from the active pulse, and the error charge is not noise-shaped and directly fed back to the input, which seriously degrades the performance of not noise-shaped and directly fed back to the input, which seriously degrades the performance of CTDSM [6,8,9]. Therefore, reducing or eliminating the effects of pulse-width jitter is most important CTDSM [6,8,9]. Therefore, reducing or eliminating the effects of pulse-width jitter is most important to to improve the performance of CTDSM in the presence of clock jitter. improve the performance of CTDSM in the presence of clock jitter. In literature, a number of methods have been proposed to reduce clock jitter effects in CTDSM In literature, a number of methods have been proposed to reduce clock jitter effects in CTDSM [7]. [7]. While some are effective, a systematic comparison is missing from the literature. In this brief, we While some are effective, a systematic comparison is missing from the literature. In this brief, we present a detailed review and comparison of the reported techniques in Section 2. Conclusions are present a detailed review and comparison of the reported techniques in Section2. Conclusions are drawn in Section 3. drawn in Section3.

FigureFigure 1. 1. IllustrationIllustration ofof clock clock jitter jitter effects effects in lowpass in lowpass Continuous-time Continuous-time Delta-Sigma Delta-Sigma Modulators Modulators (CTDSM). (CTDSM). 2. Review and Comparison of Previous Work 2. Review and Comparison of Previous Work In this Section, we ﬁrst present a detailed review of major techniques reported in literature to cope withIn clock this Section, jitter effects. we first Then, present we give a detailed a quantitative reviewcomparison of major techniques of different reported techniques in literature in terms to of copeeffectiveness with clock to jitter reduce effects. clock Then, jitter effects.we give In a particular,quantitative we comparison focus on three of different most effective techniques techniques in terms and ofcompare effectiveness them to under reduce practical clock jitter noise. effects. Finally, In anpa overallrticular, qualitative we focus on comparison three most of effective different techniques techniques andconsidering compare sixthem major under metrics practical are given. noise. Finally, an overall qualitative comparison of different techniques considering six major metrics are given. 2.1. Review of Previous Work 2.1. ReviewIn literature, of Previous a number Work of techniques have been proposed to reduce clock jitter effects in CTDSM withIn varying literature, effectiveness a number of [ 7techniques]. The basic have idea been behind proposed all methods to reduce is clock to shape jitter theeffects DAC in CTDSM feedback withwaveform varying so effectiveness that an insigniﬁcant [7]. The amount basic idea feedback behind charge all methods is transferred is to atshape times the of clockDAC transitions,feedback waveformwhich helps so that maintain an insignificant a constant amount amount feedback of feedback charge charge is transferred in each at clock times cycle,of clock thus transitions, reducing whichpulse-width helps maintain jitter. a constant amount of feedback charge in each clock cycle, thus reducing pulse- width Ajitter. simple but not very effective technique is to use NRZ (Non-Return-to-Zero) SI (Switched-Current) DACA feedback,simple but whose not very waveform effective is showntechnique in Figure is to 2use[ 7 ].NRZ In this (Non-Return-to-Zero) case, clock jitter only SI matters (Switched- when Current)the output DAC changes feedback, sign assumingwhose waveform a single-bit is quantizer.shown in Or,Figure in other 2 [7]. words, In this clock case, jitter clock only jitter affects only one matters when the output changes sign assuming a single-bit quantizer. Or, in other words, clock jitter

J. Low Power Electron. Appl. 2017, 7, 22 3 of 11 J. Low Power Electron. Appl. 2017, 7, 22 3 of 11 onlyrising affects or falling one edge rising [6]. or Furthermore, falling edge it may[6]. beFurthermore, helpful to use it multi-bitmay be NRZhelpful feedback, to use becausemulti-bit the NRZ step feedback,height of abecause multi-bit the DAC step is smallerheight of and a clockmulti-bit jitter DAC induced is smaller noise is and proportional clock jitter to that.induced For example,noise is proportionalwith a NRZ DACto that. of For 5-bit example, resolution, with 22.5 a NRZ dB SNR DAC improvement of 5-bit resolution, is achieved 22.5 dB compared SNR improvement to a RZ DAC is achievedfeedback, compared as reported to in a [ 4RZ]. However, DAC feedback, the use ofas NRZ reported DAC in feedback [4]. However, has a price. the First,use of the NRZ jitter DAC noise feedbackreduction has is limited a price. by First, the number the jitter of bits,noise since reduct a DACion is with limited a large by numberthe number of bits of increases bits, since the apower DAC withconsumption a large ofnumber the modulator of bits increases and introduces the powe linearityr consumption problems which of the has modulator to be corrected and byintroduces complex linearityDEM (Dynamic problems Element which Matching) has to be or corrected calibration by circuits complex [3,4]. DEM Besides, (Dynamic NRZ DAC Element suffers Matching) from memory or calibrationeffects, signal-dependent circuits [3,4]. Besides, quantizer NRZ jitter DAC and suffer loop delay,s from though memory they effects, can be signal-dependent reduced by RZ feedback quantizer or jitteradditional and loop circuits delay, [4]. though they can be reduced by RZ feedback or additional circuits [4].

FigureFigure 2.2. GraphicalGraphical illustration illustration of Digital-to-Analogof Digital-to-Ana Converterlog Converter (DAC) (DAC) feedback feedback waveforms waveforms for different for differenttechniques techniques [7]. [7].

FIRFIR (Finite ImpulseImpulse Response)Response) DACDAC feedback feedback is is proposed proposed in in [16 [16–20,21]–21] to reduce to reduce clock jitterclock effects. jitter effects.The idea The is idea to use is to a single-bituse a single-bit quantizer quantizer with with DAC DAC response response widened widened over overn clock n clock cycles cycles so so as as to toaverage average clock clock jitter jitter effects effects over overn nclock clock periods. periods. The The FIR FIR DACDAC hashas comparablecomparable jitter noise reduction performance as as the multi-bit NRZ DAC, but is linear due to thethe single-bitsingle-bit quantizer.quantizer. Using this technique,technique, jitter jitter noise noise reduction reduction is is reported reported to to be be up up to to 18 18 dB dB [16]. [16]. However, However, the the jitter jitter noise noise reduction reduction performance is is signal-amplitude signal-amplitude dependent dependent and and for for higher higher amplitude amplitude inputs inputs the the results results are are not not as as goodgood as as those for smaller amplitude inputs [16,17]. [16,17]. Besides, Besides, it it also also increases increases the the loop loop delay delay of of the modulatormodulator and may may lead lead to to stability stability problems problems [7], [7], which which renders renders synthesis synthesis of of the the modulator modulator with with FIR FIR DACDAC feedback feedback difficult. difﬁcult. Finally, Finally, extending extending FIR FIR feedba feedbackck to to multi-bit multi-bit operation operation is is not not readily readily done done [7]. [7]. AnotherAnother reported reported technique technique to to reduce reduce clock clock jitte jitterr effects effects explores explores the the use of sin-shaped DAC feedbackfeedback [22,23] [22,23] (an (an example example of of its waveform is also shown in Figure2 2).). InIn thisthis technique,technique, clockclock transitionstransitions take take place place when when the the sin-shaped sin-shaped feedback feedback is is at at its its maximum maximum slope slope and and hence hence results results in in a a smallsmall charge error.error. To To further further reduce reduce clock clock jitter jitter noise, noise, it may it may be more be more useful useful to use to multiple use multiple sin-shaped sin- shapedpulses perpulses sampling per sampling period period [22]. The [22]. maximum The maximum jitter noisejitter noise reduction reduction is 17dB, is 17dB, as reported as reported in [22 in]. [22].But forBut sin-shaped for sin-shaped DAC DAC feedback, feedback, the circuitthe circuit realization realization based based on phase-locked on phase-locked loop loop is complex is complex and anddifﬁcult difficult and itand may it may dramatically dramatically increase increase power power consumption. consumption. In addition, In addition, it is sensitive it is sensitive to loop to delay,loop delay,locking locking error and error phase/amplitude and phase/amplitude noise of thenoise feedback of the pulsefeedback itself pulse [22,23 ].itself Besides, [22,23]. extensibility Besides, extensibilityof the sin-shaped of the DAC sin-shaped feedback DAC to multi-bit feedback operation to multi-bit is poor operation [7]. Synthesis is poor of [7]. the Synthesis modulator of with the modulatorsin-shaped with feedback sin-shaped is also feedback more involved is also than more NRZ/RZ involved feedback. than NRZ/RZ feedback. A more effective technique is to employ SCR (Switched-Capacitor-Resistor) feedback [24], adapted from the switched capacitor feedback in discrete-time modulators. Instead of having the

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J. LowA Power more Electron. effective Appl. 2017 technique, 7, 22 is to employ SCR (Switched-Capacitor-Resistor) feedback4 [of24 11], adapted from the switched capacitor feedback in discrete-time modulators. Instead of having the traditional rectangular-shaped SI DAC feedback, which gives a constant current during a clock cycle, traditional rectangular-shaped SI DAC feedback, which gives a constant current during a clock cycle, an exponentially decreasing feedback current is generated. As illustrated in Figure 2, the SCR an exponentially decreasing feedback current is generated. As illustrated in Figure2, the SCR feedback feedback has a waveform that can transfer almost all charges to the integrators before clock has a waveform that can transfer almost all charges to the integrators before clock transitions and transitions and therefore clock jitter causes little charge error. This technique is relatively simple to therefore clock jitter causes little charge error. This technique is relatively simple to implement and implement and quite effective to reduce clock jitter effects. An example circuit implementation is quite effective to reduce clock jitter effects. An example circuit implementation is shown in Figure3a shown in Figure 3a and jitter noise reduction is reported up to 30 dB in some example and jitter noise reduction is reported up to 30 dB in some example implementations [7,24]. In SCR implementations [7,24]. In SCR feedback, the capacitor is first charged during phase and then feedback, the capacitor is ﬁrst charged during phase S and then switched to the resistor during phase switched to the resistor during phase . A similar technique1 to generate a quadratically decreasing S . A similar technique to generate a quadratically decreasing feedback current is reported in [25]. But, feedback2 current is reported in [25]. But, several drawbacks are associated with SCR feedback. The several drawbacks are associated with SCR feedback. The main drawback is that SCR feedback results main drawback is that SCR feedback results in integrator response having high-demand for OpAmp in integrator response having high-demand for OpAmp slew-rate and gain-bandwidth product due to slew-rate and gain-bandwidth product due to the big spike of the feedback current, which greatly the big spike of the feedback current, which greatly increases power consumption of the OpAmp and increases power consumption of the OpAmp and hence that of the modulator [7,24]. Also, recently it hence that of the modulator [7,24]. Also, recently it has been shown that SCR feedback may severely has been shown that SCR feedback may severely degrade the alias rejection of the CTDSM [26–28]. degrade the alias rejection of the CTDSM [26–28]. Besides, synthesis of a modulator employing SCR Besides, synthesis of a modulator employing SCR feedback is more complicated than a modulator feedback is more complicated than a modulator using SI feedback [24]. Finally, SCR feedback may using SI feedback [24]. Finally, SCR feedback may not be well extended to multi-bit operation due to not be well extended to multi-bit operation due to matching and linearization difﬁculties of reference matching and linearization difficulties of reference voltages or capacitors [7]. voltages or capacitors [7].

Figure 3. Simpliﬁed circuit schematic to implement Switched-Capacitor-Resistor (SCR) feedback (a) Figure 3. Simplified circuit schematic to implement Switched-Capacitor-Resistor (SCR) feedback (a) and Switched-Shaped-Current (SSI) feedback (b). and Switched-Shaped-Current (SSI) feedback (b).

ToTo solve solve some some of ofthe the problems problems with withSCR feedback SCR feedback while maintaining while maintaining its effectiveness, its effectiveness, Reference Reference[29] proposes [29] proposes a SSI (Switched-Shaped-Current) a SSI (Switched-Shaped-Current) DAC DAC feedback feedback technique technique for for clock clock jitter jitter noisenoise reduction.reduction. InsteadInstead ofof generatinggenerating anan exponentiallyexponentially decreasingdecreasing feedbackfeedback current overover thethe wholewhole clockclock periodperiod asas inin SCRSCR feedback,feedback, SSISSI feedbackfeedback generatesgenerates aa slowlyslowly linearlylinearly decreasingdecreasing feedbackfeedback currentcurrent inin mostmost ofof thethe clockclock period, period, and and then then fast fast decreasing decreasing feedback feedback current current in in the the rest rest of theof the clock clock period period (as (as its waveformits waveform illustrated illustrated in Figurein Figure2), 2), so thatso that almost almost all all the the charge charge is is fed fed back back before before clock clock transitions. transitions. AnAn exampleexample circuitcircuit implementationimplementation isis shownshown inin FigureFigure3 3bb [ [29].29]. TheThe capacitorcapacitor isis ﬁrstfirst chargedcharged duringduring phase S1. During phase S2, M1, M3, and M5 are in the saturation region and the capacitor linearly phase . During phase , M1, M3, and M5 are in the saturation region and the capacitor linearly dischargesdischarges until M3 starts starts to to go go into into the the triode triode region. region. Then, Then, the the capacitor capacitor continues continues to discharge to discharge but butmore more slowly slowly until until M3 M3enters enters deep deep triode triode region region (drain-source (drain-source voltage voltage almost almost 0). By 0). this By thismoment, moment, the thecurrent current has hasbeen been slowly slowly decreasing decreasing.. Subsequently, Subsequently, the capacitor the capacitor continues continues to discharge to discharge and M5 and goes M5 goesto weak to weak inversion, inversion, causing causing current current to drop to drop off off dramatically. dramatically. Meanwhile, Meanwhile, M1 M1 should should stay stay in thethe saturationsaturation region.region. AtAt last,last, M1M1 goesgoes toto the triode regionregion while M5 turns off, and the current approaches toto zerozero exponentiallyexponentially inin aa shortshort timetime duration,duration, in whichwhich clock transitions are expected to occur [29]. [29]. TheThe performanceperformance ofof thethe SSISSI feedbackfeedback isis comparablecomparable to SCR feedback in term of jitter noise reduction. ButBut compared to to SCR SCR feedback, feedback, it itrelaxes relaxes the the dema demandnd for for OpAmp OpAmp slew-rate slew-rate and andgain gain bandwidth bandwidth and, and,therefore, therefore, should should not notcause cause excessive excessive power power co consumptionnsumption of of the the OpAmp. OpAmp. However, However, the circuitcircuit implementationimplementation forfor SSISSI maymay bebe difﬁcultdifficult toto achieveachieve andand needsneeds extensiveextensive sizingsizing andand tuning.tuning. Besides,Besides, the technique requires precise control of transistor operation in the saturation region, triode region, and cutoff region, which may not scale well with transitions of transistor technologies in the nano- meter regime. Process variation effects may be detrimental, especially if the circuit is aggressively

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J.the Low technique Power Electron. requires Appl. 2017 precise, 7, 22 control of transistor operation in the saturation region, triode region,5 of and 11 cutoff region, which may not scale well with transitions of transistor technologies in the nano-meter designedregime. Process to give variation a short effects time mayduration be detrimental, for clock especiallytransitions. if theFurther, circuit like is aggressively the SCR feedback, designed synthesizingto give a short modulators time duration with forSSI clock feedback transitions. is also Further,complicated like thedue SCR to feedback,the irregular synthesizing feedback waveformmodulators shape. with SSIFinally, feedback regarding is also extension complicated of th duee SSI to feedback the irregular to multi-bit feedback operation, waveform there shape. are twoFinally, ways regarding to either extension design multiple of theSSI current feedback sources to multi-bit or multiple operation, capacitors. there However, are two waysin either to either case, thedesign settings multiple of current current sources sources or or capacitors multiple capacitors.are difficult However, due to the in irregular either case, feedback the settings waveform of current and difficult-to-controlsources or capacitors transistor are difficult operations due to in the differe irregularnt regions. feedback Therefore, waveform extending and difficult-to-control SSI feedback to multi-bittransistor operation operations is indifficult. different regions. Therefore, extending SSI feedback to multi-bit operation is difficult.While the above discussed SCR and SSI techniques are quite effective to reduce clock jitter effects by minimizingWhile the above the jitter-induced discussed SCR charge and SSI techniquesduring clock are transitions, quite effective they to reducestill do clock not jitter have effects the convenienceby minimizing of the the jitter-induced traditional SI charge feedback during with clock a rectangular-shaped transitions, they still waveform do not have from the conveniencedesign and implementationof the traditional point SI feedback of view. with However, a rectangular-shaped the traditional waveform SI feedback from design (with andeither implementation RZ or NRZ pointwaveforms) of view. is However,not very effective the traditional to reduce SI feedbackclock jitter (with effects. either To RZaddress or NRZ this waveforms) issue while ishoping not very to retaineffective its toadvantages, reduce clock one jitter idea effects. is to maintain To address the thiswidth issue of whilethe active hoping feedback to retain pulse its advantages,as fixed as possibleone idea [15], is to maintainhence to thereduce width the of dominant the active pulse-width feedback pulse jitter. as Wh fixedile asthis possible is well [15 understood], hence to theoreticallyreduce the dominant in literature, pulse-width it is recent jitter. that Whilecircuits this are is proposed well understood to generate theoretically a FWP (Fixed-Width in literature, Pulse) it is forrecent active that feedback circuits are[30,31]. proposed One recently to generate proposed a FWP method (Fixed-Width to use FWP Pulse) RZ for feedback active feedback is illustrated [30,31 by]. theOne gate-level recently proposedschematic method in Figure to 4 use (simplified FWP RZ feedbackfrom the original is illustrated circuit by in the [30,31]). gate-level Assuming schematic in isFigure the original4 (simplified jittered from clock the with original ICJ at circuit rising/falling in [ 30,31 edges,]). Assuming the resultingCLKJ issignal the original jittered has a pulse clock withof fixed-width ICJ at rising/falling set by edges, the first the resultinginverter signalchain.CLKJ Finally,ND has a pulse is ofAND fixed-width with bothtd2 Qset and by theQ’ (outputsfirst inverter from chain. a single-bit Finally, quantizerCLKJND ofis ANDa CTDSM) with bothto generate Q and Q’two (outputs RZ logic from signals, a single-bit which retain quantizer the fixed-widthof a CTDSM) pulse to generate of . twoNote RZ that logic the signals,fixed pulse which width retain the would fixed-width provide pulse a constant of td2 .amount Note that of feedbackthe fixed pulsecharge, width hencetd 2eliminatingwould provide pulse-width a constant jitter amount otherwise of feedback caused charge, by hence. The eliminating superior pulse-widtheffectiveness jitterof the otherwise FWP method caused byhasCLKJ been. Theshown superior in [15,30,31] effectiveness with ofup the to FWP33 dB method of jitter has noise been reductionshown in [in15 ,example30,31] with designs. up to 33However, dB of jitter there noise are reduction some limitations in example of the designs. FWP feedback. However, First, there the are FWPsome feedback limitations may of thenot FWP work feedback. well in case First, of thevery FWP large feedback clock jitter, may for not instance work well in case= 1.0 of very large(i.e., −1 standardclock jitter, deviation for instance of clockσCLKJ jitter= 1.0 ise 10%TS of(i.e., the standard nominal deviation clock period), of clock beca jitteruse isthe 10% fixed-width of the nominal pulse mayclock not period), be obtained because from the the fixed-width digital gates. pulse Fortunatel may not bey, practical obtained clock from jitter the digital is usually gates. not Fortunately, that large. practicalThe other clock limitation jitter is of usually the FWP not feedback that large. is The that other the circuit limitation in Figure of the FWP4 may feedback only give is thata pulse the circuitwidth in Figure up to4 may40% onlyof the give nominal a pulse clock width period.td2 up To to 40%improve of the the nominal utilization clock of period. the clock To improve period, thean alternativeutilization ofcircuit the clock is to period, generate an alternative a longer circuitpulse iswidth to generate (e.g., 70% a longer of the pulse clock width period) (e.g., 70%by using of the additionalclock period) digital by using D-flip-flops additional [32]. digital Besides, D-flip-flops FWP feedback [32]. Besides, is more FWP suitable feedback to is morerelatively suitable high- to frequencyrelatively high-frequencyCTDSM, as the CTDSM, delay is asachieved the delay by is inve achievedrter chains by inverter and very chains long and inverter very long chains inverter for a relativelychains for large a relatively clock cycle large clockmay not cycle bemay desired not bein desiredpractical in circuit practical implementations circuit implementations due to area due and to powerarea and consumption power consumption considerations. considerations.

Figure 4. SimplifiedSimpliﬁed circuit circuit schematic to implement implement the Fixed-Width Fixed-Width Pulse (FWP) feedback technique.

2.2. Comparison of the Techniques in Terms of Effectiveness In Section 2.1, we reviewed in detail previous work to reduce clock jitter effects in literature. In the following, we make a quantitative comparison of the techniques in terms of effectiveness of jitter

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2.2. Comparison of the Techniques in Terms of Effectiveness In Section 2.1, we reviewed in detail previous work to reduce clock jitter effects in literature. In the J.following, Low Power Electron. we make Appl. a 2017 quantitative, 7, 22 comparison of the techniques in terms of effectiveness of jitter6 noise of 11 reduction. In next Section 2.3, we make an overall qualitative comparison considering six performance noise reduction. In next Section 2.3, we make an overall qualitative comparison considering six metrics and summarizing their pros and cons. performance metrics and summarizing their pros and cons. In order to have a quantitative comparison, we performed behavioral simulation on a 4th-order In order to have a quantitative comparison, we performed behavioral simulation on a 4th-order Delta-Sigma modulator shown in Figure5 in MATLAB/SIMULINK [ 33], and the oversampling ratio Delta-Sigma modulator shown in Figure 5 in MATLAB/SIMULINK [33], and the oversampling ratio was assumed to be 32 to achieve at least 80 dB of SNR with single-bit quantization [30]. Ideally, the was assumed to be 32 to achieve at least 80 dB of SNR with single-bit quantization [30]. Ideally, the modulator without clock jitter effects would achieve a SNR of 82 dB with SI NRZ feedback. When modulator without clock jitter effects would achieve a SNR of 82 dB with SI NRZ feedback. When clock jitter of σ = 1.0e−2T (here σ is made relatively large to have jitter noise dominate so clock jitter of CLKJ =1.0 S (here CLKJ is made relatively large to have jitter noise dominate so that one could focus on its effect) was considered, the resulting SNRs for each technique is shown that one could focus on its effect) was considered, the resulting SNRs for each technique is shown in in the second row of Table1. It can be recognized that SCR, SSI, and FWP techniques stand out in the second row of Table 1. It can be recognized that SCR, SSI, and FWP techniques stand out in terms terms of the effectiveness to reduce clock jitter noise, as they almost achieved the same SNR as the of the effectiveness to reduce clock jitter noise, as they almost achieved the same SNR as the ideal ideal modulator without clock jitter effects. These results were as expected from the discussions in modulator without clock jitter effects. These results were as expected from the discussions in Section Section 2.1 and from inspecting their respective feedback waveforms in Figure2. 2.1 and from inspecting their respective feedback waveforms in Figure 2. Table 1. Comparison of different techniques for clock jitter noise reduction for the same modulator Table 1. Comparison of different techniques for clock jitter noise reduction for the same modulator design in Figure5 with single-bit quantization at normalized clock jitter of σ /T = 1.0e−2. CLKJ S design in Figure 5 with single-bit quantization at normalized clock jitter of / =1.0 . FWP SNRSNR Single-Bit Single-Bit SI NRZ/RZ SI NRZ/RZ [6] [6]FIR FIR [16 [16,,17]17] SIN SIN [22 [22,2323]]SCR SCR[24] [24] SSI SSI [29] [29 ] FWP [30,31] [30,31] Without noise 47 dB 64 dB 65 dB 78 dB 78 dB 80 dB Without noise 47 dB 64 dB 65 dB 78 dB 78 dB 80 dB = 128MHz - - - 66 dB 64 dB 73 dB With fs = 128 MHz - - - 66 dB 64 dB 73 dB With noise * = 12.8MHz - - - 68 dB 68 dB n/a noise * fs = 12.8 MHz - - - 68 dB 68 dB n/a = 1.28MHz - - - 74 dB 76 dB n/a fs = 1.28 MHz - - - 74 dB 76 dB n/a | | * assuming normalized power noise of / = 1.0 − and3 noise bandwidth of = 100 MHz. * Assuming normalized power noise of σVDD /|VDD| = 1.0e and noise bandwidth of fnoise=100MHz.

FigureFigure 5. 5. SIMULINKSIMULINK model model for for a a 4th-order 4th-order modulator. modulator.

ItIt can be seen that SCR, SSI, and FWP feedback are most effective to reduce clock jitter effects and they they are are to to be be used used when when clock clock jitter jitter is relatively is relatively large. large. However, However, it is itimportant is important to note to notethat they that havethey havepractical practical limitations limitations due dueto noise, to noise, namely namely intrinsic intrinsic device device noise noise and and extrinsic extrinsic power power supply supply noise. Note Note that that noise noise is is the the fund fundamentalamental reason reason behind behind even even clock clock jitter jitter itself itself (in (in an an oscillator or or a phase-locked-loop [[34])34]) and it similarly causes variation/jittervariation/jitter of of the the feedback feedback charge charge in in each each feedback feedback techniquetechnique (note (note that that in in typical typical scenarios scenarios it it is is assumed assumed that that the the noise noise sources sources are are uncorrelated so so the clock jitter itself is independent independent from the variation/jittervariation/jitter of of the the feedback feedback charge charge).). In In fact, fact, any any technique technique would only be effective to reduce clock jitter effectseffects whenwhen thethe variation/jittervariation/jitter of of the feedback charge due to noise is less less or or equal equal to to that that of of the the clock. clock. Th Therefore,erefore, it it is is imperative imperative to to study study their their performance performance under practical noisenoise inin contrastcontrast to to the the previous previous case case of of without without noise. noise. Recently Recently in [in35 ],[35], the the author author did dida theoretical a theoretical noise noise analysis analysis of the of SCR, the SSI,SCR, and SSI, FWP and techniques FWP techniques to study to their study limits their under limits external under externalpower supply power noise supply (as noise it is typically (as it is dominanttypically dominant over intrinsic over deviceintrinsic noise) device and noise) made and an analyticalmade an analytical comparison. For the sake of practical comparison in this paper, we designed transistor- level circuits in Figures 3–5 and performed electrical simulation in Cadence Virtuoso [36] on the same modulator as above to derive the SNR assuming typical wide-band white noise (with normalized | | noise power of / = 1.0 and noise bandwidth of = 100 MHz as in [35]). The results are shown in the last three rows of Table 1 when practical noise was considered. We summarized the major finding below. Under practical noise, each technique indeed has a limitation to reduce jitter

J. Low Power Electron. Appl. 2017, 7, 22 7 of 11 comparison. For the sake of practical comparison in this paper, we designed transistor-level circuits in Figures3–5 and performed electrical simulation in Cadence Virtuoso [ 36] on the same modulator as above to derive the SNR assuming typical wide-band white noise (with normalized noise power of −3 σVDD /|VDD| = 1.0e and noise bandwidth of fnoise = 100 MHz as in [35]). The results are shown in the last three rows of Table1 when practical noise was considered. We summarized the major finding below. Under practical noise, each technique indeed has a limitation to reduce jitter effects as the SNRs are clearly below those without noise. The specific limit of each technique mainly depends on the characteristic of the external noise (i.e., noise bandwidth and power) and the specific modulator design (i.e., sampling frequency). Given the same external noise, it is found that the FWP feedback technique is most effective to reduce most clock jitter effects with relatively high sampling frequency (for example, hundreds of MHz), whereas SCR and SSI techniques have best performance with low to medium frequency (for example, tens of MHz or below). When sampling frequency gets lower, the SCR and SSI techniques would be closer to break the limitation from the noise, due to increased filtering of the external power noise from the resistor-capacitor. This trend can be seen in the last three rows of Table1 as the SNRs for SCR and SSI techniques saturate to those in the second row of Table1 as frequency decreases. Also, note that when frequency is low, FWP feedback is not to be used due to significant power/area overhead, as mentioned before. Finally, note that the above practical simulation results agree well with the theoretical analysis results in [35].

2.3. Overall Comparison of the Techniques In Table1, we compared different feedback techniques in terms of effectiveness of jitter noise reduction on a common basis with/without noise. However, effectiveness of jitter noise reduction should not be the only factor when objectively evaluating the different techniques and other factors must be factored in to get a better picture. Therefore, for the sake of completeness, we also make a qualitative comparison of the different feedback techniques considering six major factors in Table2. First, we rated the techniques in terms of effectiveness (in the second row of Table2) by inferring from the results presented in Table1.

Table 2. Comparison of different methods considering six factors.

SI NRZ/RZ FIR SIN SCR [24] SSI [29] FWP [30,31] [16,17] [22,23] Single-Bit [6] Multi-Bit [4] Effectiveness of jitter * ** ** ** *** (at low freq.) *** (at low freq.) *** (at high freq.) noise reduction Ease of modulator *** *** * * * * *** synthesis Simplicity of *** * ** * ** * *** implementation Power consumption *** ** ** * * *** ** overhead Extensibility to multi-bit *** - * * ** * *** Robustness to *** * *** *** ** ** *** process variation * Represents lowest rating and *** highest rating.

Next, in terms of synthesis of the modulator: single-bit/multi-bit NRZ/RZ feedback has the rectangular-shaped current, so synthesis of the modulator at system-level design is very easy using Z-transform or modified Z-transform [37,38]. The FWP feedback retains the traditional rectangular-shaped current like the RZ feedback, so synthesis of the modulator is easy too. Synthesis of the modulator with FIR, SIN, and SCR feedback is sophisticated due to their special waveforms shapes [38]. Systematic synthesis of a modulator with SSI feedback is particularly difficult due to its wild and not-well-controlled waveform shapes and significant tuning may be needed. The comparison results are shown in the third row of Table2. J. Low Power Electron. Appl. 2017, 7, 22 8 of 11

Regarding circuit implementation, when compared on a common single-bit modulator design, NRZ/RZ, FWP, and SCR feedback are easier compared to most other methods, particularly the SIN and SSI feedback (see Section 2.1 for details). Note multi-bit SI DAC was not rated high due to design overhead from possible linearization/matching needs. In addition, the FWP feedback has only moderate demand for performance of active elements, such as OpAmp slew rate and gain-bandwidth product. This demand is slightly more compared to the NRZ/RZ feedback and SSI feedback, but much more relaxed to SCR feedback. Therefore, from this point of view, power consumption of a modulator employing the FWP feedback may be slightly larger than that employing the regular NRZ/RZ feedback and SSI feedback, but much less to SCR feedback. The comparison results are shown in the fourth and ﬁfth row in Table2. Furthermore, it is straight-forward to extend the single-bit NRZ/RZ and FWP feedback from single-bit to multi-bit operations due to compatibility to traditional SI feedback, whereas it is much harder for all other types of feedback due to either matching or linearization issues or additional circuit design overhead. Finally, the RZ or FWP feedback is potentially more robust to process variations, which ease the nominal design. It is noted that process variation does not cause jitter induced charge error but only frequency response shift, which causes little performance degradation. As studied in [39], even with a large variation range (e.g., −20% to +30%) of the active feedback pulse of td2, there is no notable performance degradation (especially if compensation was used). However, under process variation, the current decreasing rate for SCR feedback or the operation region for SSI feedback changes, which may cause increasing jitter induced charge error and frequency response shift. The former may affect the effectiveness of the SCR or SSI feedback on jitter noise reduction. Therefore, a worst-case design for SCR or SSI feedback is preferred under process variation, which may result in over-design or more power consumption. The comparison results in terms of extensibility to multi-bit operation and robustness to process variation are given in the last two rows of Table2. In Table2, it can be seen that no single technique is the winner in all aspects. To designers, a general strategy to select a technique may be as follows. If clock jitter is relatively large, performance degradation is accordingly large, therefore SCR, SSI, or FWP may be used. Which of them to select then depend on the sampling frequency. If clock jitter is relatively small (and performance degradation is relatively minor), FIR feedback (or even SI NRZ) may be used as in [38] and is preferred to SIN feedback. Finally, it should be noted that Table2 is mainly meant to provide a qualitative and intuitive comparison in typical application scenarios and thus may be over-simpliﬁed.

2.4. Discussion It should be noted that by no means is the above review of previous work on clock jitter noise reduction complete. The different methods discussed above focus on shaping the feedback waveforms to reduce pulse-width jitters in circuit-level design. In literature, there are also alternative methods that do not rely on shaping the feedback waveform. For example, one reported technique to reduce clock jitter effects is to revise modulator NTF (Noise Transfer Function) at system-level design based on an approximate relationship between the jitter noise power and the modulator NTF [40,41]. It was found that modulator NTFs designed with peaking in their passbands may result in lower jitter noise than maximally ﬂat NTFs. For an optimized NTF, the technique is effective to reduce clock jitter noise by up to 9 dB compared to a non-optimized one while quantization noise suppression capabilities are comparable. Nonetheless, having peaking in passband may not be desirable in modulator design. More importantly, such a technique at system-level design is not as effective as SCR, SSI, or FWP feedback techniques. It should also be noted that all reported methods discussed above consider ICJ [6] and have been shown effective in this case. For the sake of completeness, we next brieﬂy discuss the case of J. Low Power Electron. Appl. 2017, 7, 22 9 of 11

Accumulated Clock Jitter (ACJ) [6]. For ACJ, the sampling instants are considered as the accumulation of all previous sampling intervals and become:

n tn = nTS + αn, αn = ∑ τi, n = 0, 1, 2, . . . , N (2) i=0 where τi is jitter of the clock cycle i (in contrast to jitter of the rising/falling edge in the ICJ) and is modeled as i.i.d Gaussian noise [6]. Though the statistics of τi are independent and stationary, those of αn are not. ACJ is typically caused by voltage controlled oscillators with limited stability [6]. SNR of the modulator with ACJ degrades signiﬁcantly when σCLKACJ of τi increases as in the case of ICJ. −4 −2 When σCLKACJ of τi is in the range of 1.0e TS to 1.0e TS (which is the range typically studied for ICJ), the SNR of the modulator is only marginally improved by 3 to 5 dB when either SCR, SSI or FWP feedback is applied to reduce clock jitter noise. It is obvious that any of the feedback techniques is much less effective for ACJ than ICJ. A very similar observation is reported in [42] when SCR feedback is applied but found not effective for ACJ. In typical circuit implementations, the clock is usually derived from Phase-Locked-Loop (PLL), which is neither truly ICJ (with white phase noise) nor ACJ (with large noise skirts), but a complex combination of them. In this case, SCR, SSI, or FWP may still be useful for jitter noise reduction based on the analysis results in [12].

3. Conclusions In this paper, we presented a detailed review and comparison of previous work reported in literature to reduce clock jitter effects in lowpass continuous-time Delta-Sigma modulators. It was found that the SCR, SSI, and FWP feedback techniques are more favorable in terms of effectiveness on jitter noise reduction. However, in practice, the effectiveness of each technique is limited by external noise. Assuming typical wide-band white noise, it was found from electrical simulations that FWP feedback is most effective at high sampling frequency (of hundreds of MHz), while SCR and SSI techniques have best performance at low to medium frequencies (of tens of MHz or below). In addition to the quantitative comparison of SCR, SSI, and FWP techniques in terms of effectiveness to reduce clock jitter effects with and without noise, a qualitative comparison of all is given considering also other performance metrics, such as ease of modulator synthesis, simplicity of circuit implementation, power consumption overhead, extensibility from single-bit to multi-bit operation, and robustness to process variation. The presented results would be very helpful to circuit designers to decide on which technique to use for their speciﬁc design scenarios.

Acknowledgments: The authors acknowledge the support from EVCAA special research fund at University of Minnesota Duluth in the early stage of the work. Author Contributions: H.C. designed and simulated some of the circuits under H.T. supervision. Conﬂicts of Interest: The authors declare no conﬂict of interest. The founding sponsors had no role in the design of the study; in the collection, analyses, or interpretation of data; in the writing of the manuscript, and in the decision to publish the results.

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