AH1721 SJA1105SMBEVM User Manual Rev

AH1721 SJA1105SMBEVM User Manual Rev. 1.00 — 16 July 2018 User Manual

Document information Info Content Keywords SJA1105PQRS, SJA1105S, SJA1105S Evaluation Board, SJA1105SMBEVM, Cascading, Ethernet, Wakeup, Sleep Abstract The SJA1105SMBEVM Evaluation Board is described in this document.

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Revision history Rev Date Description 1.00 20180716 Release

Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: mailto:[email protected]

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1. Introduction The SJA1105SMBEVM (SJA1105S Mother Board Evaluation Module, see Fig 1) is designed for evaluating the capabilities of the SJA1105P/Q/R/S Automotive Ethernet switch family and the TJA1102 Automotive Ethernet PHYs, by developing and running customer software. Therefore, the board features the MPC5748G MCU with a rich set of peripherals for communication and automotive applications. It is designed to allow early adaptions of applications, like a X-to-Ethernet gateway, communication hub, etc.

Fig 1. SJA1105SMBEVM board

This user manual describes the board hardware and the software development environment to allow the user to quickly bring up a working system and to pave the way towards an own customized software, and in the end towards an all custom system. After the HW description the manual walks the user through the process to create the factory firmware starting at the supplied example project and describes the recommended SW development environment S32 Design Studio for Power as far as it is needed for the example project. 2. Prerequisites Besides this document and the hardware package you will need the following support material - consult https://www.docstore.nxp.com and https://www.nxp.com SJA1105PQRS User Manual (UM11040) SJA1105PQRS Data sheet SJA1105PQRS Application Hint (AH1704) TJA1102 Datasheet

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TJA1102 Application Hint (AH1508) SJA1105S Evaluation Board Software Package TJA1145FD CAN-Transceiver Product data sheet and Application Hint (AH1309) MPC5748G reference manual If you want to download and run SW on the SJA1105SMBEVM you also need a JTAG- Debug adapter. The easiest solution is the PEMicro “USB Multilink Universal” USB-to- JTAG debug probe (http://www.pemicro.com/products/product_viewDetails.cfm?product_id=15320168), as this is already integrated in the S32 Design Studio IDE. 3. System Overview

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Fig 2. Block diagram indicating the primary functional blocks and interconnections

The primary functional components of the SJA1105SMBEVM Evaluation Module are: • 1 Microcontroller MPC5748G • 2 switches SJA1105S: ETH-SW(A) and ETH-SW(B) • 3 100BASE-T1 PHYs: ETH-PHY TJA1102 (2*) + TJA1102S • 2 1000BASE-T PHYs: 1G PHY KSZ9031 • 1 100BASE-TX PHY; FE PHY DP83848C • 1 CAN Transceiver TJA1145FD • 1 UART-USB-Converter FT230XQ The main Ethernet data paths are:

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• Switch-A and Switch-B can exchange ethernet data via a SGMII connection at 1GBps. • Port0 of the MPC5748G is wired to Switch-A Port0 using MII-Lite at 100MBps. • The FE-PHY is directly connected to MPC5748G’s Port1, also with MII-Lite. • The 1G-PHYs are connected to Switch-A’s ports 2 and 3. These links support speed autonegotiation, but not direction autonegotiation. The actual link speed depends on the result of the autonegotiation process. 4. Hardware Description

4.1 Power The SJA1105SMBEVM is powered by a single 12 Volt input. It is advised to use an adapter that can deliver at least 1 Amp for covering startup current peaks and full-load situations. The nominal current is ~350mA@12V and depends on the number of active PHYs, and if the port is connected to a peer.

Fig 3. Power supply topology

The power supply topology is shown in Fig 3. The switching regulators for 5V0, 3V3 and 2V5 are controlled by the signal VREG_EN, which can be either fixed to “enable” or controlled by a combination of an output signal from the PHYs and some sign-off signal from the CPU. The selection is done with a jumper (J6). With this schema, most of the board can be switched off when entering sleep mode. For more details see chapter 6.4.

4.2 MPC5748G Microcontroller The microcontroller runs the user’s software, which controls all components on the board, e.g. switches, PHYs, LEDs, etc. It also has an ethernet connection to the switches, so it can receive and send ethernet packets. Therefore, the microcontroller can work as a host controller for protocols like gPTP, where the software works in conjunction with hardware features implemented in the switches. which are only partly implemented in the switches, and need SW assistance. The MPC5748G features: • 2 e200Z4 32bit cores with 160MHz and 8k I-cache + 4k D-cache

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• 1 e200Z2 32bit core with 80MHz • 6MB on-chip flash and 768kB internal RAM • 2 independent 100Mbps ethernet ports with AVB and 1588 support • 6 SPI, 18 LIN/UART, 8 CAN (with FD support), 4 I2C and USB peripheral blocks • Standard microcontroller infrastructure, like interrupt controller, DMA, timer, watchdog, JTAG debug interface, etc. For making the task to create user’s software easier, there is an example project, which initializes all peripherals on the SJA1105SMBEVM and implements basic functions, like communicating via the USB-UART adapter, configuring the PHYs and switches, sending and receiving ethernet packets, sending and receiving CAN frames, dealing with PHY plug events, etc. This example project serves as a foundation for user extensions for specific applications. The SW development environment and the example project is described in chapter 6.

4.3 SJA1105S switches The SJA1105S is an IEEE 802.3-compliant 5-port automotive Ethernet switch supporting Audio Video Bridging (AVB) and Time-Sensitive Networking (TSN) standards. It is a member of the SJA1105P/Q/R/S family of switches:

Table 1. SJA1105P/Q/R/S variants Device SGMII interface TT-Ethernet and TSN-Ethernet SJA1105P No No SJA1105Q No Yes SJA1105R Yes No SJA1105S Yes Yes

The SJA1105S’s fifth port is a SGMII-only port and is capable to operate at up to 1Gbps. The other four ports can be individually configured to operate at 10Mbps, 100Mbps or 1Gbps, depending on the capability and configuration of the PHY connected. Interfacing a PHY to one of these four ports can be done using one of the 3 supported MII interface standards: MII, RMII or RGMII. This port arrangement provides the flexibility to connect a mix of PHY devices such as the TJA110x 100BASE-T1 PHYs from NXP Semiconductors and other commercially available Fast Ethernet and Gigabit Ethernet PHYs, or fiber optic PHYs. The high-speed interface makes it easy to cascade multiple switches of the SJA1105 family for scalability. It can be used in various automotive scenarios such as gateway applications, body domain controllers or for interconnecting multiple ECUs in a daisy chain. Full Audio Video Bridging (AVB) support means that the SJA1105 family can be used in infotainment and driver assistance systems. Time-triggered Ethernet and Time-Sensitive Networking support with IEEE 802.1Qbv time-aware traffic shaping and IEEE 802.1Qci per-stream policing makes the SJA1105 family usable in applications with hard realtime communication requirements. In the SJA1105SMBEVM design, the switches are used in a cascaded topology: the SGMII ports are connected to create a high-speed link for forwarding payload ethernet frames and management data frames. Cascading also includes HW provisions to synchronize the PTP clock counter by using a master/slave clock configuration. The usage of the switches’ ports is shown in Table 2.

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4.4 TJA1102 PHYs for 100BASE-T1 The TJA1102 is an OPEN Alliance 100BASE-T1 compliant Dual Ethernet PHY optimized for automotive use cases. The device provides 100Mbit/s transmit and receive capability over a single Unshielded Twisted Pair (UTP) cable, supporting a cable length of up to at least 15 m. Optimized for automotive use cases such as IP camera links, driver assistance systems and back-bone networks, the TJA1102 has been designed to minimize power consumption and system costs, while still providing the robustness required for automotive use cases.

The default configuration of the TJA1102 PHYs on the SJA1105S Evaluation Module are detailed in Table 2, together with the interconnection to the switch ports. The PHYs’ default configuration can be overruled by issuing SMI commands to the PHY.

Table 2. Ethernet port usage and default PHY configurations MAC: PHY/Peer MII mode: Connector SMI Master / Slave: address: Switch A0 Proc Port0 MII-Lite - - - Switch A1 U19, TJA1102S RMII J11 4 Master Switch A2 U18, KSZ9031 RGMII P2 2 - Switch A3 U17, KSZ9031 RGMII P1 3 - Switch A4 Switch B4 SGMII - - - Switch B0 U21A, TJA1102 RMII J14 6 Master Switch B1 U21B, TJA1102 RMII J15 7 Master Switch B2 U20A, TJA1102 RMII J12 8 Master Switch B3 U20B, TJA1102 RMII J13 9 Master Switch B4 Switch A4 SGMII - - - Proc Port0 Switch A0 MII-Lite - - - Proc Port1 J4 MII-Lite J4 1 -

4.5 PHYs for copper ethernet For the two GBit (1000BASE-T) ports A2 and A3 the KSZ9031 PHY is used. The two PHYs are connected to Switch-A via RGMII. The single FE (100BASE-TX) port, which makes the MPC5748G’s 2nd ethernet port available, uses a DP83848 PHY. The copper ethernet PHYs are configured to allow autonegotiation. This requires SW assistance to configure the MACs in the switch or the in the µC to the interface speed.

4.6 CAN interface The SJA1105SMBEVM features a CAN interface, which is implemented with one of the MPC5748G’s FlexCAN-controllers and the TJA1145TK/FD CAN transceiver. In the example project, the CAN-interface is configured with 100kbps and a payload size of 8Byte. FD extensions are not used. The TJA1145TK/FD requires a configuration setting via SPI before it can forward data. This is also done in the example project.

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4.7 LEDs

Fig 4. LEDs and Connectors

Table 3. SJA1105SMBEVM LEDs overview LED label Color Description: D1 red Indicates if the reset line for the on-board μC is active. D2, D4, green link-up indication LEDs for the 100BASE-T1 ethernet ports. Each LED D5, D15, is controlled by the on-board uC. and is set/cleared by the D16 LinkUp/LinkFail interrupt of the associated port’s PHY. D2: Port A1 D4: Port B0 D5: Port B1 D15: Port B2 D16: Port B3 J4-L, J4-R L=green LEDs integrated in the FE connector J4 R=yellow L = Link; controlled by the FE-PHY U10 LEDLINK output. By default (Mode 1) the LED is on when there is a good link on the port. R = Activity; controlled by the FE-PHY U10 LEDACTCOL output. By default (Mode 1) the LED is on during activity on either TX or RX.

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LED label Color Description: P2-L, L=green LEDs integrated in the GBit connectors P2 and P3 P2-R, R=yellow L is controlled by the GBit PHY’s LED2 output, and R by the LED1 P3-L, output. In Tri-Color dual-LED mode the following settings are used: P3-R state L = green R = yellow Link off off off 1000 Link, no activity on off 1000 Link/Activity (RX, TX) blink off 100 Link, no activity off on 100 Link/Activity (RX, TX) off blink 10 Link, no activity on on 10 Link/Activity (RX, TX) blink blink

D6, D7, green Power-Good LEDs for the voltages generated by switching regulators. D8 D6 = 5V0 D7 = 3V3 D8 = 2V5 D11, D12 green Power-Good LEDs for the voltages generated by LDOs. D11 = 1V8 D12 = 1V2 D3 green Labeled “ALIVE”. General purpose LED connected to the uC. Used by the μC software as a heartbeat. This LED should continuously blink if the example SW is running. D17 green General purpose LED connected to the uC. No special meaning. D13 green PTP LED. The LED is connected to SwitchA’s PTP_CLK output by a transistor inverter. If PTP_CLK is low, the LED is off.

Positions of the LEDs are shown in Fig 4.

4.8 Jumper blocks and connectors The position of the jumper blocks and connectors is shown in Fig 4.

Table 4. Jumper blocks and connectors Name Meaning/Usage J1 Power Jack 12V input J2 USB Type B receptacle for the serial link to PC J3,J5 CAN bus termination setting; J3 = CAN_L, J5 = CAN_H 1-2: 120R termination active (used for an end node on the CAN bus) 2-3: 2k6 termination active (used for a middle node on the CAN bus) No jumper: No termination J4 Fast Ethernet RJ45 receptacle with LEDs J6 Jumper block for selecting the source of the enable signal VREG_EN to the switching power regulators (5V0, 3V3, 2V5) 2-3: 12V0 – regulators permanently enabled 1-2: VREG_EN is under control of the PHYs and the processor – see ch 6.3 for sleep/wakeup

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Name Meaning/Usage J7 Screw type terminal block for CAN bus Pin 1: 5V0 Pin 2: CAN_L Pin 3: CAN_H Pin 4: GND J9 Header block to easily access SPI and SMI signals for debugging purpose Pin Description Pin Description 1 GND 2 SPI1_CLK 3 SMI – MDIO 4 SPI1_MOSI 5 SMI – MDC 6 SPI1_MISO 7 GND 8 SPI1_CS0 (Switch-A) 9 WAKE_IN_OUT 10 SPI1_CS1 (Switch-B)

J10 Debug connector for flashing the uC and for SW debugging J11..J15 100BASE-T1 cable screw blocks J11: Port A1 J12: Port B2 J13: Port B3 J14: Port B0 J15: Port B1 P1, P2 GBit Ethernet RJ45 receptacle with LEDs P1: Port A3 P2: Port A2

4.8.1 USB connector The USB receptacle J2 connects to a USB-to-UART converter FTDI FT231X1. It is included on the board to provide an easy serial interface between a host computer and the μC. The example SW project uses this interface for a debug console with 115200- 8N1 and no HW handshaking protocol. Use TeraTerm or any other terminal emulation software for accessing the console. To access the µC’s UART via USB under Windows, a device driver from FTDI must be installed. This device driver provides a virtual COM port to be used by the terminal emulation software or other applications accessing the µC’s UART. The FTDI device driver can be downloaded from http://www.ftdichip.com/FTDrivers.htm 4.8.2 Software debug connector The debug connector J10 implements a standard 14pin OnCE/Nexus interface (with underlying JTAG signals), which is in use for all PowerPC processors of the MPC5xxx familiy. A debug solution for the MPC5xxx family, like PEMicro’s USB Multilink Universal, or Lauterbach Trace32 for Quorivva presumes an adapter compatible with this standard. J10 uses the following pinning:

1 http://www.ftdichip.com/Products/ICs/FT231X.html

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Table 5. Pinning of the debug connector J10 Meaning/Name Pin Pin Meaning/Name JTAG_TDI 1 2 GND JTAG_TDO 3 4 GND JTAG_TCK 5 6 GND n.c. 7 8 n.c. JTAG_RESET (PowerPC Reset) 9 10 JTAG_TMS VREF (3V3) 11 12 GND n.c. 13 14 JCOMP (10k pulldown)

4.9 Buttons and switches

Table 6. Buttons and switches Name Meaning/Usage SW1 Wakeup – connects the PHYs’ wakeup line with VCC – this is for wakeup/sleep SW2 Reset button – controls the uC’s reset input. SW3, General purpose buttons connected to interrupt capable GPIOs SW4 SW3: Button0 SW4: Button1 SW5 Rotary switch with 16 positions

The software can make use of the rotary switch to select a specific board configuration. The example software project uses the rotary settings in the following way to enable/disable ethernet and/or CAN operation:

Table 7. Rotary switch configuration in the example project Configuration: Ethernet operation CAN operation 0 no no 1 yes yes 2 yes no 3 no yes 4-F Not used – see configuration #0

For ethernet operation, the switches and PHYs are initialized and configured with a simple setup, and the µC periodically sends out a packet on its both ethernet ports – one port connected to the switches and another one to the FE port. For CAN operation the µC periodically tries to send out a CAN telegram, and reports received telegrams on the serial console. 5. Getting started The following steps are required to bring the SJA1105SMBEVM into operation: 1. Installation of the software development environment S32DS for Power Architecture

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2. Import the example project for SJA1105SMBEVM and build an executable file 3. Flash the executable and start it 4. Connect ethernet stations and send traffic 5. Modify the Software according to the special needs of the project

5.1 Install S32DS The S32 Design Studio for Power Architecture home page is at https://www.nxp.com/support/developer-resources/run-time-software/s32-design-studio- ide/s32-design-studio-ide-for-power-architecture-based-mcus:S32DS-PA At the time of writing this document you need • the basic packet “S32 Design Studio for Power Architecture 2017.R1 - Windows/Linux” and • the cumulative update “S32 Design Studio for Power Architecture 2017.R1 Update 2 - MPC574xx SDK BETA 0.9.0” Refer to the screenshots in Fig 5 for downloading the development environment and the SDK update. Design Studio has its own documentation on installation and usage of the software, so this is only partly covered here.

Fig 5. S32DS installation packets for download

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Installing the base package is straight forward: just execute the downloaded program, and answer the questions. At one point enter the license number you have received via email. SDK 0.9.0 is not part of the base package, but it must be installed in a separate step. This can be done either • Online: S32DS/Eclipse downloads the package itself and installs it then. This requires that Eclipse can access the internet, which is often not possible due to corporate firewall rules and proxy architectures. Web browsers are usually capable to deal with these topics, but for other SW this is cumbersome. • Offline: the update package is downloaded with the web browser and temporarily stored in the filesystem, just like the base package. For installing the update, the user must point Eclipse to the downloaded package. The second method is shown in the following steps: 1. In S32DS IDE select “Help -> Install New Software”

Fig 6. S32DS installing SDK update – step 1

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2. Click “Add…”

Fig 7. S32DS installing SDK update – step 2

3. Click “Archive…” and select the .zip file with the update/patch downloaded earlier and stored in the filesystem. Click “OK”

Fig 8. S32DS installing SDK update – step 3

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4. It will start installing the patch to the S32DS_Power installation tree. Upon completion, you should see the Beta_0.9.0 folder:

Fig 9. S32DS installing SDK update – step 4

5.2 Import example project files and build an executable file The following step-by-step guidance is just ONE way how to create an executable .elf file from the example project .zip file. This is a known working way, but there may be faster alternatives. • Choose your workspace – usually just an (empty) directory in the user’s part of the file system. • Start S32 Design Studio for Power Architecture and select this workspace • You will see an empty Project Explorer pane (usually upper left corner) • Create an empty project with “File -> New -> Project” (not “C-Project”, not “Project from Example”, just pure “Project”) and choose a wizard with “General -> Project”. Use a project name, for example “sja1105smbevm_example”2 and select to use the default location, which is just inside the workspace. • A new project with the chosen name appears in the project explorer. • In the context menu of this project (right click) call “Import” and as a wizard select “General -> Archive file”. Select the .zip file with the example project blob. You

2 If you use a different project name than “sja1105smbevm_example”, you will later have to adjust the debug setting.

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may have to select a folder for importing to – use the project folder. During execution after “Finish”, there may be a warning, that existing resources will be overwritten, which you should acknowledge: the generic project’s resources must be substituted by the files in the example project blob. • While import is running, you can see activity on the lower right corner of the eclipse window, saying “C/C++ Indexer” and “Building workspace”. • In case you don’t see the ProcessorExpert’s component window in the lower left corner, select “ProcessorExpert -> Show Views”. This enables another phase of import activity. • During import, a couple of warnings appear in the console window, e.g. 08.05.2018 12:55:41 Starting Processor Expert service System directory = C:\NXP\S32DS_Power_v2017.R1\eclipse\ProcessorExpert Internal cache directory = C:\ProgramData\Processor Expert\PECache\26661c51 Processor Expert license file = not used (no license file) 08.05.2018 12:55:42 Successfully started Processor Expert service Type specification is not defined "typedspi_bitsperframe_t", symbol: MasterbitsPerFrame Type specification is not defined "typedspi_bitsperframe_t", symbol: MasterPCS Type specification is not defined "typedspi_bitsperframe_t", symbol: MasterbitsPerFrame Type specification is not defined "typedspi_bitsperframe_t", symbol: MasterPCS Type specification is not defined "typedspi_bitsperframe_t", symbol: MasterbitsPerFrame Type specification is not defined "typedspi_bitsperframe_t", symbol: MasterPCS Error: Unknown type info: typedspi_bitsperframe_t in item "Bits/frame "/MasterbitsPerFrame from component /dspi Error: Unknown type info: typedspi_bitsperframe_t in item "PCS"/MasterPCS from component /dspi Error: Unknown type info: typedspi_bitsperframe_t in item "Bits/frame "/SlavebitsPerFrame from component /dspi Error: Unknown type info: typedspi_bitsperframe_t in item "Bits/frame "/MasterbitsPerFrame from component spi_sw/dspi Error: Unknown type info: typedspi_bitsperframe_t in item "PCS"/MasterPCS from component spi_sw/dspi Error: Unknown type info: typedspi_bitsperframe_t in item "Bits/frame "/MasterbitsPerFrame from component /dspi Error: Unknown type info: typedspi_bitsperframe_t in item "PCS"/MasterPCS from component /dspi Error: Unknown type info: typedspi_bitsperframe_t in item "Bits/frame "/SlavebitsPerFrame from component /dspi Type specification is not defined "typedspi_bitsperframe_t", symbol: MasterbitsPerFrame Type specification is not defined "typedspi_bitsperframe_t", symbol: MasterPCS Type specification is not defined "typedspi_bitsperframe_t", symbol: SlavebitsPerFrame

• caused by a Processor Expert bug and can be ignored (according to the developers) • These warnings and errors are false positives and can be ignored. • Once the import is complete, you can see the components managed by ProcessorExpert on the lower left window, called “Components”. If you change some PEx component configuration (with the help of the PE component inspector) start PE’s code generation with Project -> Generate Processor Expert Code. • Build the project by clicking the hammer symbol (or by Project -> Build All), using the build configuration “Debug_FLASH”, and watch the progress in the Console window on the lower right pane (see Fig 10).

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Fig 10. Screenshot of a successfully created executable

If all goes well you will have a .elf file, which can be downloaded and started on the target board with a JTAG debugger, like PEMicro ML universal or with the Lauterbach debugger.

5.3 Download and run the firmware The following description presumes that the PEMicro ML Universal probe is used. • Call “Run -> DebugConfigurations” (also available under the beetle symbol) and check the entries in the configuration with the “debug_flash_pemicro” suffix (see Fig 11)

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Fig 11. Screenshot of the debug configuration popup window part1

If you have chosen the recommended project name “sja1105smbevm_example” (ch. 5.2) you will see a predefined debug configuration under “GDB PEMicro Interface Debugging”, else you must add some items for your debug configuration in the “main” and “debugger” pane. Refer to Fig 12 and Fig 13 for details:

Fig 12. Screenshot of the debug configuration popup window part2

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Fig 13. Screenshot of the debug configuration popup window part3

• Make sure you have the debug adapter connected to the PC, and the SJA1105SMBEVM connected to the adapter and powered up before continuing. • When activating the debug configuration, you can see the actions behind the scenes on the console window. Usually this involves connecting to the GDB server in the debug probe, erasing the flash, downloading and writing the program image to the flash, and starting the downloaded image. • If everything went well, you will see the debug view (a combination of windows and sub-windows well adapted for debugging), and the main window will show, that the program has stopped on “main()” and is expecting user input (see Fig 14). • If you select Run -> Run (or Ctrl-F11), the program continues, and you should see the Link-LEDs blinking with a characteristic startup test pattern. After that, the Alive-LED D3 is blinking at a steady rate.

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Fig 14. Screenshot of a debug session

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5.4 Example Software features The example software project implements the following exemplary features: • Changing the rotary switch while the FW is running causes a reboot. • With dial-setting #1 and #2, ethernet functions are enabled. This means: o All ports receive untagged traffic and traffic on VLAN-0. Egress traffic is always untagged. o Traffic is forwarded between all ports (except the FE port). This includes dynamic address learning, and transparent forwarding over the cascading SGMII link. o No policers, no traffic shapers. o the GBit-Ports and the FE-Port allow auto-negotiation for link speed only. This is since the switches’ MACs only allow full duplex links. o The uC periodically sends out data packets on its ENET0 (connected to the switch) and ENET1 (FE) ports. As the chosen destination address 08:00:27:02:12:88 is not known in the switch’s L2 address tables, the packets are flooded to all ports. The µC uses 08:00:27:02:12:01 and 08:00:27:02:12:02 as source address. These addresses are configured with ProcessorExpert in the ENET device driver. o For 100BASE-T1 ports, the Link LED indicates an established link. All 100BASE-T1 ports on the SJA1105SMBEVM take the master role, so the peers must be configured for slave, so that a link can come up. This can be changed by SW, but it is not implemented in the delivered example. • With dial-setting #1 and #3, the CAN interface is activated. The uC then periodically sends out a CAN-frame at 100kBit/sec, using 8 payload bytes and the CAN-ID 333h. Can-FD is not used. With each frame, the 2nd Byte is incremented, and when having reached 255 wraps around.

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6. Example project software

6.1 Components and Layers

Fig 15. Software components and layers

The example project consists of the following components and layers (refer to Fig 15, bottom to top): • Board HW components, like the various PHYs, the CAN-Transceiver, the switches, etc. These are components which need a device driver to control the component’s features. • The board HW components are connected to peripherals in the µC, which are, for example, implementing a communication interface (UART, SPI, xMII, SMI, etc.) or simply GPIOs. For simplicity, the GPIOs are not drawn in Fig 15, but they control LEDs, reset and enable lines of those on-board HW components. The uC ENET peripheral has an MII(Lite)-Interface for ethernet data, but also a SMI interface for accessing the PHYs. • The next upper layer contains the SW components, which come with S32DS’s SDK: SDK components are for example: o device drivers for the µC peripherals, e.g. SPI, clock, ADC, CAN, UART, GPIO, etc. o device drivers for classes of peripherals outside the of the µC: For example, the PHY device driver handles generic PHYs (like the GBit and FE copper PHYs) but also special PHYs, like the TJA110x family. This driver uses the

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services of the ENET driver for the ENET0 block to access the PHYs via ENET0’s SMI interface. o peripheral abstraction layers to provide a uniform API for a device driver class to enable writing generic application code runnable on different hardware platforms. The UART_PAL component is an example for this. o Generic higher-level infrastructure software, like communication stacks, real time kernels, filesystems, etc. In the example project, FreeRTOS is configured to allow separating functions into realtime tasks, and make use of delays, synchronization, inter-task-communication, etc. o The pinmux component is special, as it is the central place for configuring all IO pins – this starts with allocating one of many possible pins for a particular peripheral component IO, for example MISO pin for a SPI block. Pin configuration goes as far as enabling a pullup or a pulldown or none, configuring push-pull or open-drain output style, enabling input hysteresis for Schmitt behavior, etc. etc. Each SDK component is activated and configured with ProcessorExpert, a utility and database coming with S32DS. The components used in the example project are all preconfigured to the needs for the actual HW components used on the SJA1105SMBEVM board, and the smooth interaction with the application layer and communication peers. The configuration is done interactively within the Eclipse framework. The default settings may be perused and changed if needed. The SDK’s API documentation is available in the .html tree starting at the SDK installation folder in C:\NXP\S32DS_Power_v2017.R1\S32DS\S32_SDK_MPC574xx_BETA_0.9.0\doc, A list of the device driver calls is provided within the Eclipse framework in the ProcessorExpert’s Components window, when unfolding a device entry. • There are device drivers between the SDK component layer and the application layer which are not integrated in ProcessorExpert and the SDK framework, but come from other sources. So technically, these are application components, but logically, they are still device drivers, which abstract the view of the hardware components by an API. The SJA1105SMBEVM employs such an example, which is the NXP SJA1105PQRS switch driver. This driver provides a low-level sublayer and an application-oriented high-level sublayer. The switch driver requires static configuration streams to be downloaded to the switches. These streams are contained in a configuration source file, and represented in the source code file as byte arrays. The example project comes with a default set of basic configuration streams, which can be expanded step by step, when need arises. Therefore, the Python tools for dealing with the configuration comes with the example project. For the first attempts, a ready-to-use .c file “NXP_SJA1105P_configStream.c” is included. See ch 6.3 for more details. • On top of this there is the application layer. This layer is split into sections with different properties. o SJA1105SMBEVM specific application data: sja1105smbevm_ethsetup.c contains board specific data about relations between HW components,

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addresses, usage of GPIOs, device handles, etc. This data is used by other application components to call the right device driver instances. o SJA1105SMBEVM utilities: sja1105smbevm_console.c contains some very simple functions for implementing a serial console. This is useful for debugging, and very simple visualization. It makes use of the UART configuration via ProcessorExpert (baud rate, etc.), and the UART2USB interface and the USB connector. o Callback functions for ENET and CAN: ProcessorExpert allows for some drivers to optionally configure callback functions in the application layer in specific situations, for example when errors occur or when data has been received or transmitted. Callback functions are called in the context of a device specific service task or from the interrupt context. Therefore, they should not perform time or stack consuming operations. In the example project, the ENET callback functions handle receiving ethernet packets. The PHY callbacks are for handling link detection changes and for auto-negotiation result processing. o ENET and CAN application. These SW modules contain code to initialize the proper device drivers, which in turn configure the devices, and to start tasks to maintain regular communication. The initialization and tasks are only started for specific rotary dial settings, see Table 7. o The general application module main.c does general initialization, and hardware plausibility tests, and starts the other application modules, depending on rotary dial settings. Periodic blinking the alive LED is also a task done in the main application module.

6.2 Code organization Fig 16 shows the source files of the example project as they are presented in S32DS:

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Fig 16. Organization of example project source code

From top to bottom: • Includes: system include files – provided by ProcessorExpert during project setup. • Generated Code: .h and .c files generated by ProcessorExpert, based on the interactive configuration with the GUI. For each SDK module, there are .c and .h files, containing data structure definitions, configuration data arrays, array dimensions, and more definitions in a form usable for the SDK device driver. The data structures must be passed to the driver’s initialization function. • ProjectSettings: essential files for producing an executable, like linker files (memory layout) and processor specific generic low-level files, like startup code after reset, interrupt vector table, etc. This code comes from the SDK, and is made available during project setup. • SDK: for each component configured in ProcessorExpert, its component source code (.c and .h files) is copied from the SDK distribution directory to this project specific

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directory. The files are compiled and linked to the executable. The SDK directory has some internal structure: o platform: devices contains more processor specific low-level code; drivers contains the device drivers used in this project; pal contains the abstraction modules. o rtos: contains the FreeRTOS source code; osif: contains an abstraction layer to allow to make use of alternative real time kernels without changing the application. • Sources: This is where the application code is located. There is the SJA1105PQRS device driver, the board specific modules in sja1105smbevm, the application modules and main.c • Debug_FLASH and/or Debug_RAM are directories, which contain everything, what the S32DS tools create during the project build phase, depending on which build configuration is active. • Project_Settings is a directory with links to the SDK installation directory.

6.3 Changing the static switch configuration stream Creating a new configuration for the SJA1105S switches requires a working installation of Python 2.7. For a Windows machine, we recommend Python-XY, available from https://python-xy.github.io/ Make sure the path of the Python package is contained in the %PATH% variable. These are the steps: 1. The configuration source files are in the project folder under Sources -> sja1105PQRS_driver -> configtools (see Fig 17). There is a naming convention, that the file name indicates at the end of the basename, if the configuration is for switchA or switchB. The MAC specific settings for swA and swB match the HW.

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Fig 17. Switch configuration files

2. There is • a minimalistic example “simple”, which is the one which is used in the example project firmware, • a more elaborate example “example” and • an example making use of the TSN features, like CBS, policer, MAC filtering for gPTP, etc. in “example_TSN”. • There are also some two examples “snake1” and “snake2”, which are identical to “simple” except they implement snake-like paths through the switches using loopback cables. They can be used for testing purposes. 3. Create a copy of one of the example configuration sources and rename it as desired. 4. Edit the copies of the configuration source files, modify them as desired and save them.

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5. Check the DOS .bat file “generate_config_cFile.bat” and add your newly created custom configuration source files at two locations: • Calling python to execute them • Using the .hex files created from the last step in the parameter list of the call to the converter.py utility, which generates the configStream.c source file. 6. Open cmd.com (DOS box) and navigate to the project’s subdirectory, where the config files are located. 7. Execute the batch script. A new version of NXP_SJA1105P_configStream.c is created, overwriting the old one. 8. Rebuild the project

6.4 Wakeup and Sleep The SJA1105SMBEVM hardware allows applications to send the board to sleep mode, and to get woken up either by a remote wakeup command received over one of the communication links, or by a local event, represented by a pushbutton. A simplified schematic is shown in Fig 18.

Fig 18. HW support for wakeup and sleep applications

During board sleep mode, most of the components are powered down, except the PHYs and the CAN transceiver, which use VBAT (or 12V0) to maintain some minor activity, but also shutting down the major part of the chip during sleep. Powering down the components is implemented by disabling the three switching power regulators for the 5V0, 3V3 and 2V5 power rails.

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Going to sleep starts in the PHYs and the Transceivers: if one of these receives a remote sleep request command via its communication interface, or a command from the µC to go to sleep, it releases its INH output to Low. Only when all have lowered their INH output, the Low level dominates and propagates over the diode and the jumper block to the EN pins of the switching voltage regulators. There is also a µC GPIO pin (Port-A 15), which works as an additional inhibit signal: When the PHYs and transceivers are ready for sleep, they not only release their INH signal, but also alert the µC via interrupt or via the control bus (SMI or SPI). Since the last PHY releasing the INH effectively switches the power off at the same time, there may be not enough time for the µC to complete housekeeping tasks before power is gone. Therefore, the µC can delay or inhibit power-off by setting the GPIO pin to High. Jumper block J6 allows to disable powering off the board with this mechanism, by connecting the switchers’ EN inputs directly to 12V0. This can be useful, if there is no SW support for wakeup/sleep, or for debugging, or for the first bring-up of the board. Waking the board may be triggered by a remote wakeup command received by one of the PHYs: Once the PHY detects the remote wakeup request, it puts the INH high again, which effectively switches on power again, and starts the boot process. Depending on the PHY configuration before being sent to sleep, the PHY may be configured to also wake the other PHYs via the WAKE line. PHYs woken by the WAKE line may be configured not only to raise their own INH line, but also send a wakeup telegram via the communication link to their peers. 7. Abbreviations

Table 8. Abbreviations Acronym Description 100BASE-T1 2-wire Ethernet standard μC Microcontroller ARP Address Resolution Protocol AVB Audio/Video Bridging (IEEE 802.1BA) CAN Controller Area Network – serial bus used in automotive applications CAN-FD CAN with Flexible Data rate – enhanced CAN standard CBS Credit based shaper DOS Very old operating system from Microsoft – some concepts are still used in modern MS Windows systems, e.g. the command window. EN Enable ENET Ethernet or Ethernet Controller FE Fast Ethernet – ethernet standard for copper cables – aka. IEEE 100BASE-TX. GDB GNU Debugger – a free SW debug tool. It defines a serial protocol which is used to connect the user interface on the PC with the target device to be debugged. Many USB connected debug probes implement the free GDB protocol. GPIO General Purpose Input Output GUI Graphical User Interface IC Integrated Circuit

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Acronym Description ICMP Internet Control Message Protocol INH Inhibit ISP In-System Programming JTAG Joint Test Action Group – Standard for accessing hardware via a serial protocol for testing after manufacturing; often also used for debugging software on embedded systems. LDO Low Drop Out (Voltage Regulator) LED Light Emitting Diode MAC Media Access Controller MISO, MOSI SPI data signals MII Media Independent Interface OnCE On-Chip Emulation: a Freescale (now NXP) standard for a debugging interface to embedded microcontrollers PHY Physical layer or chip responsible for adapting to the physical layer of a communication link RMII Reduced Media Independent Interface RGMII Reduced Gigabit Media Independent Interface S32DS Eclipse-based development environment for NXP microcontroller: S32 Design Studio SDK Software developer kit – set of libraries and tools to make embedded programming easier. SMI Serial Management Interface, a.k.a. Media Independent Interface Management SPI Serial Peripheral Interface – a synchronous serial communication interface SW Switching Voltage Regulator (“Switcher”) TSN Time Sensitive Networking TT Time-triggered UART Universal Asynchronous Receiver/Transmitter UTP Unshielded Twisted Pair – a standard for ethernet cables for e.g. 10BASE-T µC Microcontroller USB Universal Serial Bus

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8. Legal information

customer’s applications or products, or the application or use by customer’s 8.1 Definitions third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Draft — The document is a draft version only. The content is still under Semiconductors products in order to avoid a default of the applications and internal review and subject to formal approval, which may result in the products or of the application or use by customer’s third party modifications or additions. NXP Semiconductors does not give any customer(s). NXP does not accept any liability in this respect. representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences Export control — This document as well as the item(s) described herein of use of such information. may be subject to export control regulations. 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NXP Semiconductors takes no implied or statutory, including but not limited to the implied warranties of non- responsibility for the content in this document if provided by an information infringement, merchantability and fitness for a particular purpose. The entire source outside of NXP Semiconductors. risk as to the quality, or arising out of the use or performance, of this product In no event shall NXP Semiconductors be liable for any indirect, incidental, remains with customer. punitive, special or consequential damages (including - without limitation - In no event shall NXP Semiconductors, its affiliates or their suppliers be lost profits, lost savings, business interruption, costs related to the removal or liable to customer for any special, indirect, consequential, punitive or replacement of any products or rework charges) whether or not such incidental damages (including without limitation damages for loss of damages are based on tort (including negligence), warranty, breach of business, business interruption, loss of use, loss of data or information, and contract or any other legal theory. the like) arising out the use of or inability to use the product, whether or not Notwithstanding any damages that customer might incur for any reason based on tort (including negligence), strict liability, breach of contract, breach whatsoever, NXP Semiconductors’ aggregate and cumulative liability of warranty or any other theory, even if advised of the possibility of such towards customer for the products described herein shall be limited in damages. accordance with the Terms and conditions of commercial sale of NXP Notwithstanding any damages that customer might incur for any reason Semiconductors. whatsoever (including without limitation, all damages referenced above and Right to make changes — NXP Semiconductors reserves the right to make all direct or general damages), the entire liability of NXP Semiconductors, its changes to information published in this document, including without affiliates and their suppliers and customer’s exclusive remedy for all of the limitation specifications and product descriptions, at any time and without foregoing shall be limited to actual damages incurred by customer based on notice. This document supersedes and replaces all information supplied prior reasonable reliance up to the greater of the amount actually paid by to the publication hereof. customer for the product or five dollars (US$5.00). The foregoing limitations, exclusions and disclaimers shall apply to the maximum extent permitted by Suitability for use — NXP Semiconductors products are not designed, applicable law, even if any remedy fails of its essential purpose. authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected 8.3 Licenses to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for Purchase of NXP components inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these 8.4 Patents products are for illustrative purposes only. NXP Semiconductors makes no Notice is herewith given that the subject device uses one or more of the representation or warranty that such applications will be suitable for the following patents and that each of these patents may have corresponding specified use without further testing or modification. patents in other jurisdictions. Customers are responsible for the design and operation of their applications — owned by and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine 8.5 Trademarks whether the NXP Semiconductors product is suitable and fit for the Notice: All referenced brands, product names, service names and customer’s applications and products planned, as well as for the planned trademarks are property of their respective owners. application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks — is a trademark of NXP Semiconductors N.V. associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the

NXP Semiconductors AH1721 SJA1105SMBEVM UM

9. List of figures

Fig 1. SJA1105SMBEVM board ...... 3 Fig 2. Block diagram indicating the primary functional blocks and interconnections ...... 5 Fig 3. Power supply topology ...... 6 Fig 4. LEDs and Connectors ...... 9 Fig 5. S32DS installation packets for download ...... 13 Fig 6. S32DS installing SDK update – step 1 ...... 14 Fig 7. S32DS installing SDK update – step 2 ...... 15 Fig 8. S32DS installing SDK update – step 3 ...... 15 Fig 9. S32DS installing SDK update – step 4 ...... 16 Fig 10. Screenshot of a successfully created executable ...... 18 Fig 11. Screenshot of the debug configuration popup window part1 ...... 19 Fig 12. Screenshot of the debug configuration popup window part2 ...... 19 Fig 13. Screenshot of the debug configuration popup window part3 ...... 20 Fig 14. Screenshot of a debug session ...... 21 Fig 15. Software components and layers ...... 23 Fig 16. Organization of example project source code . 26 Fig 17. Switch configuration files...... 28 Fig 18. HW support for wakeup and sleep applications ...... 29

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10. List of tables

Table 1. SJA1105P/Q/R/S variants ...... 7 Table 2. Ethernet port usage and default PHY configurations ...... 8 Table 3. SJA1105SMBEVM LEDs overview ...... 9 Table 4. Jumper blocks and connectors ...... 10 Table 5. Pinning of the debug connector J10 ...... 12 Table 6. Buttons and switches ...... 12 Table 7. Rotary switch configuration in the example project ...... 12 Table 8. Abbreviations ...... 30

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11. Contents

1. Introduction ...... 3 2. Prerequisites ...... 3 3. System Overview ...... 4 4. Hardware Description ...... 6 4.1 Power ...... 6 4.2 MPC5748G Microcontroller ...... 6 4.3 SJA1105S switches ...... 7 4.4 TJA1102 PHYs for 100BASE-T1 ...... 8 4.5 PHYs for copper ethernet ...... 8 4.6 CAN interface ...... 8 4.7 LEDs ...... 9 4.8 Jumper blocks and connectors ...... 10 4.8.1 USB connector ...... 11 4.8.2 Software debug connector ...... 11 4.9 Buttons and switches ...... 12 5. Getting started ...... 12 5.1 Install S32DS ...... 13 5.2 Import example project files and build an executable file ...... 16 5.3 Download and run the firmware ...... 18 5.4 Example Software features ...... 22 6. Example project software ...... 23 6.1 Components and Layers ...... 23 6.2 Code organization ...... 25 6.3 Changing the static switch configuration stream ...... 27 6.4 Wakeup and Sleep ...... 29 7. Abbreviations ...... 30 8. Legal information ...... 32 8.1 Definitions ...... 32 8.2 Disclaimers...... 32 8.3 Licenses ...... 32 8.4 Patents ...... 32 8.5 Trademarks ...... 32 9. List of figures ...... 33 10. List of tables ...... 34 11. Contents ...... 35