AH1721 SJA1105SMBEVM User Manual Rev. 1.00 — 16 July 2018 User Manual Document information Info Content Keywords SJA1105PQRS, SJA1105S, SJA1105S Evaluation Board, SJA1105SMBEVM, Cascading, Ethernet, Wakeup, Sleep Abstract The SJA1105SMBEVM Evaluation Board is described in this document. NXP Semiconductors AH1721 SJA1105SMBEVM UM Revision history Rev Date Description 1.00 20180716 Release Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: mailto:[email protected] AH1721 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. User Manual Rev. 1.00 — 16 July 2018 2 of 35 NXP Semiconductors AH1721 SJA1105SMBEVM UM 1. Introduction The SJA1105SMBEVM (SJA1105S Mother Board Evaluation Module, see Fig 1) is designed for evaluating the capabilities of the SJA1105P/Q/R/S Automotive Ethernet switch family and the TJA1102 Automotive Ethernet PHYs, by developing and running customer software. Therefore, the board features the MPC5748G MCU with a rich set of peripherals for communication and automotive applications. It is designed to allow early adaptions of applications, like a X-to-Ethernet gateway, communication hub, etc. Fig 1. SJA1105SMBEVM board This user manual describes the board hardware and the software development environment to allow the user to quickly bring up a working system and to pave the way towards an own customized software, and in the end towards an all custom system. After the HW description the manual walks the user through the process to create the factory firmware starting at the supplied example project and describes the recommended SW development environment S32 Design Studio for Power as far as it is needed for the example project. 2. Prerequisites Besides this document and the hardware package you will need the following support material - consult https://www.docstore.nxp.com and https://www.nxp.com SJA1105PQRS User Manual (UM11040) SJA1105PQRS Data sheet SJA1105PQRS Application Hint (AH1704) TJA1102 Datasheet AH1721 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. User Manual Rev. 1.00 — 16 July 2018 3 of 35 NXP Semiconductors AH1721 SJA1105SMBEVM UM TJA1102 Application Hint (AH1508) SJA1105S Evaluation Board Software Package TJA1145FD CAN-Transceiver Product data sheet and Application Hint (AH1309) MPC5748G reference manual If you want to download and run SW on the SJA1105SMBEVM you also need a JTAG- Debug adapter. The easiest solution is the PEMicro “USB Multilink Universal” USB-to- JTAG debug probe (http://www.pemicro.com/products/product_viewDetails.cfm?product_id=15320168), as this is already integrated in the S32 Design Studio IDE. 3. System Overview AH1721 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. User Manual Rev. 1.00 — 16 July 2018 4 of 35 NXP Semiconductors AH1721 SJA1105SMBEVM UM Fig 2. Block diagram indicating the primary functional blocks and interconnections The primary functional components of the SJA1105SMBEVM Evaluation Module are: • 1 Microcontroller MPC5748G • 2 switches SJA1105S: ETH-SW(A) and ETH-SW(B) • 3 100BASE-T1 PHYs: ETH-PHY TJA1102 (2*) + TJA1102S • 2 1000BASE-T PHYs: 1G PHY KSZ9031 • 1 100BASE-TX PHY; FE PHY DP83848C • 1 CAN Transceiver TJA1145FD • 1 UART-USB-Converter FT230XQ The main Ethernet data paths are: AH1721 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. User Manual Rev. 1.00 — 16 July 2018 5 of 35 NXP Semiconductors AH1721 SJA1105SMBEVM UM • Switch-A and Switch-B can exchange ethernet data via a SGMII connection at 1GBps. • Port0 of the MPC5748G is wired to Switch-A Port0 using MII-Lite at 100MBps. • The FE-PHY is directly connected to MPC5748G’s Port1, also with MII-Lite. • The 1G-PHYs are connected to Switch-A’s ports 2 and 3. These links support speed autonegotiation, but not direction autonegotiation. The actual link speed depends on the result of the autonegotiation process. 4. Hardware Description 4.1 Power The SJA1105SMBEVM is powered by a single 12 Volt input. It is advised to use an adapter that can deliver at least 1 Amp for covering startup current peaks and full-load situations. The nominal current is ~350mA@12V and depends on the number of active PHYs, and if the port is connected to a peer. Fig 3. Power supply topology The power supply topology is shown in Fig 3. The switching regulators for 5V0, 3V3 and 2V5 are controlled by the signal VREG_EN, which can be either fixed to “enable” or controlled by a combination of an output signal from the PHYs and some sign-off signal from the CPU. The selection is done with a jumper (J6). With this schema, most of the board can be switched off when entering sleep mode. For more details see chapter 6.4. 4.2 MPC5748G Microcontroller The microcontroller runs the user’s software, which controls all components on the board, e.g. switches, PHYs, LEDs, etc. It also has an ethernet connection to the switches, so it can receive and send ethernet packets. Therefore, the microcontroller can work as a host controller for protocols like gPTP, where the software works in conjunction with hardware features implemented in the switches. which are only partly implemented in the switches, and need SW assistance. The MPC5748G features: • 2 e200Z4 32bit cores with 160MHz and 8k I-cache + 4k D-cache AH1721 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. User Manual Rev. 1.00 — 16 July 2018 6 of 35 NXP Semiconductors AH1721 SJA1105SMBEVM UM • 1 e200Z2 32bit core with 80MHz • 6MB on-chip flash and 768kB internal RAM • 2 independent 100Mbps ethernet ports with AVB and 1588 support • 6 SPI, 18 LIN/UART, 8 CAN (with FD support), 4 I2C and USB peripheral blocks • Standard microcontroller infrastructure, like interrupt controller, DMA, timer, watchdog, JTAG debug interface, etc. For making the task to create user’s software easier, there is an example project, which initializes all peripherals on the SJA1105SMBEVM and implements basic functions, like communicating via the USB-UART adapter, configuring the PHYs and switches, sending and receiving ethernet packets, sending and receiving CAN frames, dealing with PHY plug events, etc. This example project serves as a foundation for user extensions for specific applications. The SW development environment and the example project is described in chapter 6. 4.3 SJA1105S switches The SJA1105S is an IEEE 802.3-compliant 5-port automotive Ethernet switch supporting Audio Video Bridging (AVB) and Time-Sensitive Networking (TSN) standards. It is a member of the SJA1105P/Q/R/S family of switches: Table 1. SJA1105P/Q/R/S variants Device SGMII interface TT-Ethernet and TSN-Ethernet SJA1105P No No SJA1105Q No Yes SJA1105R Yes No SJA1105S Yes Yes The SJA1105S’s fifth port is a SGMII-only port and is capable to operate at up to 1Gbps. The other four ports can be individually configured to operate at 10Mbps, 100Mbps or 1Gbps, depending on the capability and configuration of the PHY connected. Interfacing a PHY to one of these four ports can be done using one of the 3 supported MII interface standards: MII, RMII or RGMII. This port arrangement provides the flexibility to connect a mix of PHY devices such as the TJA110x 100BASE-T1 PHYs from NXP Semiconductors and other commercially available Fast Ethernet and Gigabit Ethernet PHYs, or fiber optic PHYs. The high-speed interface makes it easy to cascade multiple switches of the SJA1105 family for scalability. It can be used in various automotive scenarios such as gateway applications, body domain controllers or for interconnecting multiple ECUs in a daisy chain. Full Audio Video Bridging (AVB) support means that the SJA1105 family can be used in infotainment and driver assistance systems. Time-triggered Ethernet and Time-Sensitive Networking support with IEEE 802.1Qbv time-aware traffic shaping and IEEE 802.1Qci per-stream policing makes the SJA1105 family usable in applications with hard realtime communication requirements. In the SJA1105SMBEVM design, the switches are used in a cascaded topology: the SGMII ports are connected to create a high-speed link for forwarding payload ethernet frames and management data frames. Cascading also includes HW provisions to synchronize the PTP clock counter by using a master/slave clock configuration. The usage of the switches’ ports is shown in Table 2. AH1721 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. User Manual Rev. 1.00 — 16 July 2018 7 of 35 NXP Semiconductors AH1721 SJA1105SMBEVM UM 4.4 TJA1102 PHYs for 100BASE-T1 The TJA1102 is an OPEN Alliance 100BASE-T1 compliant Dual Ethernet PHY optimized for automotive use cases. The device provides 100Mbit/s transmit and receive capability over a single Unshielded Twisted Pair (UTP) cable, supporting a cable length of up to at least 15 m. Optimized for automotive use cases such as IP camera links, driver assistance systems and back-bone networks, the TJA1102 has been designed to minimize power consumption and system costs, while still providing the robustness required for automotive use cases. The default configuration of the TJA1102 PHYs on the SJA1105S Evaluation Module are detailed in Table 2, together with the interconnection