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EC 413 Computer Organization EC 413 Computer Organization CPU Design Summary Prof. Michel A. Kinsy Department of Electrical & Computer Engineering Transistors § MOS - Metal-Oxide Semiconductor § MOS transistors have three terminals: drain, gate, and source § A transistor acts as switches: § If the voltage on the gate terminal is higher/lower than the source terminal then a conducting path will be established between the drain and source terminals G G S D S D n-channel p-channel Department of Electrical & Computer Engineering Transistors Vdd § CMOS - Complementary MOS § Transistors are the primary components of ICs I O § An integrated circuit (IC) or a chip is made up of transistors (these days Vss billions) and other electronic components § ICs are the building blocks of computers (CPU, bus interface, memory management unit) Department of Electrical & Computer Engineering 1 Volume I: RISC-V User-Level ISA V2.2 11 2.2 Base Instruction Formats In the base ISA, there are four core instruction formats (R/I/S/U), as shown in Figure 2.2. All are a fixed 32 bits in lengthBase and must Instruction be aligned on a four-byte Formats boundary in memory. An instruction address misaligned exception is generated on a taken branch or unconditional jump if the target address§ is not four-byte aligned. No instruction fetch misaligned exception is generated for a conditionalThe branch base that isRISC-V not taken. ISA has four main instruction formats The alignment§ R, I, constraint S and forU types base ISA instructions is relaxed to a two-byte boundary when instruction extensions with 16-bit lengths or other odd multiples of 16-bit lengths are added. 31 25 24 20 19 15 14 12 11 7 6 0 funct7 rs2 rs1 funct3 rd opcode R-type imm[11:0] rs1 funct3 rd opcode I-type imm[11:5] rs2 rs1 funct3 imm[4:0] opcode S-type imm[31:12] rd opcode U-type Figure 2.2: RISC-V base instruction formats. Each immediate subfield is labeled with the bit position (imm[x ]) in the immediate value being produced, rather than the bit position within the instruction’s immediateDepartment field asof isElectrical usually done.& Computer Engineering The RISC-V ISA keeps the source (rs1 and rs2) and destination (rd) registers at the same position in all formats to simplify decoding. Except for the 5-bit immediates used in CSR instructions (Section 2.8), immediates are always sign-extended, and are generally packed towards the leftmost available bits in the instruction and have been allocated to reduce hardware complexity. In partic- ular, the sign bit for all immediates is always in bit 31 of the instruction to speed sign-extension circuitry. Decoding register specifiers is usually on the critical paths in implementations, and so the in- struction format was chosen to keep all register specifiers at the same position in all formats at the expense of having to move immediate bits across formats (a property shared with RISC-IV aka. SPUR [18]). In practice, most immediates are either small or require all XLEN bits. We chose an asym- metric immediateCentral split (12 bitsProcessing in regular instructions plus Unit a special load(CPU) upper immediate in- struction with 20 bits) to increase the opcode space available for regular instructions. Immediates are sign-extended because we did not observe a benefit to using zero-extension §for someCentral immediates Processing as in the MIPS ISA Unit and wanted(CPU) to keep Organization the ISA as simple as possible. § CPU = Control Unit + ALU + Registers 2.3 Immediate§ Control Encoding Unit: monitors Variants and directs sequences of instructions There are a§ further ALU two (Arithmetic-Logic variants of the instruction Unit): formats performs (B/J) based arithmetic on the handling of imme- diates, as shown in Figure 2.3. and logical operations Department of Electrical & Computer Engineering Central Processing Unit (CPU) § Central Processing Unit (CPU) Fetch Instruction Organization § CPU Execution Process Decode Increment PC 1. Fetch Instruction Read registers 2. Decode Instruction ALU Operation 3. Execute Operation Or Branch Address 4. Memory Operation 5. Register Writeback Operation Data Memory Operation Write Back Department of Electrical & Computer Engineering 2 Single Cycle RISC-V CPU 1 PC[31-20] 0 0 ADD 1 Instr[31-12] ADD 4 Shift left 1 PCSrc ALUOp Jump Branch MemRead Control MemtoReg Unit MemWrite ALUSrc Instr[31-21] RegWrite Overflow Instr[19-15] Read Addr 1 zero Read Instruction Instr[24-20] Data 1 Memory Read Addr 2 Read PC Inst[31-0] Register File Address Read Data Address ALU 1 Instr[11-7] Write Addr Read 0 Data Data 2 Memory 0 Write Data 1 Write Data Sign Extend ALU 12 | 20 32 Control Instr[30, 14-12] Department of Electrical & Computer Engineering Central Processing Unit (CPU) § Central Processing Unit (CPU) Fetch Instruction Organization § CPU Execution Process Decode Increment PC 1. Fetch Instruction Read registers § Read IM[PC] ALU Operation Or Branch Address Data Memory Operation Write Back Department of Electrical & Computer Engineering Execute Operation § The Arithmetic Logic Unit (ALU) is at the center of the CPU operation execution § ALU operation is based on instruction type and function code § Performs subtraction for branches (beq) § Performs no operation for jumps § Performs the operation is specified by the function field for R-type instructions § ALU Control unit will have the following inputs: § 3-bit control field called ALUOp § Funct3 and funct7 function fields Department of Electrical & Computer Engineering 3 Memory Operation § For RISC-V Load and Store are the only two memory instructions § Recall: § RISC-V does not support memory to memory data processing operations § Data values must be moved into registers before using them § The basic load and store instructions are Load and Store Word or Byte § lw/lb rd, offset(rs1) § sw/sb rs2, offset(rs1) Department of Electrical & Computer Engineering CPU Instruction Execution Stages Stage R-Type Memory Reference Branches Jumps Instruction(Inst) [31:0] ß Memory[PC] Instruction Fetch PC ß PC + 4 Read1 ß Reg. File[Inst[19:15]] Instruction Decode Read2 ß Reg. File[Inst[24:20]] ALU_Result ßPC + (sign-extend(Inst[11:0]) << 1) If PC ß ………… ALU_Result ßRead1 ALU_Result ßA + sign- (Read1==Read2) {PC[31:28], Execution Operation Op Read2 extend(Inst[15:0]) PC ß ALU_Result extend(Inst[20:0])} Load Memory ß ALU_Result Memory Access Store Memory[ALU_Result ] ß Read2 Load Reg. File[Inst[11:07]] ß ß Register Writeback ALU_Result Reg[Inst[11:07]] Memory[ALU_Result ] Department of Electrical & Computer Engineering 5-Stage RISC-V Pipelining Instruction Instruction Decode Execute Memory WriteBack Fetch Instruction Instruction Execute Memory Writeback Fetch Decode Department of Electrical & Computer Engineering 4 Multi-Stage RISC-V CPU PCSrc 1 0 ADD Shift left 1 ALUOp Branch MemRead ADD Control MemtoReg Unit MemWrite ALUSrc 4 RegWrite Instr[31-21] Overflow Instr[19-15] Read Addr 1 zero Read Instruction Data 1 Memory Instr[24-20] Read Addr 2 Read PC Inst[31-0] Register File ALU Address Read Data 1 Address Instr[11-7] Write Addr Read 0 Data Data 2 Memory 0 Write Data 1 Write Data RegWrite Sign Extend ALU 12 | 20 32 Control Instr[30, 14-12] Department of Electrical & Computer Engineering Instruction Interactions § An instruction in the pipeline may need a resource being used by another instruction in the pipeline § Structural hazard § An instruction may depend on something produced by an earlier instruction § Dependence may be for a data calculation § Data hazard § Dependence may be for calculating the next address § Control hazard (branches, interrupts) Department of Electrical & Computer Engineering Resolving Data Hazards § Strategy 1: Wait for the result to be available by freezing earlier pipeline stages § Interlocks § Strategy 2: Route data as soon as possible after it is calculated to the earlier pipeline stage § Bypass Department of Electrical & Computer Engineering 5 Resolving Data Hazards § Strategy 3: Speculate on the dependence § Two cases: § Guessed correctly § Do nothing § Guessed incorrectly § Kill and restart Department of Electrical & Computer Engineering Source and Destination Registers 7 5 5 3 5 7 R-type funct7 rs2 rs1 funct3 rd opcode I-type imm[11:0] rs1 funct3 rd opcode S-type imm[11:5] rs2 rs1 funct3 imm[4:0] opcode SB-type imm[12] imm[10:5] rs2 rs1 funct3 imm[4:1-11] opcode U-type imm[31:12] rd opcode UJ-type imm[20] imm[10:1] imm[11] imm[19:12] rd opcode source(s) destination ALU rd ß (rs1) [func3,func7] (rs2) rs1, rs2 rd ALUi rd ß (rs1) [func3] I-imm rs1 rd rd ß (rs1) [funct3, inst[30]] I-imm[4:0] rs1 rd Department of Electrical & Computer Engineering Source and Destination Registers 7 5 5 3 5 7 R-type funct7 rs2 rs1 funct3 rd opcode I-type imm[11:0] rs1 funct3 rd opcode S-type imm[11:5] rs2 rs1 funct3 imm[4:0] opcode SB-type imm[12] imm[10:5] rs2 rs1 funct3 imm[4:1-11] opcode U-type imm[31:12] rd opcode UJ-type imm[20] imm[10:1] imm[11] imm[19:12] rd opcode source(s) destination ALU rd ß (rs1) [func3,func7] (rs2) rs1, rs2 rd ALUi rd ß (rs1) [func3] I-imm rs1 rd rd ß (rs1) [funct3, inst[30]] I-imm[4:0] rs1 rd LW rd ß M [(rs1) + imm] rs1 rd SW M [(rs1) + imm] ß (rs2) rs1, rs2 LUI rd ß U-imm rd AUIPC rd ß pc + U-imm rd Department of Electrical & Computer Engineering 6 Source and Destination Registers source(s) destination ALU rd ß (rs1) [func3,func7] (rs2) rs1, rs2 rd ALUi rd ß (rs1) [func3] I-imm rs1 rd rd ß (rs1) [funct3, inst[30]] I-imm[4:0] rs1 rd LW rd ß M [(rs1) + imm] rs1 rd SW M [(rs1) + imm] ß (rs2) rs1, rs2 LUI rd ß U-imm rd AUIPC rd ß pc + U-imm rd JAL rd ß pc + 4 rd pc ß pc + J-imm
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