Combinational Logic

COMBINATIONAL LOGIC

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 Overview

Static CMOS Conventional Static CMOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic CMOS Logic Domino np-CMOS

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 Combinational vs. Sequential Logic

Out Logic In Logic In Out Circuit Circuit

State

(a) Combinational (b) Sequential

Output = f(In) Output = f(In, Previous In)

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 Static CMOS Circuit

At every point in time (except during the switching transients) each gate output is connected to either VDD or Vss via a low-resistive path. The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes.

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 Static CMOS

VDD

In1 In2 PUN PMOS Only In3

F = G

In1 In2 PDN NMOS Only In3

VSS

PUN and PDN are Dual Networks

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 NMOS Transistors in Series/Parallel Connection

Transistors can be thought as a switch controlled by its gate signal NMOS switch closes when switch control input is high

A B

X Y Y = X if A and B

B Y = X if A OR B X Y

NMOS Transistors pass a “strong” 0 but a “weak” 1

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 PMOS Transistors in Series/Parallel Connection

PMOS switch closes when switch control input is low

A B

X Y Y = X if A AND B = A + B A

X B Y = X if A OR B = AB Y

PMOS Transistors pass a “strong” 1 but a “weak” 0 Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 Complementary CMOS Logic Style Construction (cont.)

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 Example Gate: NAND

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 Example Gate: NOR

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 Example Gate: COMPLEX CMOS GATE

VDD

B A C

D OUT = D + A• (B+C) A D B C

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 4-input NAND Gate

Vdd VDD

In1 In2 In3 In4 Out In1

In2

Out In3

In4

GND

In1 In2 In3 In4

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 Standard Cell Layout Methodology

metal1 VDD

Well

VSS Routing Channel signals polysilicon

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 Two Versions of (a+b).c

VDD VDD

x x

GND GND

a c b a b c

(a) Input order {a c b} (b) Input order {a b c}

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 Logic Graph

VDD x b PUN

j c c a i x VDD x b j a c i PDN GND a b

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 Consistent Euler Path

i x VDD

b a j

GND

{ a b c}

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 Example: x = ab+cd

x x

b c b c

x VDD x VDD

a d a d

GND GND

(a) Logic graphs for (ab+cd) (b) Euler Paths {a b c d}

VDD

GND a b c d (c) stick diagram for ordering {a b c d}

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 Properties of Complementary CMOS Gates

High noise margins:

VOH and VOL are at VDD and GND, respectively. No static power consumption:

There never exists a direct path between VDD and VSS (GND) in steady-state mode. Comparable rise and fall times: (under the appropriate scaling conditions)

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 Properties of Complementary CMOS Gates

High noise margins:

VOH and VOL are at VDD and GND, respectively. No static power consumption:

There never exists a direct path between VDD and VSS (GND) in steady-state mode. Comparable rise and fall times: (under the appropriate scaling conditions)

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 Transistor Sizing

• for symmetrical response (dc, ac) • for performance

VDD

B 12 A 6 Input Dependent C 12 Focus on worst-case D 6 F A 2 D 1 B 2 C 2

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 Propagation Delay Analysis - The Switch Model

RON =

VDD VDD VDD Rp Rp Rp Rp A B B A F R Rp n C F L A R B n F CL Rn Rn Rn A CL A A B

(a) Inverter (b) 2-input NAND (c) 2-input NOR

tp = 0.69 Ron CL

(assuming that CL dominates!)

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 What is the Value of Ron?

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 Numerical Examples of Resistances for 1.2mm CMOS

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 Analysis of Propagation Delay

V DD 1. Assume Rn=Rp= resistance of minimum sized NMOS inverter Rp Rp 2. Determine “Worst Case Input” transition A B F (Delay depends on input values) Rn CL 3. Example: tpLH for 2input NAND B - Worst case when only ONE PMOS Pulls up the output node R n - For 2 PMOS devices in parallel, the resistance is lower A tpLH = 0.69RpCL 2-input NAND 4. Example: tpHL for 2input NAND - Worst case : TWO NMOS in series

tpHL = 0.69(2Rn)CL

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 Design for Worst Case

VDD VDD 1 1 B 4 2 A B A F C 4 2 CL B D 2 F 2 A 2 1 A D B 2 C 2

Here it is assumed that Rp = Rn

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 Influence of Fan-In and Fan-Out on Delay

VDD

A B C D Fan-Out: Number of Gates Connected 2 Gate Capacitances per Fan-Out

A B FanIn: Quadratic Term due to: C 1. Resistance Increasing D 2. Capacitance Increasing (tpHL)

2 tp = a1FI+a2FI + a3FO

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 tp as a function of Fan-In

4.0

tpHL 3.0 ) c e

s 2.0 quadratic tp n (

p t 1.0 t linear pLH

0.0 1 3 5 7 9 fan-in

AVOID LARGE FAN-IN GATES! (Typically not more than FI < 4)

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 Fast Complex Gate - Design Techniques

• Transistor Sizing: As long as Fan-out Capacitance dominates • Progressive Sizing:

Out

InN MN CL M1 > M2 > M3 > MN

C3 In3 M3 Distributed RC-line C In2 M2 2

In M1 C1 1 Can Reduce Delay with more than 30%!

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 Fast Complex Gate - Design Techniques (2)

• Transistor Ordering

critical path critical path

C In L CL 3 M3 In1 M1

C In M2 2 C2 2 In2 M2

In 1 C1 C 1 M In3 M3 3

(a) (b)

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 Fast Complex Gate - Design Techniques (3)

• Improved Logic Design

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 Fast Complex Gate - Design Techniques (4)

• Buffering: Isolate Fan-in from Fan-out

C CL L

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 Example: Full Adder

V DD VDD C i A B A B A B

Ci B V A DD X Ci Ci A S

Ci A B B VDD

A B Ci A

C o B

Co = AB + Ci(A+B) 28 transistors

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 A Revised Adder Circuit

VDD

VDD VDD A

A B B A B Ci B Kill "0"-Propagate A Ci Co Ci S

A Ci "1"-Propagate Generate

A B B A B Ci A

24 transistors

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 Ratioed Logic

VDD VDD VDD

Resistive Depletion PMOS Load RL Load VT < 0 Load VSS F F F In1 In1 In1 In2 PDN In2 PDN In2 PDN In3 In3 In3

VSS VSS VSS (a) resistive load (b) depletion load NMOS (c) pseudo-NMOS

Goal: to reduce the number of devices over complementary CMOS

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 Ratioed Logic

VDD

• N transistors + Load Resistive Load • VOH = VDD RL

• VOL = RPN

F RPN + RL

In1 • Assymetrical response In2 PDN In3 • Static power consumption

• tpL= 0.69 RLCL VSS

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 Active Loads

VDD VDD

Depletion PMOS Load VT < 0 Load

VSS F F

In1 In1 In2 PDN In2 PDN In3 In3

VSS VSS depletion load NMOS pseudo-NMOS

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 Load Lines of Ratioed Gates

1 Current source

) 0.75 d e z i l a

m Pseudo-NMOS r 0.5 o N ( L I Depletion load 0.25 Resistive load

0 0.0 1.0 2.0 3.0 4.0 5.0 Vout (V)

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 Pseudo-NMOS

VDD

F C A B C D L

VOH = VDD (similar to complementary CMOS)

2 æV ö k 2 – – OL p – knç(VDD VTn)VOL ------÷ = ------(VDD VTp ) è2 ø 2

kp V =(V – V ) 1– 1 – ------(assumingthatV =V = V ) OL DD T k T Tn Tp n

SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 Pseudo-NMOS NAND Gate

VDD

GND

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 Improved Loads

VDD

M1 Enable M2 M1 >> M2

CL A B C D

Adaptive Load

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 Improved Loads (2)

VDD VDD

M1 M2

Out Out

A A PDN1 PDN2 B B

VSS VSS

Dual Cascode Voltage Switch Logic (DCVSL)

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 Example

Out

B B B B

A A

XOR-NXOR gate

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 Pass-Transistor Logic

Switch Out A s

t Out u p

n Network B I B

• N transistors • No static consumption

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 NMOS-only switch

C = 5 V C = 5 V

M2 A = 5 V A = 5 V B M B n

CL M1

VB does not pull up to 5V, but 5V - VTN

Threshold voltage loss causes static power consumption

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 Solution 1: Transmission Gate

C C

A B A B

C C

C = 5 V A = 5 V B

CL C = 0 V

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 Resistance of Transmission Gate

30000.0

(W/L)p=(W/L)n = 1.8/1.2 20000.0 ) m

h Rp O (

R 10000.0 Req

0.0 0.0 1.0 2.0 3.0 4.0 5.0 Vout

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 Pass-Transistor Based Multiplexer

S S

VDD

V S DD

A M2

S F

M1 B

GND

In1 S S In2

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 Transmission Gate XOR

B M2

A A F

M1 M3/M4 B

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 Delay in Transmission Gate Networks

5 5 5 5 V V V V V V In 1 i-1 i i+1 n-1 n

C C C 0 0 C 0 C 0

(a)

Req Req Req Req V1 Vi V Vn-1 V In i+1 n

C C C C C

(b) m

Req Req Req Req Req Req In C C C C C C C C

Vin R1 1 R2 2 Ri-1 i-1 Ri i RN N

C1 C2 Ci-1 Ci CN

Assume All internal nodes are precharged to VDD and a step voltage is applied at the input Vin

N N N i =R C = C R tN å i å j å i å j i= 1 j= i i= 1 j= 1

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 Delay Optimization

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 Transmission Gate Full Adder

P VDD V C DD A i P S Sum Generation A A P Ci A P V B B DD V A DD P P CoCarry Generation

Ci Ci Ci A Setup P

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 (2) NMOS Only Logic: Level Restoring Transistor

VDD Level Restorer VDD Mr B M2 X A Mn Out

• Advantage: Full Swing • Disadvantage: More Complex, Larger Capacitance • Other approaches: reduced threshold NMOS

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995 Level Restoring Transistor

with 5.0 5.0

) without V

( without 3.0 t 3.0 X

u with o V V V 1.0 B 1.0

-1.00 2 4 6 -1.00 2 4 6 t (nsec) t (nsec) (a) Output node (b) Intermediate node X

VT=0

VDD

VDD 0V 5V

Out VDD 0V

WATCH OUT FOR LEAKAGE CURRENTS

A Pass-Transistor A F B Network B (a)

A Inverse A Pass-Transistor F B B Network

B B B B B B

A A A

B F=AB B F=A+B A F=AÅBÝ (b) A A A

B F=AB B F=A+B A F=AÅBÝ

AND/NAND OR/NOR EXOR/NEXOR

VDD VDD

f Mp f Me Out

In1 CL In1 In2 PUN In2 PDN In3 In3 Out

CL f Me f Mp

fn network fp network • Precharge 2 phase operation: • Evaluation

VDD

M f p • N + 1 Transistors Out • Ratioless

• No Static Power Consumption A • Noise Margins small (NML) C • Requires Clock B

f Me

6.0

f Vout

4.0

) PRECHARGE t EVALUATION l o V (

t u o V 2.0

0.0 0.00e+00 2.00e-09 4.00e-09 6.00e-09 t (nsec)

VDD

Out

In1

In2

In3

In4

f GND

VDD f

f Mp Out (1) CL A t precharge (2) Vout evaluate

f Me

t (a) Leakage sources (b) Effect on waveforms

Minimum Clock Frequency: > 1 MHz

VDD case 1) if DVout < VTn

f Mp C V = C V t + C V – V V L DD L out () a(DD Tn(X)) Out or C CL a DV =V (t) – V = –------(V – V (V )) A Ma out out DD C DD Tn X X L

Ca B = 0 Mb case 2) if DVout > VTn C æa ö Cb DV = –V ------out DDçC + C ÷ f Me èa Lø

V VDD DD

M M f f Mp Mbl f p bl Out Out A M A Ma a

B Mb B Mb

f M f Me e

(a) Static bleeder (b) Precharge of internal nodes

VDD

M could potentially forward f p bias the diode Out

CL 5V A Ma f X

Ca B Mb overshoot

Cb out f Me

output without redistribution (Ma off) h

g 6 u o r h t d e e

f out 4

) f t l

o internal node in PDN V (

V 2

0 0 1 2 3 t (nsec)

VDD VDD V f

f Mp f Mp In Out1 Out2

Out1 In VTn

Out2 DV

f Me f Me t

(a) (b)

Only 0®1 Transitions allowed at inputs!

VDD VDD VDD

f M f M p p M Out1 r

Out2

In1 Static Inverter PDN In2 In4 PDN with Level Restorer In3

f Me f Me

• Only non-inverting logic

• Very fast - Only 1->0 transitions at input of inverter

move VM upwards by increasing PMOS

• Adding level restorer reduces leakage and charge redistribution problems

• Optimize inverter for fan-out

V DD VDD

f Mp f M Out1 e

In1 PUN In2 PDN In4 In3 Out2

Me f f Mp

Only 1®0 transitions allowed at inputs of PUN

VDD VDD VDD VDD f f f f S1 Ci1 A B1 B1 1 A1 A B1 Ci1 1 A 1 B f 1 f f Ci2 f

VDD VDD VDD f f f B0 A0 Ci1 A0 B0 Ci0 A0 A0 B0 B0 Ci0 S0 f f f Ci0 Carry Path

VDD Total Area: 225 mm ´ 48.6 mm f 0.5

P0 P1 P2 P3 P4 M0 M1 M2 M3 M4 3 2.5 2 1.5 1 C Ci,0 3.5 3 2.5 2 1.5 1 o,4 G0 G1 G2 G3 G4

4 3.5 3 2.5 2 f 1.5