DPLL) Using Pipelined Carrier Synthesis Techniques

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ISSN: 2278 – 909X International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE) Volume 2, Issue 1, January 2013 High speed all digital phase locked loop (DPLL) using pipelined carrier synthesis techniques

T.Kranthi Kiran, Dr.PS.Sarma

 polynomial approximation, e.g. Taylor series. But it requires Abstract— DPLLs are used widely in communications a considerable amount of hardware space on the silicon systems like radio, telecommunications, computers and other substrate. Interpolation method using table look-up may be electronic applications. Digital PLLs are a type of PLL used to the other solution. But it also requires large number of gates synchronize digital signals. While DPLLs input and outputs are and ROM memory. The CORDIC offers the opportunity to typically all digital, they do have internal functions which are calculate the desired functions in a simple and efficient way. dependent on analog signals. This project deals with the design Due to the simplicity of the involved operations, the of pipelined architecture for coordinate rotation algorithm for the computation of loop performance of complex Digital Phase CORDIC realization of complex DPLL is very well suited in Locked Loop (DPLL). For on-chip application, the area VLSI hardware design and its implementation. This paper reduction in proposed design can is achieved through first describes the CORDIC algorithm and then pipelined optimization in the number of micro rotations. For better loop architecture design [7]. Thereafter, implementation with performance of second order complex DPLL and to minimize adjustment of micro- rotation has been described. Finally quantization error, the numbers of iterations are also CORDIC realization of a complex phase locked loop is optimized. Modelsim Xilinx Edition (MXE) and Xilinx ISE will described. be used simulation and synthesis respectively. The Xilinx Chipscope tool will be used to test the FPGA inside results while the logic running on FPGA. The Xilinx Spartan 3 Family FPGA development board will be used this project.

Index Terms—CORDIC, Digital Signal Processing, Pipelined II. CORDIC ALGORITHM Architecture, DPLL, Micro-rotation, Loop performance. The Volder’s CORDIC algorithm [1] is derived from the general equations of vector rotation. The theory of CORDIC computation is to decompose the desired rotation angle into I. INTRODUCTION the weighted sum of a set of predefined elementary rotation CORDIC algorithm was first developed by Jack E. Volder in angles. Each of them can be accomplished with simple shift 1959 [1]. CORDIC algorithm is extremely useful in efficient add operation for a desired rotational angle θ. It can be T and effective implementation of DSP systems [2]. This represented for M iterations of an input vector (x,y) setting algorithm allows implementation of trigonometric functions initial conditions: x0=x, y0=y,and z0= θ as like sine, cosine, magnitude and phase with great precision by using just simple shift and adding operations [1-4]. Although the same functions can be implemented using multipliers, variable shift registers or Multiply Accumulator (MAC) units, but CORDIC can implement these functions If zf=0 holds, then efficiently while saving enough silicon area which is considered to be primary design criteria in VLSI technology. This paper designs first order complex DPLL using CORDIC which functions as a FSK demodulator [6]. In digital PLL, an adjustable local sine wave generator and phase detector is required. The sine and cosine terms can be calculated using i.e. the total accumulated rotation angle is equal to θ.

δi , 0 ≤ 1≤ M-1denote a sequence of ±1s that determine the direction of each elementary rotation. When M is the total Manuscript received jan2, 2013. number of elementary rotation angles, i-th angle αi is given T.Kranthi Kiran, M.Tech VLSI-SD, Aurora Technological and Research Institute, JNTUH, Hyderabad, India, Mobile No:9704481664 Dr.PS.Sarma, professor of ECE Department & Dean of Academics , Aurora Technological and Research Institute, JNTUH, Hyderabad, India, Mobile No:9490755593.

11 All Rights Reserved © 2012 IJARECE ISSN: 2278 – 909X International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE) Volume 2, Issue 1, January 2013 by: CORDIC architecture [4] only adder/ subtractor is used. The shift operations are hardwired using permanent oblique bus -i connections to perform multiplications by 2 . The precomputed values, as given in Table I, of i-th iteration angle αi required at each module is stored at a ROM memory location. The delay is adjusted by using proper bit-length in the shift register. Since no sign detection is needed to force where m=0, 1 and -1 correspond to the rotation operation in zf=0, the carry save adders are well suited in this architecture. linear, circular, and hyperbolic coordinate system The use of these adders reduces the stage delay significantly. respectively. For a given value of θ, the CORDIC iteration is With the pipelining architecture, the propagation delay of the given by: multiplier is the total delay of a single adder. So ultimately the throughput of the architecture is increased to many folds as the throughput is given by: ―1/(delay due to a single adder)‖. If an iterative implementation of the CORDIC is

-1 -i used, the processor would take several clock cycles to give where α i = tan 2 . In case of counter clockwise rotation of a vector, the recursively updated equations are output for a given input. But in the pipelined architecture, each pipeline stage takes exactly one clock cycle to pass one output [5].

The equations can be simplified in the form of :

-i Here, tan αi is restricted to ± 2 . Thus, multiplication is transformed to an arithmetic right shift. Since cosine is an even function, therefore cos(α )= cos(−α ) The iterative equation can be reduced to-

Where

is known as gain factor for each iteration. If M iterations are performed, then scale factor, K, is defined as the multiplication of every Ki. So,

The elementary functions sine and cosine can be computed using the rotation mode of the CORDIC algorithm if the initial vector starts at ( |K| ,0) with unit length.

The most recurrent problem for a CORDIC implementation is overflow. Since the first tangent value is 20=1 then rotation range will be [−π /2,π/ 2]. The difference in binary representation between these two angles is one bit.Overflow arises when a rotational angle crosses a positive right angle to a negative one. To avoid overflow, an overflow control is added. It checks for the sign of the operands involved in addition or subtraction and the result of the operation. If an overflow is produced, the result keeps its last sign without affecting the final result. In the overflow control, the sign of z determines whether addition or subtraction is to be i performed.

III. PIPELINED ARCHITECTURE OF CORDIC In Pipelined CORDIC architecture, number of rotational modules are incorporated and each module is responsible for one elementary rotation. The modules are cascaded through intermediate latches (Fig. 1). Every stage within the pipelined

ISSN: 2278 – 909X International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE) Volume 2, Issue 1, January 2013

( a ) ( c ) Fig 2 : Simulation Results of All DPLL

( b )

IV. BLOCK DIAGRAM OF ALL DPLL

DDS is used for carrier generation. All the blocks are Fig 3: Top Level Block Diagram All DPLL connected with common clock and reset signals. The delta phase value decides the phase increment for each clock pulse. Hence decides the resulting signal frequency. The Frequency modulating instantaneous value is added to the delta phase Proposed All DPLL consists of: value which causes instantaneous change in frequency. Due to the digital nature of the modulator only at each clock tick 1. DDS the modulating signal value shall affect the resulting frequency. The phase accumulator produces accumulated 2. Filters phase value for each clock pulse. In case if the DDS is used for phase modulation then instantaneous phase modulating 3. Arc tan estimator signal value is added to the phase output of phase accumulator. 4. Loop Filter (PID controller) This resulting phase value is given to the four Look Up

Tables. Each Look Up Table is configured to produce a 1. DDS specific waveform. The outputs of four Look Up Tables are given to the input lines a 4 to 1 Multiplexer. This multiplexer connects one of the inputs to the output depending on the select lines. The output of Multiplexer consists the 8 amplitude bits which is the final output in case required modulation schemes are FM or PM. In case of Amplitude modulation, the output of Multiplexer is multiplied with instantaneous modulating signal. In three modulation schemes if modulating signal is analog in nature then an appropriate Analog to Digital converter is required to convert into 8 bit digital output. From the figure 4 the basic blocks in DDS can be identified as PIPO registers, adders, Look Up Tables and other combinational circuits. The ModelSim tool from Mentor Graphics is used, for simulation and functional verification of DDS. Fig 4: Basic Block Diagram of DDS VHDL has been used as design entry method for all these blocks. Xilinx ISE (Integrated Software Environment) XST (Xilinx Synthesis Tool) is used as a synthesis tool to implement the design on Spartan-3E FPGA. Chipscope pro is used for analyzing the implemented design.

ISSN: 2278 – 909X International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE) Volume 2, Issue 1, January 2013 a.PIPO n bit generic register: The Parallel in Parallel Out four look up tables are same. The output of modulator is shift register cells are required in phase accumulator block to given to the demodulator. hold frequency and phase values. Synchronization is required between the phase increment register and phase register. 2. FILTERS This is achieved by connecting a common clock signal. Generic is used in VHDL implementation which allows to The carrier waves (Cosine and Sine) that are generated by instantiate the PIPO component any bit size. DDS core is given as input to the filter. The direct form of FIR filter is standard linear convolution, which described the b. N bit generic adder: The N-bit generic adder is output as convolution of input and impulse response of the implemented in VHDL with simple ripple carry adder logic. filter. The adder is tested with inputs A=011001, B=000101 and y[n] = x[n]*c[n] = ∑ x[k]c[n-k] = ∑ c[k]x[n-k]. output observed is Z = 011110. Where c[n] values represent filter coefficients, and x[n]

represents the input samples. c. Phase Accumulator: The phase accumulator consists of phase increment register, adder and phase register.

Fig 5: Phase Accumulator

The phase increment register stores the instantaneous phase Fig 6: Direct form 6-tap FIR filter increment values resulting from frequency modulation Finite impulse response (FIR) filters are the most popular control block. This is fed to a 8 bit adder as one of its input. type of filters implemented in software. Filters are signal The other input for adder is phase register output. The phase conditioners. Each functions by accepting an input signal, register holds the instantaneous phase for each clock pulse. blocking prespecified frequency components, and passing the original signal minus those components to the output. A The accumulated phase also is represented by 8 bits, which digital filter takes a digital input, gives a digital output, and limits the maximum phase by 11111111, and addition by 1 to consists of digital components. In a typical digital filtering maximum value causes the phase to become 00000000 This application, software running on a digital signal processor is expected and desired since the Look Up Tables are (DSP) reads input samples from an A/D converter, performs programmed to consider 255 as highest phase value and the mathematical manipulations dictated by theory for the phase increment by one results next cycle of waveform. required filter type, and outputs the result via a D/A converter. Since 8 bits are used to represent the 0O to 360O the increment in digital phase value by one causes effective increment of 3. ARC TAN ESTIMATOR 1.40625O (results by dividng 360O with 256 maximum possible combinations of 8 bits) . This also implies that The outputs of filters are given to this module. atan(y / x) outputs can’t have more that 256 samples for one cycle. The returns in radians. The result is between -pi and pi. The output of phase accumulator when the phase increment value vector in the plane from the origin to point (x, y) makes this is 00000001 (decimal four) is given in figure 3.5. It can be angle with the positive X axis. The point of atan2 () is that observed that the resulting phase value after each clock pulse the signs of both inputs are known to it, so it can compute the is four added to the previous phase value. In the following correct quadrant for the angle. For example, atan figure initial phase is 0 and further with clock pulses resulting (1) and atan2 (1, 1) are both pi/4, but atan2 in 4,8,12,16 ... (-1, -1) is -3*pi/4. The ATAN function returns the angle, expressed in radians, whose tangent is X (i.e., the d. Look up Tables: Four Look up Tables are implemented to arc-tangent). If two parameters are supplied, the angle whose produce four different output waveforms, namely sine wave, tangent is equal to Y/X is returned. For real input, the range of square wave, triangular wave and arbitrary waveform. As a ATAN is between -/2 and /2 for the single argument case standard practice these LUTs are implemented using VHDL and between - and  if two arguments are given. In the CASE statement. Matlab is used for calculating the amplitude single argument case with a complex number, Z = X + iY, bits from the corresponding phase bits. Since the generation Syntax: Result = ATAN(X [, /PHASE] ) of square wave requires producing only two amplitude levels in one cycle, it can be implemented without Look up Table. It is possible to implement any arbitrary waveform, by appropriately changing the content of LUT. The ports of all

4.LOOP FILTER

A proportional–integral–derivative controller (PID controller) is a generic control loop feedback mechanism (controller) widely used in industrial control Table-2: Effects of increasing a parameter independently systems – a PID is the most commonly used feedback controller. A PID controller calculates an "error" value as the The response from arctan estimator is given to Loop filter. This helps in minimizing the error. The output is given to difference between a measured process variable and a filter block. desired set point. The PID controller calculation (algorithm) involves three separate constant parameters, and is V. CONCLUSION accordingly sometimes called three-term control: the proportional, the integral and derivative values, The proposed VLSI implementation of high performance denoted P, I, and D. Histically, these values can be digital phase locked loop based FM receiver has been interpreted in terms of time: P depends on the present error, designed so that it can meet the constraint for the application in personal wireless communication, very high frequency I on the accumulation of past errors, and D is a prediction signal processing field. The circuit requires only 3.5K slices of future errors, based on current rate of change. The for implementation and it can operate at maximum frequency weighted sum of these three actions is used to adjust the of 50 MHz. Xilinx xc3s500e-5fg320 devices has been used process via a control element such as the position of a control as the target device for FPGA implementation and XST has valve or the power supply of a heating element. been used as a synthesis tool. Here it is concluded that the designed high performance FM receiver can be easily fitted into the next generation communication receiver circuit where low-power and minimum hardware utilization with the maximum clock. frequency is the key concern. As future work, This work can be extended in order to increase the accuracy by increasing the speed of modem. The cost also can be reduced by simplifying the circuit complexity by making simple design.

REFERENCES

[1] J.E. Volder. "The CORDIC Trigonometric Computing Technique". IRE Transactions on Electronic Computing, vol Fig 7: PID Block Diagram EC-8, pp 330-334, Sept 1959. [2] Y.H. Hu. "CORDIC-Based VLSI Architectures for Digital In theory, a controller can be used to control any process Signal Processing" IEEE Signal Processing Magazine, Vol. 9, No. 3, pp. 16-35, 1992. which has a measurable output (PV), a known ideal value for [3] Andraka R.A., "Survey of CORDIC Algorithms for FPGA that output (SP) and an input to the process (MV) that will Based Computers‖, Proceedings of the 1998 ACM/SIGDA 6th affect the relevant PV. Controllers are used in industry to International Symposium on FPGAs, pp 191-200, Monterey, regulate temperature, pressure, flowrate, chemical compositi California, Feb.22-24, 1998. on, speed and practically every other variable for which a [4] S.Wang, V.Piuri, E.E.Swartzlander. Jr.,"Granularly-pipelined measurement exists. The loop filter/loop controller used is CORDIC processors for sine and cosine generators‖, IEEE PID Controller. The transfer function of the PID controller International Conference on Acoustics, Speech, and Signal looks like the following: Processing ICASSP, vol. 6, pp. 3298-3301, 1996. [5] M. Chakraborty, A. S. Dhar and Moon Ho Lee, ―A Trigonometric Formulation of the LMS Algorithm for Realisation of Pipelined CORDIC,‖ IEEE Trans. Circuits and Systems, vol. 52, no. 9, pp. 530-534, Sep.2005. [6] Vuori J., ―Implementation of a Digital Phase-Locked Loop Using CORDIC Algorithm‖, IEEE International Symposium  Kp = Proportional gain on Circuit and Systems, Atlanta, USA 1996, pp.IV-164-167. [7] A. Mandal, K.C. Tyagi, B.K. Kaushik, ―VLSI Architecture  KI = Integral gain Design and Implementation for Application Specific CORDIC Processor‖, 2nd IEEE International Conference on Advances  Kd = Derivative gain in Recent Technologies in Communicaion and Computing (ARTCom),pp 191-193, Oct 16-17, 2010. The values are

kp is "0000000000000010" -- 0.09375 with Q7 format ki is "0000000000000001" -- in Q7 format kd is "0000000000000010" -- 0.09375 with Q7 format