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DPLL) Using Pipelined Carrier Synthesis Techniques ISSN: 2278 – 909X International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE) Volume 2, Issue 1, January 2013 High speed all digital phase locked loop (DPLL) using pipelined carrier synthesis techniques T.Kranthi Kiran, Dr.PS.Sarma polynomial approximation, e.g. Taylor series. But it requires Abstract— DPLLs are used widely in communications a considerable amount of hardware space on the silicon systems like radio, telecommunications, computers and other substrate. Interpolation method using table look-up may be electronic applications. Digital PLLs are a type of PLL used to the other solution. But it also requires large number of gates synchronize digital signals. While DPLLs input and outputs are and ROM memory. The CORDIC offers the opportunity to typically all digital, they do have internal functions which are calculate the desired functions in a simple and efficient way. dependent on analog signals. This project deals with the design Due to the simplicity of the involved operations, the of pipelined architecture for coordinate rotation algorithm for the computation of loop performance of complex Digital Phase CORDIC realization of complex DPLL is very well suited in Locked Loop (DPLL). For on-chip application, the area VLSI hardware design and its implementation. This paper reduction in proposed design can is achieved through first describes the CORDIC algorithm and then pipelined optimization in the number of micro rotations. For better loop architecture design [7]. Thereafter, implementation with performance of second order complex DPLL and to minimize adjustment of micro- rotation has been described. Finally quantization error, the numbers of iterations are also CORDIC realization of a complex phase locked loop is optimized. Modelsim Xilinx Edition (MXE) and Xilinx ISE will described. be used simulation and synthesis respectively. The Xilinx Chipscope tool will be used to test the FPGA inside results while the logic running on FPGA. The Xilinx Spartan 3 Family FPGA development board will be used this project. Index Terms—CORDIC, Digital Signal Processing, Pipelined II. CORDIC ALGORITHM Architecture, DPLL, Micro-rotation, Loop performance. The Volder’s CORDIC algorithm [1] is derived from the general equations of vector rotation. The theory of CORDIC computation is to decompose the desired rotation angle into I. INTRODUCTION the weighted sum of a set of predefined elementary rotation CORDIC algorithm was first developed by Jack E. Volder in angles. Each of them can be accomplished with simple shift 1959 [1]. CORDIC algorithm is extremely useful in efficient add operation for a desired rotational angle θ. It can be T and effective implementation of DSP systems [2]. This represented for M iterations of an input vector (x,y) setting algorithm allows implementation of trigonometric functions initial conditions: x0=x, y0=y,and z0= θ as like sine, cosine, magnitude and phase with great precision by using just simple shift and adding operations [1-4]. Although the same functions can be implemented using multipliers, variable shift registers or Multiply Accumulator (MAC) units, but CORDIC can implement these functions If zf=0 holds, then efficiently while saving enough silicon area which is considered to be primary design criteria in VLSI technology. This paper designs first order complex DPLL using CORDIC which functions as a FSK demodulator [6]. In digital PLL, an adjustable local sine wave generator and phase detector is required. The sine and cosine terms can be calculated using i.e. the total accumulated rotation angle is equal to θ. δi , 0 ≤ 1≤ M-1denote a sequence of ±1s that determine the direction of each elementary rotation. When M is the total Manuscript received jan2, 2013. number of elementary rotation angles, i-th angle αi is given T.Kranthi Kiran, M.Tech VLSI-SD, Aurora Technological and Research Institute, JNTUH, Hyderabad, India, Mobile No:9704481664 Dr.PS.Sarma, professor of ECE Department & Dean of Academics , Aurora Technological and Research Institute, JNTUH, Hyderabad, India, Mobile No:9490755593. 11 All Rights Reserved © 2012 IJARECE ISSN: 2278 – 909X International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE) Volume 2, Issue 1, January 2013 by: CORDIC architecture [4] only adder/ subtractor is used. The shift operations are hardwired using permanent oblique bus -i connections to perform multiplications by 2 . The precomputed values, as given in Table I, of i-th iteration angle αi required at each module is stored at a ROM memory location. The delay is adjusted by using proper bit-length in the shift register. Since no sign detection is needed to force where m=0, 1 and -1 correspond to the rotation operation in zf=0, the carry save adders are well suited in this architecture. linear, circular, and hyperbolic coordinate system The use of these adders reduces the stage delay significantly. respectively. For a given value of θ, the CORDIC iteration is With the pipelining architecture, the propagation delay of the given by: multiplier is the total delay of a single adder. So ultimately the throughput of the architecture is increased to many folds as the throughput is given by: ―1/(delay due to a single adder)‖. If an iterative implementation of the CORDIC is -1 -i used, the processor would take several clock cycles to give where α i = tan 2 . In case of counter clockwise rotation of a vector, the recursively updated equations are output for a given input. But in the pipelined architecture, each pipeline stage takes exactly one clock cycle to pass one output [5]. The equations can be simplified in the form of : -i Here, tan αi is restricted to ± 2 . Thus, multiplication is transformed to an arithmetic right shift. Since cosine is an even function, therefore cos(α )= cos(−α ) The iterative equation can be reduced to- Where is known as gain factor for each iteration. If M iterations are performed, then scale factor, K, is defined as the multiplication of every Ki. So, The elementary functions sine and cosine can be computed using the rotation mode of the CORDIC algorithm if the initial vector starts at ( |K| ,0) with unit length. The most recurrent problem for a CORDIC implementation is overflow. Since the first tangent value is 20=1 then rotation range will be [−π /2,π/ 2]. The difference in binary representation between these two angles is one bit.Overflow arises when a rotational angle crosses a positive right angle to a negative one. To avoid overflow, an overflow control is added. It checks for the sign of the operands involved in addition or subtraction and the result of the operation. If an overflow is produced, the result keeps its last sign without affecting the final result. In the overflow control, the sign of z determines whether addition or subtraction is to be i performed. III. PIPELINED ARCHITECTURE OF CORDIC In Pipelined CORDIC architecture, number of rotational modules are incorporated and each module is responsible for one elementary rotation. The modules are cascaded through intermediate latches (Fig. 1). Every stage within the pipelined 12 All Rights Reserved © 2012 IJARECE ISSN: 2278 – 909X International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE) Volume 2, Issue 1, January 2013 ( a ) ( c ) Fig 2 : Simulation Results of All DPLL ( b ) 13 All Rights Reserved © 2012 IJARECE ISSN: 2278 – 909X International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE) Volume 2, Issue 1, January 2013 IV. BLOCK DIAGRAM OF ALL DPLL DDS is used for carrier generation. All the blocks are Fig 3: Top Level Block Diagram All DPLL connected with common clock and reset signals. The delta phase value decides the phase increment for each clock pulse. Hence decides the resulting signal frequency. The Frequency modulating instantaneous value is added to the delta phase Proposed All DPLL consists of: value which causes instantaneous change in frequency. Due to the digital nature of the modulator only at each clock tick 1. DDS the modulating signal value shall affect the resulting frequency. The phase accumulator produces accumulated 2. Filters phase value for each clock pulse. In case if the DDS is used for phase modulation then instantaneous phase modulating 3. Arc tan estimator signal value is added to the phase output of phase accumulator. 4. Loop Filter (PID controller) This resulting phase value is given to the four Look Up Tables. Each Look Up Table is configured to produce a 1. DDS specific waveform. The outputs of four Look Up Tables are given to the input lines a 4 to 1 Multiplexer. This multiplexer connects one of the inputs to the output depending on the select lines. The output of Multiplexer consists the 8 amplitude bits which is the final output in case required modulation schemes are FM or PM. In case of Amplitude modulation, the output of Multiplexer is multiplied with instantaneous modulating signal. In three modulation schemes if modulating signal is analog in nature then an appropriate Analog to Digital converter is required to convert into 8 bit digital output. From the figure 4 the basic blocks in DDS can be identified as PIPO registers, adders, Look Up Tables and other combinational circuits. The ModelSim tool from Mentor Graphics is used, for simulation and functional verification of DDS. Fig 4: Basic Block Diagram of DDS VHDL has been used as design entry method for all these blocks. Xilinx ISE (Integrated Software Environment) XST (Xilinx Synthesis Tool) is used as a synthesis tool to implement the design on Spartan-3E FPGA. Chipscope pro is used for analyzing the implemented design. 14 All Rights Reserved © 2012 IJARECE ISSN: 2278 – 909X International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE) Volume 2, Issue 1, January 2013 a.PIPO n bit generic register: The Parallel in Parallel Out four look up tables are same.
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