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FPGA Based Gate Signal Generator for Three-Level Neutral Point Clamped Inverters

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FPGA Based Gate Signal Generator for Three-Level Neutral Point Clamped Inverters The University of Manchester Research FPGA based gate signal generator for three-level neutral point clamped inverters Link to publication record in Manchester Research Explorer Citation for published version (APA): Ahmed, M. R., & Rogers, D. J. (2015). FPGA based gate signal generator for three-level neutral point clamped inverters. In host publication IEEE. Published in: host publication Citing this paper Please note that where the full-text provided on Manchester Research Explorer is the Author Accepted Manuscript or Proof version this may differ from the final Published version. If citing, it is advised that you check and use the publisher's definitive version. General rights Copyright and moral rights for the publications made accessible in the Research Explorer are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights. Takedown policy If you believe that this document breaches copyright please refer to the University of Manchester’s Takedown Procedures [http://man.ac.uk/04Y6Bo] or contact [email protected] providing relevant details, so we can investigate your claim. Download date:04. Oct. 2021 FPGA based Gate Signal Generator for Three-level Neutral Point Clamped Inverters Md Rishad Ahmed Daniel J. Rogers School of Electrical and Electronic Engineering, Institute of Energy, School of Engineering, Power Conversion Group, The University of Manchester Cardiff University Manchester, United Kingdom. Cardiff, United Kingdom. [email protected] [email protected] Abstract—The gate signals in a commercial three-phase two- where sinusoidal control signals are compared with the level induction motor drive are translated to operate a three- triangular carrier signal(s) to generate gate pulses for the power phase three-level neutral point clamped (NPC) inverter. An switches. FPGA is used to demodulate the two-level gate signals and then to generate NPC gate drive signals by re-modulation. A sine Fig. 2(a) and 2(b) respectively show the simplified inputs PWM modulation strategy with in-phase disposition of carriers is and actual PWM inputs to the gate drivers of four switches used to generate NPC gate drive signals. The modulation strategy (T1-T4) in a phase leg of a NPC or TNPC inverter circuit is simulated first and then implemented using an Altera FPGA. shown in Fig. 1(a) and 1(b). Fig. 2 also shows the respective The close match between the simulation and experimental results hypothetical phase to neutral voltage output, u(t). The auxiliary proves the concept and demonstrates the accuracy of this unique transistors (T2,T3) are driven with complementary gate signals modulation technique. to the main transistors (T1,T4). When the upper two switches (T1,T2) are on, the output voltage is equal to +DC, when the Keywords— NPC inverter; Modulation strategy; sine PWM; middle two switches (T2,T3) are on, the output voltage is zero, VHDL code; FPGA and when the bottom two switches (T3,T4) are on, the output voltage is equal to –DC. I. INTRODUCTION In any AC motor drive system, harmonics in the applied voltage cause losses and pulsating torques in the motor. The main reason for the development of pulse width modulation (PWM) technique for the motor-drive inverter was to reduce these harmonics and to ensure better control of the fundamental voltage. Again, three level inverters were developed to further reduce harmonics and consequently to increase the efficiency of the motor drive system. [1] Compared to the two-level inverter a conventional three- level neutral point clamped (NPC) inverter features two Fig. 1. Phase leg of a (a) 2L inverter, (b) three-level NPC inverter and (c) three- additional active switches, two extra isolated gate drivers, and level TNPC inverter four extra diodes per phase leg (Fig. 1(a) and 1(b)). In case of three-level T-type neutral point clamped inverter (TNPC), a In this paper an FPGA based implementation of sine-triangular total of four active switches and four diodes are required per PWM modulation technique for three-level NPC inverter is phase (Fig. 1(c)). Both NPC inverters have the advantage of presented. The uniqueness of the proposed technique is the better controllability of phase currents and DC link voltage, derivation of the sinusoidal control signals directly from the lower output current total harmonic distortion and therefore gate signals of a commercial three-phase bridge (3PB) (two- smaller passive components, higher efficiency at increased level) converter. The two-level PWM gate drive waveform is switching frequency (considering similar modulation demodulated and then re-modulated into a three-level PWM technique), and lower voltage stress on the switching gate drive waveform. An example of the useful application of components (only for NPC inverter) [2, 3]. this technique is when investigating how an existing commercial two-level motor drive product would perform with There are many PWM modulation techniques for both two- an alternative three-level power output stage. In this case, it is level inverter and three-level NPC inverter. For both inverters not necessary to redesign an existing and proven Application popular PWM techniques are sine-triangle PWM, space vector Specific Integrated Circuit (ASIC) solution from the original PWM, PWM with third harmonic injection, programmed PWM product. In addition, if the existing ASIC lacks sufficient PWM with selective harmonic elimination and current-regulated output hardware, the cost associated with migrating this into a PWM from hysteresis control [4, 5]. In both cases the simplest new ASIC is also avoided. This technique can dramatically form of PWM generation technique is sine-triangular PWM reduce development time and is particularly useful in the early This work was conducted at Cardiff University under a research project funded by Control Techniques Emerson Industrial Automation. 978-1-4799-6300-3/15/$31.00 ©2015 IEEE 419 prototyping an experimentation phase of a design when the carrier frequency and the modulating frequency, fc / fm. The advantages of a three-level output stage are under investigation. amplitude modulation index, ma determines the peak of the Although the technique requires the addition of an FPGA fundamental component of output phase voltage, Vu_peak as device to perform the de- and re-modulation, it could shown in equation (1) for linear modulation. potentially be used in a final design to extend an existing m V product family whilst keeping common DSP hardware and = a DC (1) Vu _ peak avoiding a major redesign and qualification process. 2 where, VDC is the total DC link voltage and A = m (2) ma Ac Here, Am is the peak value of the modulating waveform and Ac is the peak value of the carrier waveforms. For linear modulation, Am ≤ Ac. The PWM gate signals shown in Fig. 2 (b) can be found from the comparison between the modulating and carrier signals shown in Fig. 3. For example, when the modulating signal is greater than the positive carrier signal in Fig. 3(a), then the corresponding semiconductor switch is turned on i.e. Vg1 is positive. Otherwise the semiconductor switch is turned off i.e. Vg1 is zero. Similarly, the negative carrier determines Vg2. Vg3 and Vg4 are found by taking the complementary Fig. 2. Hypothetical gate driver signals and output phase voltage of NPC or signals of Vg1 and Vg2, respectively. Sometimes, zero sequence TNPC inverter (a) simplified signals and (b) PWM signals voltages are added to the modulating signal to reduce switching losses and to gain better control of the neutral point voltage [8]. Modulating Signal Negetive Carrier Positive Carrier II. MODULATION TECHNIQUES FOR THREE-LEVEL 13 NPC INVERTER Although there are many strategies for generating gate 0 signals for NPC inverters most of them are extension of either 0.02 0.025 0.03 0.035 0.04 sinusoidal PWM technique or space vector PWM technique or ( v) Voltage a hybrid technique between them. A brief description of the -13 Time (s) common modulation techniques from literature is given in this section. (a) Modulating Signal Positive Carrier Negetive Carrier A. Standard Sinusiodal PWM Techniques 13 Standard Sinusoidal PWM techniques for NPC inverters can be categorized according to the different types of carrier 0 signals. Usually in three-level NPC inverters two triangular 0.02 0.025 0.03 0.035 0.04 carrier signals are required for sine PWM modulation for each (v) Voltage phase. These two carrier signals can be phase shifted or voltage -13 Time (s) shifted or both phase and voltage shifted. They are compared with a sinusoidal modulating waveform to generate the gate (b) pulses for the semiconductor switches in each phase. The most Fig. 3. Sine PWM strategies for NPC or TNPC inverter (a) in-phase disposition common sinusoidal PWM techniques for NPC inverters are in- of carriers and (b) phase-opposition disposition of carriers phase disposition method and phase-opposition disposition B. Space Vector PWM Techniques method [6, 7]. As shown in Fig. 2 each output phase voltage of the NPC Fig. 3(a) and 3(b) show the two sine-PWM modulation inverter depends on the switching state of any two phase-leg strategies for three-level NPC or TNPC inverters. In both switches. Therefore, there are three types of switching states cases, the frequency of the carrier signals (fc) determine the per phase and in total there are 27 switching states for the three switching frequency of the output phase voltages and the phase inverter [7, 9] If the three switching states corresponding frequency of the sinusoidal modulating wave (fm) determines to the DC, 0 and –DC levels are denoted as P, G and N, the 27 the fundamental frequency of the output voltages and currents.
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