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Simulink®-Based Programming Environment for Heterogeneous Mpsoc ® ® Simulink®-based Programming Environment for Heterogeneous MPSoC Katalin Popovici [email protected] Software Engineer, The MathWorks © 2009 TheMathWorks, Inc. DATE 2009, Nice, France ® ® Summary . MPSoC (Multi-Processor System On Chip) integrates different components (hardware and software) on a single chip . Context: . Heterogeneous MPSoC are required by current embedded applications . TI OMAP, ST Nomadik, NXP Nexperia, Atmel Diopsis . DSP + µC + sophisticated communication infrastructure . Multiple software (SW) stacks . Problem: . Classic programming environments do not fit: . High level programming environments are not efficient to handle specific architecture capabilities (e.g., C/C++, Simulink) . HW (Virtual) prototypes are too detailed and time consuming for SW debug . Challenge: . Efficient and fast programming environment for heterogeneous MPSoC 2 1 ® ® Proposal . Simulink based SW development and validation environment . Combined architecture and application model in Simulink . Architecture markers to ggyenerate executable SystemC models . Performance analysis with different levels of details . Computation and communication mapping exploration DPCD Variable IDCT Zigzag Length IQ Scan JPEG Decoding Images RLD Quantification Huffman Tables Tables Regenerate SystemC C\C++ Virtual Architecture Transaction Model Virtual Prototype 3 ® ® Outline . Introduction . Software Design and Validation . System Architecture . Virtual Architecture . Transaction Accurate Architecture . Conclusions 4 2 ® ® MPSoC Architecture . Heterogeneous MPSoC HW-SS SW-SS . SW subsystems for flexibility . HW subsyypstems for performance Interconnect Component . Complex communication network . Bus based architectures . Network on Chip (NoC) architectures Application . SW subsystem Software Hardware dependent Software (HdS) . Specific CPU subsystem: . CPUs: GPP, DSP, ASIP .CPU . I/O + memoryypp architecture + other peripherals CPU Memory . Layered SW architecture: Hardware . Application code (tasks) Network Other Interface Periph. Hardware dependent Software (HdS) . Specific to architecture / application to achieve efficiency . Programming heterogeneous MPSoC . Generate SW efficiently by using HW resources for communication & synchronization 5 ® ® Example of Heterogeneous MPSoC: Reduced Atmel Diopsis RDT MEM SS ARM9 SS . ARM9 SS SRAM DXM . DSP SS Bridge Bridge ARM9 ROM . MEM SS AMBA AHB . POT SS (Periph. On Tile) . I/O peripherals Bridge POT SS Bridge DMA DSP SS . System peripherals Timer mailbox PIC mailbox PMEM . Interconnect: AMBA bus AIC SPI REG DMEM DSP . Local & global memories accessible by both processing units . Different communication schemes between CPUs . Require multiple software stacks (ARM + DSP) 6 3 ® ® Software Stack Organization SW Subsystem Task 1 Task 2 Task n Memory CPU Application HdS HDS API Comm OS InterfInterf.. PeriphPeriph.. HAL API HAL . SW stack is organized into layers SW Stack . Application code . SW code of tasks mapped on the CPU . HdS (Hardware dependent Software) made of different components . OS ((pOperating Sy stem) . Comm (Communication Primitives) . HAL (Hardware Abstraction Layer) . API (Application Programming Interface) . Different SW components need to be validated incrementally . Different abstraction levels corresponding to the different SW components . SW development platforms (HW abstraction models) to allow specific SW components debug and communication refinement 7 ® ® Software Development Platform User SW code Development Platform . User SW Code . C/C++, Simulink functions, binary,… Executable . Development platform to abstract Model architectures Generation . Runtime library, simulator (ISS, Simulink) HW Executable Model Abstraction . Executable model generation . Compile, Link Debug & . Debug Performance Hardware Platform . Iterative process Validation . Different SW components need different detail levels . Requirements for MPSoC executable models: . Speed . Easily experiment with several mapping schemes . Multiple SW stacks . Accuracy . Evaluate the effect on performance by using specific HW resources . Debug low level SW code 8 4 ® ® Software Design Flow ARM7 Mem. XTENSA Mem. Platform Independent Local Bus Local Bus F1 F2 Architecture Application F0 F5 F Interface Periph. Interface Periph. 6 F3 F4 Global Bus HdHardware AhittArchitecture ARM-SS XTENSA-SS Simulink Template T1 T2 T3 F F 1 Partitioning2 & Mapping F 0 F5 F6 F3 F4 Simulink System Architecture Combined Architecture / Application Model Development Platform Software Stack Generation Generation HW Library SW Library SystemC Virtual Prototype & SW Binary 9 ® ® Software Abstraction Levels SW-SS1 SW-SS2 SW Development T1 T2 T3 SW Architecture Platform Simulink Sy stem Architect u re Abstract CPU-SS1 Abstract CPU-SS2 T1 MEM T2 T3 SystemC TLM T2 HDS API Abstract Interconnect Component Virtual Architecture Abstract CPU-SS1 Abstract CPU-SS2 T2 T3 MEM-SS CPU1 Memory CPU2 Memory SystemC TLM HDS API Interface Periph Interface Periph Comm OS HAL API Transaction Accurate Interconnect Component (Bus/NoC) Architecture CPU1 CPU-SS1 CPU2 CPU-SS2 T2 T3 MEM-SS SystemC TLM ISS Memory ISS Memory HDS API Periph Interface Periph Interface Comm OS Virtual Prototype HAL API Interconnect Component (Bus/NoC) HAL 10 5 ® ® Software Abstraction Levels SW-SS1 SW-SS2 SW Development T1 T2 T3 SW Architecture Platform Simulink Sy stem Architect u re Abstract CPU-SS1 Abstract CPU-SS2 T1 MEM T2 T3 SystemC TLM T2 HDS API Abstract Interconnect Component Virtual Architecture Models to debug the SW GAPSW Design Abstract CPU-SS1 Abstract CPU-SS2 T2 T3 MEM-SS CPU1 Memory CPU2 Memory SystemC TLM HDS API Interface Periph Interface Periph Comm OS HAL API Transaction Accurate Interconnect Component (Bus/NoC) Architecture CPU1 CPU-SS1 CPU2 CPU-SS2 T2 T3 MEM-SS SystemC TLM ISS Memory ISS Memory HDS API Periph Interface Periph Interface Comm OS Virtual Prototype HAL API Interconnect Component (Bus/NoC) HAL 11 ® ® Outline . Introduction . Software Design and Validation . System Architecture . Virtual Architecture . Transaction Accurate Architecture . Conclusions 12 6 ® ® System Architecture Model SW-SS1 SW-SS2 SW Development T1 T2 T3 SW Architecture Platform Simulink Sy stem Architect u re Abstract CPU-SS1 Abstract CPU-SS2 T1 MEM T2 T3 SystemC TLM T2 HDS API Abstract Interconnect Component Virtual Architecture Abstract CPU-SS1 Abstract CPU-SS2 T2 T3 MEM-SS CPU1 Memory CPU2 Memory SystemC TLM HDS API Interface Periph Interface Periph Comm OS HAL API Transaction Accurate Interconnect Component (Bus/NoC) Architecture CPU1 CPU-SS1 CPU2 CPU-SS2 T2 T3 MEM-SS SystemC TLM ISS Memory ISS Memory HDS API Periph Interface Periph Interface Comm OS Virtual Prototype HAL API Interconnect Component (Bus/NoC) HAL 13 ® ® System Architecture Design . Captures application and mapping to Subsystems Tasks architecture Functions SW-SS1 SW-SS2 . Task T1 T2 T3 . Set of functions: . Simulink blocks, S-functions F1 F2 F3 F4 . Subsystem COMM3 . Set of tasks COMM1 . Abstract communication types . Communication Intra-SS COMM2 . Communication Inter-SS Param1 = Value1 Param2 = Value2 . Communication protocol Comm. Generic Simulink I/Os Inter-SS Comm. Explicit annotation for implementation Intra-SS . Algorithm validation through simulation 14 7 ® ® Application Example: M-JPEG Decoder Mapped on Diopsis RDT T1 DC Coefficients T2 T3 T4 . Application JPEG Variable DPCD Images IDCT specification Length Zigzag Scan IQ Decoding (~ 1700 LOC) 01101… RLD Huffman Tables AC Coefficients Quantification Tables Bitmap Images MEM SS ARM9 SS SRAM . Target architecture: DXM Diopis RDT with AMBA Bridge Bridge ARM9 ROM AMBA AHB Bridge POT SS Bridge DMA DSP SS . Partitioning & mapping Timer mailbox PIC mailbox PMEM REG DMEM DSP AIC SPI 15 ® ® System Architecture Level Software Development Platform for Diopsis RDT ARM9-SS DSP-SS POT-SS (I/O) T1 T2 T3 T4 ch1_T1T2 … … ch5_T1T2 ch1_T2T3 ch_T3T4 ResourceType = DXM ch2_T2T3 InterconnectType = AMBA ModuleName = DXM0 Communication units: Simulink Signals Architecture markers annotating the model: . 5 Intra SS communication units . ResourceType . depends on application . ARM9, DSP, POT, Task . Communication: swfifo, dmem, sram, reg, dxm . 3 Inter SS communication units . NetworkType: AMBA_AHB, NoC . depends on application . AccessType: DMA, direct . Generic channels to be mapped on resources . MemName . Execution model in Simulink Validation of application functionality 16 8 ® ® MJPEG System Architecture in Simulink . 7 S-Functions . Algorithm validation,10 frames QVGA YUV 444 . Simulation time: 15s on PC 1.73GHz, 1GBytes RAM ch1_T2T3 ch_T3T4 ARM9 ch2_T2T3 DSP POT Task1 Task2 Decoded Microblock Simulation running 17 ® ® Capture of Low Level Architecture Features in Simulink for MJPEG . 8 communication units: MEM SS . 3 Inter-SS + 5 Intra-SS SRAM ARM9 SS DXM . Communication schemes: . Chang ing mar ks o f Simu lin k mo de l Bridge Bridge ARM9 ROM AMBA AHB . Nb AMBA cycles REG to transfer “N” words Bridge POT SS Bridge DMA DSP SS . ARM wr: N/4+8+(N-1) Timer mailbox PIC mailbox PMEM . DSP rd: N/4 ResourceType = REG AIC SPI REG DMEM DSP For example, REG ch1_T2T3 ch_T3T4 ch2_T2T3 REG 18 9 ® ® Capture of Low Level Architecture Features in Simulink for MJPEG MEM SS . Nb AMBA cycles DXM to transfer “N” words SRAM ARM9 SS DXM . ARM wr: 2*N . DSP rd: 14+(N-1) Bridge Bridge ARM9 ROM AMBA AHB ResourceType = DXM Bridge POT SS Bridge DMA DSP SS AccessType = DMA Timer mailbox PIC mailbox PMEM AIC SPI REG DMEM DSP For example, DXM ch1_T2T3 ch_T3T4 ch2_T2T3 DXM 19 ® ® Capture of Low Level Architecture
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