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Intel(R) 64 and IA-32 Architectures Software Developer's Manual

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Intel(R) 64 and IA-32 Architectures Software Developer's Manual Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 1: Basic Architecture NOTE: The Intel® 64 and IA-32 Architectures Software Developer's Manual consists of five volumes: Basic Architecture, Order Number 253665; Instruction Set Reference A-M, Order Number 253666; Instruction Set Reference N-Z, Order Number 253667; System Programming Guide, Part 1, Order Number 253668; System Programming Guide, Part 2, Order Number 253669. Refer to all five volumes when evaluating your design needs. Order Number: 253665-033US December 2009 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANT- ED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR IN- TENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUA- TION WHERE PERSONAL INJURY OR DEATH MAY OCCUR. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "unde- fined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without no- tice. Do not finalize a design with this information. The Intel® 64 architecture processors may contain design defects or errors known as errata. Current char- acterized errata are available on request. Intel® Hyper-Threading Technology requires a computer system with an Intel® processor supporting Intel Hyper-Threading Technology and an Intel® HT Technology enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. For more information, see http://www.intel.com/technology/hyperthread/index.htm; including details on which processors support Intel HT Technology. Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor (VMM) and for some uses, certain platform software enabled for it. Functionality, perfor- mance or other benefits will vary depending on hardware and software configurations. Intel® Virtualization Technology-enabled BIOS and VMM applications are currently in development. 64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, oper- ating system, device drivers and applications enabled for Intel® 64 architecture. Processors will not operate (including 32-bit operation) without an Intel® 64 architecture-enabled BIOS. Performance will vary de- pending on your hardware and software configurations. Consult with your system vendor for more infor- mation. Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check with your PC manufacturer on whether your system delivers Ex- ecute Disable Bit functionality. Intel, Pentium, Intel Xeon, Intel NetBurst, Intel Core, Intel Core Solo, Intel Core Duo, Intel Core 2 Duo, Intel Core 2 Extreme, Intel Pentium D, Itanium, Intel SpeedStep, MMX, Intel Atom, and VTune are trade- marks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other coun- tries. *Other names and brands may be claimed as the property of others. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725, or by visiting Intel’s website at http://www.intel.com Copyright © 1997-2009 Intel Corporation CONTENTS PAGE CHAPTER 1 ABOUT THIS MANUAL 1.1 INTEL® 64 AND IA-32 PROCESSORS COVERED IN THIS MANUAL. 1-1 1.2 OVERVIEW OF VOLUME 1: BASIC ARCHITECTURE . 1-3 1.3 NOTATIONAL CONVENTIONS . 1-5 1.3.1 Bit and Byte Order . 1-5 1.3.2 Reserved Bits and Software Compatibility. 1-5 1.3.2.1 Instruction Operands. 1-6 1.3.3 Hexadecimal and Binary Numbers. 1-7 1.3.4 Segmented Addressing. 1-7 1.3.5 A New Syntax for CPUID, CR, and MSR Values . 1-7 1.3.6 Exceptions . 1-8 1.4 RELATED LITERATURE . 1-9 CHAPTER 2 INTEL® 64 AND IA-32 ARCHITECTURES 2.1 BRIEF HISTORY OF INTEL® 64 AND IA-32 ARCHITECTURE. 2-1 2.1.1 16-bit Processors and Segmentation (1978) . 2-1 2.1.2 The Intel® 286 Processor (1982) . 2-1 2.1.3 The Intel386™ Processor (1985) . 2-2 2.1.4 The Intel486™ Processor (1989) . 2-2 2.1.5 The Intel® Pentium® Processor (1993) . 2-2 2.1.6 The P6 Family of Processors (1995-1999) . 2-3 2.1.7 The Intel® Pentium® 4 Processor Family (2000-2006) . 2-4 2.1.8 The Intel® Xeon® Processor (2001- 2007) . 2-4 2.1.9 The Intel® Pentium® M Processor (2003-Current). 2-5 2.1.10 The Intel® Pentium® Processor Extreme Edition (2005-2007). 2-5 2.1.11 The Intel® Core™ Duo and Intel® Core™ Solo Processors (2006-2007). 2-5 2.1.12 The Intel® Xeon® Processor 5100, 5300 Series and Intel® Core™2 Processor Family (2006-Current) . 2-6 2.1.13 The Intel® Xeon® Processor 5200, 5400, 7400 Series and Intel® Core™2 Processor Family (2007-Current) . 2-6 2.1.14 The Intel® Atom™ Processor Family (2008-Current) . 2-7 2.1.15 The Intel® Core™i7 Processor Family (2008-Current) . 2-7 2.2 MORE ON SPECIFIC ADVANCES. 2-8 2.2.1 P6 Family Microarchitecture . 2-8 2.2.2 Intel NetBurst® Microarchitecture. 2-10 2.2.2.1 The Front End Pipeline . 2-12 2.2.2.2 Out-Of-Order Execution Core . 2-13 2.2.2.3 Retirement Unit . 2-13 2.2.3 Intel® Core™ Microarchitecture . 2-13 2.2.3.1 The Front End . 2-15 2.2.3.2 Execution Core . 2-16 2.2.4 Intel® Atom™ Microarchitecture . 2-16 Vol. 1 iii CONTENTS PAGE 2.2.5 Intel Microarchitecture (Nehalem) . 2-17 2.2.6 SIMD Instructions . 2-18 2.2.7 Intel® Hyper-Threading Technology . 2-21 2.2.7.1 Some Implementation Notes. 2-22 2.2.8 Multi-Core Technology . 2-22 2.2.9 Intel® 64 Architecture. 2-26 2.2.10 Intel® Virtualization Technology (Intel® VT) . 2-27 2.3 INTEL® 64 AND IA-32 PROCESSOR GENERATIONS . 2-27 CHAPTER 3 BASIC EXECUTION ENVIRONMENT 3.1 MODES OF OPERATION . 3-1 3.1.1 Intel® 64 Architecture . 3-2 3.2 OVERVIEW OF THE BASIC EXECUTION ENVIRONMENT . 3-2 3.2.1 64-Bit Mode Execution Environment . 3-6 3.3 MEMORY ORGANIZATION. 3-8 3.3.1 IA-32 Memory Models . 3-8 3.3.2 Paging and Virtual Memory . 3-10 3.3.3 Memory Organization in 64-Bit Mode. 3-10 3.3.4 Modes of Operation vs. Memory Model . 3-10 3.3.5 32-Bit and 16-Bit Address and Operand Sizes . 3-11 3.3.6 Extended Physical Addressing in Protected Mode. 3-12 3.3.7 Address Calculations in 64-Bit Mode . 3-12 3.3.7.1 Canonical Addressing. ..
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