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Computer Organization LEVEL 2 Microcode Chapter 12 Computer Organization LEVEL 2 Microcode APPLICATION LEVEL HIGH-ORDER LANGUAGE LEVEL ASSEMBLY LEVEL OPERATING SYSTEM LEVEL INSTRUCTION SET ARCHITECTURE LEVEL MICROCODE LEVEL 2 LOGIC GATE LEVEL 9781284079630_CH12_689_782.indd 689 29/01/16 8:27 am Computer Systems F I F T H E D I T I O N Central Processing Unit • Data section ‣ Receives data from and sends data to the main memory subsystem and I/O devices • Control section ‣ Issues the control signals to the data section and the other components of the computer system Copyright © 2017 by Jones & Bartlett Learning, LLC an Ascend Learning Company 692 CHAPTER 12 Computer Organization T is f nal chapter shows the connection between the combinational and sequential circuits at Level LG1 and the machine at Level ISA3. It describes how hardware devices can be connected at the Mc2 level of abstraction to form black boxes at successively higher levels of abstraction to eventually construct the Pep/9 computer. 12.1 Constructing a Level-ISA3 Machine FIGURE 12.1 is a block diagram of the Pep/9 computer. It shows the CPU divided into a data section and a control section. T e data section receives data from and sends data to the main memory subsystem and the disk. T e control section issues the control signals to the data section and to the other components of the computer. The CPU Data Section FIGURE 12.2 is the data section of the Pep/9 CPU. T e sequential devices in the f gure are shaded to distinguish them from the combinational devices. T e CPU registers at the top of the f gure are identical to the two-port register bank of Figure 11 . 52 . T e control section, not shown in the f gure, is to the right of the data section. T e control lines coming in from the right come from the control section. T e control lines are rendered as dashed lines in Figure 12 . 1 , but they are solid lines in Figure 12 . 2 . T ere are two kinds of control signals— combinational circuit controls and clock pulses. Names of the clock pulses all end in Ck and all act to clock data into a register or f ip-f op. For example, FIGUREComputer 12.1 Systems F I F T H E D I T I O N Figure 12.1 Block diagram of the Pep/9 computer. Main memory Disk CPU Input Data Control Output section section Data flow Control Copyright © 2017 by Jones & Bartlett Learning, LLC an Ascend Learning Company 9781284079630_CH12_689_782.indd 692 29/01/16 8:27 am 12.1 Constructing a Level-ISA3 Machine 693 FIGURE 12.2 The data section of the Pep/9 CPU. 01 8 14 15 22 23 A IR T3 M1 0x00 0x01 LoadCk 23 991 100 16 17 24 25 Figure 12.2 X T4 M2 0x02 0x03 45 11 18 19 26 27 5 C SP T1 T5 M3 0x04 0x08 67 12 13 20 21 28 29 5 B PC T2 T6 M4 0xF0 0xF6 5 30 31 A CPU registers M5 0xFE 0xFF CBus ABus BBus System bus MARB MARCk MARA MDRCk MDR MDRMux AMux AMux MDRMux CMux ALU 4 ALU CMux Cin CSMux CSMux Cout S SCk Mem C CCk Addr V VCk 0 AndZ Data 0 0 AndZ Z ZCk 0 Zout N NCk MemWrite MemRead 9781284079630_CH12_689_782.indd 693 29/01/16 8:27 am Computer Systems F I F T H E D I T I O N CPU components • 16-bit memory address register (MAR) ‣ 8-bit MARA and 8-bit MARB • 8-bit memory data register (MDR) • 8-bit multiplexers ‣ AMux, CMux, MDRMux ‣ 0 on control line routes left input ‣ 1 on control line routes right input Copyright © 2017 by Jones & Bartlett Learning, LLC an Ascend Learning Company Computer Systems F I F T H E D I T I O N Control signals • Originate from the control section on the right (not shown in Figure 12.2) • Two kinds of control signals ‣ Clock signals end in “Ck” to load data into registers with a clock pulse ‣ Signals that do not end in “Ck” set up the data flow before each clock pulse arrives Copyright © 2017 by Jones & Bartlett Learning, LLC an Ascend Learning Company 12.1 Constructing a Level-ISA3 Machine 693 Figure 12.2 FIGURE 12.2Computer Systems F I F T H E D I T I O N (expanded) The data section of the Pep/9 CPU. 01 8 14 15 22 23 A IR T3 M1 0x00 0x01 LoadCk 23 991 100 16 17 24 25 X T4 M2 0x02 0x03 45 11 18 19 26 27 5 C SP T1 T5 M3 0x04 0x08 67 12 13 20 21 28 29 5 B PC T2 T6 M4 0xF0 0xF6 5 30 31 A CPU registers M5 0xFE 0xFF CBus ABus BBus System bus MARB MARCk MARA MDRCk MDR Copyright © 2017 by Jones & Bartlett Learning, LLC an Ascend Learning Company MDRMux AMux AMux MDRMux CMux ALU 4 ALU CMux Cin CSMux CSMux Cout S SCk Mem C CCk Addr V VCk 0 AndZ Data 0 0 AndZ Z ZCk 0 Zout N NCk MemWrite MemRead 9781284079630_CH12_689_782.indd 693 29/01/16 8:27 am 12.1 Constructing a Level-ISA3 Machine 693 FIGURE 12.2 The data section of the Pep/9 CPU. 01 8 14 15 22 23 A IR T3 M1 0x00 0x01 LoadCk 23 991 100 16 17 24 25 X T4 M2 0x02 0x03 45 11 18 19 26 27 5 C SP T1 T5 M3 0x04 0x08 67 12 13 20 21 28 29 5 B PC T2 T6 M4 0xF0 0xF6 5 30 31 A CPU registers M5 0xFE 0xFF CBus ABus BBus System bus MARB MARCk MARA MDRCk MDR MDRMux AMux AMux MDRMux CMux ALU 4 ALU CMux Cin CSMux CSMux Cout S SCk Mem C CCk Addr V VCk 0 AndZ Data 0 0 AndZ Z ZCk 0 Zout N NCk MemWrite MemRead 9781284079630_CH12_689_782.indd 693 29/01/16 8:27 am Computer Systems F I F T H E D I T I O N The status bits NZVC • Each status bit is a one-bit D flip-flop • Each status bit is available to the control section • The status bits can be sent as the low-order nybble to the left input of CMux and from there to the register bank Copyright © 2017 by Jones & Bartlett Learning, LLC an Ascend Learning Company Computer Systems F I F T H E D I T I O N The shadow carry bit S • Invisible at level ISA3 • Visible at level Mc2 • Used for internal arithmetic operations that should not affect the C bit • Example: PC ← PC + 1 • Selected by CSMux = 1 Copyright © 2017 by Jones & Bartlett Learning, LLC an Ascend Learning Company Computer Systems F I F T H E D I T I O N Setting the status bits • C can be set directly from ALU Cout, and can be the Cin input to the ALU • V and N can be set directly from ALU • Z can be set in one of two ways ‣ If AndZ control signal is 0, Z is set directly from ALU Zout ‣ If AndZ control signal is 1, Z is set as the AND of ALU Zout and Z Copyright © 2017 by Jones & Bartlett Learning, LLC an Ascend Learning Company 696 CHAPTER 12 Computer Organization Computer FIGURE 12 . 3 Systems F I F T H E D I T I O N Figure 12.3 The truth table for the AndZ combinational circuit in Figure 12.2. Input AndZ Z Zout Output 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 through CMux, and f nally back to the bank of 32 registers via CBus. Data from main memory can be injected into the loopCopyright © 2017from by Jones & Bartlettthe Learning, system LLC an Ascend Learningbus, Company through the MDRMux to the MDR. From there, it can go through the AMux, the ALU, and the CMux to any of the CPU registers. To send the content of a CPU register to memory, you can pass it through the ALU via the ABus and AMux, through the CMux and MDRMux into the MDR. From there it can go to the memory subsystem over the system bus. T e control section has 34 control output lines and 12 input lines. T e 34 output lines control the f ow of data around the data section loop and specify the processing that is to occur along the way. T e 12 input lines come from the 8 lines of BBus plus 4 lines from the status bits, which the control section can test for certain conditions. Later in this chapter is a description of how the control section generates the proper control signals. In the following description of the data section, assume for now that you can set the control lines to any desired values for any cycle. The von Neumann Cycle T e heart of the Pep/9 computer is the von Neumann cycle. T e data section in Figure 12 . 2 implements the von Neumann cycle. It really is nothing more than plumbing. In the same way that water in your house runs through the pipes controlled by various faucets and valves, signals (electrons, literally) f ow through the wires of the buses controlled by various multiplexers.
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