Beyond BIOS Developing with the Unified Extensible Firmware Interface

Total Page:16

File Type:pdf, Size:1020Kb

Beyond BIOS Developing with the Unified Extensible Firmware Interface Digital Edition Digital Editions of selected Intel Press books are in addition to and complement the printed books. Click the icon to access information on other essential books for Developers and IT Professionals Visit our website at www.intel.com/intelpress Beyond BIOS Developing with the Unified Extensible Firmware Interface Second Edition Vincent Zimmer Michael Rothman Suresh Marisetty Copyright © 2010 Intel Corporation. All rights reserved. ISBN 13 978-1-934053-29-4 This publication is designed to provide accurate and authoritative information in regard to the subject matter covered. It is sold with the understanding that the publisher is not engaged in professional services. If professional advice or other expert assistance is required, the services of a competent professional person should be sought. Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Intel may make changes to specifications, product descriptions, and plans at any time, without notice. Fictitious names of companies, products, people, characters, and/or data mentioned herein are not intended to represent any real individual, company, product, or event. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Intel, the Intel logo, Celeron, Intel Centrino, Intel NetBurst, Intel Xeon, Itanium, Pentium, MMX, and VTune are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. † Other names and brands may be claimed as the property of others. This book is printed on acid-free paper. Publisher: Richard Bowles Editor: David J. Clark Program Manager: Stuart Douglas Text Design & Composition: InfoPros Graphic Art: Ted Cyrek (cover) InfoPros (illustrations) Library of Congress Cataloging in Publication Data: 10 9 8 7 6 5 4 3 2 1 First printing, November 2010 To my wife Jan, and my daughters Ally and Zoe, without whose love this book would not have been possible. To my parents Stanley and Joann, and my sister Natalie, who have helped me on my journey through life. —Vincent Zimmer To my wife Sandi for having infinite patience in allowing me to find the “spare” time for this endeavor, and to my sons Ryan and Aaron who keep me grounded in what life is really about. —Mike Rothman To my very supporting spouse Anitha, my son Ketan and daughter Manisha for being the source of inspiration in my life. —Suresh Marisetty Contents Contents v Foreword to the First Edition xi Foreword to the Second Edition xv Preface xix Chapter 1 Introduction 1 Terminology 5 A Short History of EFI 6 EFI Becomes UEFI—The UEFI Forum 7 PIWG and USWG 10 Platform Trust/Security 14 Embedded Systems: The New Challenge 17 Summary 19 Chapter 2 Basic UEFI Architecture 21 Objects Managed by UEFI-based Firmware 22 UEFI System Table 22 Handle Database 23 Protocols 26 Working with Protocols 30 Tag GUID 31 v vi n Beyond BIOS: Developing with the Unified Extensible Firmware Interface UEFI Images 31 Events and Task Priority Levels 37 Summary 41 Chapter 3 UEFI Driver Model 43 Why a Driver Model Prior to OS Booting? 44 Driver Initialization 44 Host Bus Controllers 46 Device Drivers 48 Bus Drivers 50 Platform Components 52 Hot Plug Events 53 Additional Innovations 63 Summary 67 Chapter 4 Protocols You Should Know 69 EFI OS Loaders 71 Device Path and Image Information of the OS Loader 74 Accessing Files in the Device Path of the OS Loader 75 Finding the OS Partition 76 Getting the Current System Configuration 77 Getting the Current Memory Map 78 Getting Environment Variables 79 Transitioning to an OS Kernel 80 Summary 81 Chapter 5 UEFI Runtime 83 Isn’t There Only One Kind of Memory? 85 How Are Runtime Services Exposed? 88 Time Services 89 Virtual Memory Services 92 Variable Services 94 Miscellaneous Services 98 Summary 101 Contents n vii Chapter 6 UEFI Console Services 103 Simple Text Input Protocol 106 Simple Text Input Ex Protocol 109 Simple Text Output Protocol 110 Remote Console Support 113 Console Splitter 116 Network Consoles 118 Summary 120 Chapter 7 Different Types of Platforms 121 Summary 138 Chapter 8 DXE Basics: Core, Dispatching, and Drivers 139 DXE Core 141 Global Coherency Domain Services 152 DXE Dispatcher 157 DXE Drivers 162 Boot Device Selection (BDS) Phase 163 Summary 166 Chapter 9 Some Common UEFI and PI Functions 167 Architectural Protocol Examples 168 PCI Protocols 177 Block I/O 188 Disk I/O 190 Simple File System 192 Configuration Infrastructure 194 Using the Configuration Infrastructure 196 Driver Model Interactions 197 Provisioning the Platform 201 Summary 203 viii n Beyond BIOS: Developing with the Unified Extensible Firmware Interface Chapter 10 Platform Security and Trust 205 Trust Overview 206 Trusted Platform Module (TPM) and Measured Boot 209 UEFI Secure Boot 221 UEFI Executable Verification 222 UEFI Networking 224 UEFI User Identification (UID) 227 Hardware Evolution: SRTM-to-DRTM 228 Platform Manufacturer 229 Vulnerability Classification 231 Roots of Trust/Guards 232 Summary 232 Chapter 11 Boot Device Selection 235 Firmware Boot Manager 238 Globally-Defined Variables 242 Default Behavior for Boot Option Variables 245 Boot Mechanisms 246 Summary 248 Chapter 12 Boot Flows 249 Defined Boot Modes 250 Priority of Boot Paths 251 Reset Boot Paths 253 Normal Boot Paths 254 Recovery Paths 257 Special Boot Path Topics 259 Architectural Boot Mode PPIs 264 Recovery 265 Summary 266 Chapter 13 Pre-EFI Initialization (PEI) 267 Scope 268 Rationale 268 Contents n ix Phase Prerequisites 273 Concepts 274 Operation 279 Summary 289 Chapter 14 Putting It All Together—Firmware Emulation 291 Virtual Platform 292 Hardware Pass-Through 300 Summary 302 Chapter 15 Reducing Platform Boot Times 303 Proof of Concept 308 Marketing Requirements 309 Additional Details 315 Summary 320 Chapter 16 Embedded Boot Solution 323 CE Device Landscape 324 CE Device Boot Challenges 325 In-Vehicle Infotainment 328 Other Embedded Platforms 331 Generic Requirements 332 Boot Strategies 335 Power Management 337 Boot Storage Devices 337 Security 340 Manageability 344 Summary 345 Chapter 17 Manageability 347 Overall Management Framework 348 UEFI Error Format Standardization 351 Windows Hardware Error Architecture and the Role of UEFI 358 x n Beyond BIOS: Developing with the Unified Extensible Firmware Interface Technology Intercepts: UEFI, IPMI, Intel® AMT, WS-MAN 364 The UEFI/IPMI/Intel® AMT/WS-MAN Bridge 370 Summary 372 Data Types 373 Status Codes 377 Index 381 Foreword to the First Edition n xi Foreword to the First Edition Beyond BIOS. Those two words began to circulate through the elite firmware architects and developers in the industry standard computing circle around 1998, when Intel, Microsoft, HP and a number of other companies began to lay out the plan for bringing up the first Intel® Itanium® systems. The plan was originally called IBI, the Intel Boot Initiative. Mainstream PCs had been using BIOS ever since the beginning of the IBM PC. Its drawbacks and limitations were magnified in the “big iron” machines based on the Itanium processors. For example, BIOS depends on many of the PC-AT hardware such as the 8254 timer and 8259 interrupt controller, which were not designed to scale to larger servers like the HP Integrity Superdome† servers. Worse, BIOS assumes a 1MB execution memory limit and has very limited memory space to execute the Option ROMs on the add-in cards. BIOS’ 16-bit nature stifles the platform advancement for Itanium systems that are 64-bit based. There have been non-BIOS solutions in the more proprietary vertical integrated systems design, such as Open Firmware used by IBM Power†, SUN SPARC†, and Apple PowerPC†; ARCS† by DEC Alpha, and PDC/IODC† by HP PA-RISC. Open Firmware is Forth-based, it is difficult to find the talent, and its specifications have not kept up with the evolution of the technology. ARCS lacks the driver model to support add-in cards. With BIOS hitting the wall and no clear alternative that can be brought into the industry standard arena, Intel spearheaded the IBI, which at this stage is named Extensible Firmware Interface (EFI), to reflect objective of the effort. EFI brought the modern computer software architectural concepts into firmware. EFI enables firmware development in high-level languages like C, provides proper xii n Beyond BIOS: Developing with the Unified Extensible Firmware Interface abstraction of hardware, and enables extensibility through the GUID concept. The benefits of EFI were so convincing that Microsoft and the industry made it the only boot mechanism for the Itanium-based systems. Now that the IA-32 processors are also extended to 64-bit via Intel® 64, the industry is working on Unified EFI (UEFI) as the standard pre-boot firmware infrastructure going forward. Intel also spearheaded the effort on the Intel Platform Innovation Framework for EFI (Framework). The Framework is Intel’s implementation of EFI, and it is also the starting point for the industry to define the Platform Initialization (PI) specifications that establish the firmware internal interface architecture as well as firmware-to-silicon interfaces that enable silicon driver modularity and interoperability. With Framework’s implementation of UEFI and PI, Intel has completed the task of replacing BIOS, thus enabling the industry to move beyond BIOS. This book is a landmark in the development of the UEFI and PI firmware. It couples a powerful, modern firmware infrastructure with a unique look into the mind of a few UEFI/PI architects who have made the Framework implementation into reality and as a reference.
Recommended publications
  • Enabling RUST for UEFI Firmware
    presented by Enabling RUST for UEFI Firmware UEFI 2020 Virtual Plugfest August 20, 2020 Jiewen Yao & Vincent Zimmer, Intel Corporation www.uefi.org 1 Jiewen Yao • Jiewen Yao is a principal engineer in the Intel Architecture, Graphics, and Software Group. He has been engaged as a firmware developer for over 15 years. He is a member of the UEFI Security sub team, and the TCG PC Client sub working group. www.uefi.org 2 Vincent Zimmer • Vincent Zimmer is a senior principal engineer in the Intel Architecture, Graphics, and Software Group. He has been engaged as a firmware developer for over 25 years and leads the UEFI Security sub team. www.uefi.org 3 Agenda • EDKII Security Summary • RUST Language • Enabling RUST for EDKII • Summary / Call to Action www.uefi.org 4 EDKII Security Summary www.uefi.org 5 BIOS Memory Issue in Hack Conf www.uefi.org 6 BIOS Security Bug Top Issue Open Source Close Source Buffer Overflow/ 50% 38% Integer Overflow SMM 7% 18% Variable 8% 5% Register Lock 3% 10% www.uefi.org 7 Vulnerabilities in C/C++ Source: Trends, challenges, and strategic shifts in the software vulnerability mitigation landscape – Microsoft, Bluehat IL 2019 www.uefi.org 8 Firmware as Software • Many software issues are also firmware issues. – Buffer Overflow – Integer Overflow – Uninitialized Variable • Software mitigation can be used for firmware mitigation. – (See next page) www.uefi.org 9 3 Levels of Prevention Prevention Method EDKII Open Source Example Eliminate Reduce Attack Surface SMI Handler Profile Vulnerability Static Analysis / Dynamic
    [Show full text]
  • Intel Advisor for Dgpu Intel® Advisor Workflows
    Profile DPC++ and GPU workload performance Intel® VTune™ Profiler, Advisor Vladimir Tsymbal, Technical Consulting Engineer, Intel, IAGS Agenda • Introduction to GPU programming model • Overview of GPU Analysis in Intel® VTune Profiler • Offload Performance Tuning • GPU Compute/Media Hotspots • A DPC++ Code Sample Analysis Demo • Using Intel® Advisor to increase performance • Offload Advisor discrete GPUs • GPU Roofline for discrete GPUs Copyright © 2020, Intel Corporation. All rights reserved. *Other names and brands may be claimed as the property of others. 2 Intel GPUs and Programming Model Gen9 Application Workloads • Most common Optimized Middleware & Frameworks in mobile, desktop and Intel oneAPI Product workstations Intel® Media SDK Direct Direct API-Based Gen11 Programming Programming Programming • Data Parallel Mobile OpenCL platforms with C API C++ Libraries Ice Lake CPU Gen12 Low-Level Hardware Interface • Intel Xe-LP GPU • Tiger Lake CPU Copyright © 2020, Intel Corporation. All rights reserved. *Other names and brands may be claimed as the property of others. 3 GPU Application Analysis GPU Compute/Media Hotspots • Visibility into both host and GPU sides • HW-events based performance tuning methodology • Provides overtime and aggregated views GPU In-kernel Profiling • GPU source/instruction level profiling • SW instrumentation • Two modes: Basic Block latency and memory access latency Identify GPU occupancy and which kernel to profile. Tune a kernel on a fine grain level Copyright © 2020, Intel Corporation. All rights reserved. *Other names and brands may be claimed as the property of others. 4 GPU Analysis: Aggregated and Overtime Views Copyright © 2020, Intel Corporation. All rights reserved. *Other names and brands may be claimed as the property of others.
    [Show full text]
  • Uefi وبعض أنظمة Bios Uefi واجهة الربنامج الثابت املوحدة والقابلة للتمديد
    - جدول أقسامGUID GUID Partition Table جدول أقسام )أو تقسيم( يستخدم املعرفات الفريدة العميمة "! G % تعري. و-يي, ا+قسام *( ال)'ي& املقسم % أ$#مة !0/ و2ع1 أ$#مة 45!3 UEFI واج=ة ال>$ا;: ال9ا82 امل)7دة والقا62ة ل6تمديد مس جد? % ;<رم ّو@B @AA دة 'Cتمرب/أي6)ل DE@F2 " F جدول أقسام GUID *باIة *H تخGيط )أو تقسيم( جدول أقسام ;عياJI *( أج=,ة التخ,يH الفي,ياKيةM9; L ا+قراN الثا2تةL أو أقراN الحالة الC6OةPQ Lا التخGيط يستخدم املعرR الفريد العميم U@TS % متيي, ا+قسام وأ$)ا*هاL وXIم أ$W ج,H; V ;عياI واج=ة ال>نا;: الثا82 امل)حدة والقا62ة ل6تمديد !U ZD S YL /0 )املق^[ ;H ;\تد] h _`abc /0! 0defgبديM ل6\ظام التق6يدJ 45!3( $ظام Hlm GPj ا'تخدا;W أيضا % 2ع1 أ$#مة 45!3 بسnC ;حدو?ية جدول أقسام Lo3p الذJ يستخدم 82qTD فقط % تخ,يH ;ع6)مات ال<rم و*ناويr7 v; us3t Hم القGاw التق6يدqx@D Jبايu8 ;ع#م أ$#مة التشyيM تد*م P\; LGPj العام LDE@E 2ع1 ا+$#مة ;M9 ما{ أوu|} ومايكرو')ف8 ويندو~ )x86( تد*م فقط اإلقالH; w أقسام GPj % أ$#مة !L /0!B/0 2ي\ام ;ع#م ت)~يعات لي\lس و ت)~يعات 2ريhيل ي)$lس ;M9 فرJ يب |} ?lm J\ها اإلقالH; w أقسام GPj % أج=,ة 45!3 أو أج=,ة !u /0 6A TD % ا+قراN الثا2تة التي تستخدم r7م القطاw املعياx@D JI بايL8 ال<rم ا+قىص ل6قرN با'تخدام DuD (Q o3p ترياباي8 أو ) x@D × D بايuU @ S )8 2ي\ام ال<rم ا+قىص ل6قرN با'تخدام GPj 'يك)ن FuA ~يتاباي8 أو ) x@D × D بايU T S U @ S )8 والسnC % ذلك ا'تخدام H; 82 6A أجM *ناويH الكتM امل\Gقية % جدول أقسام u GPj تاIيخياL رشhة |$تي LM كا$8 وIاV تG)ير LGPj أواخر التسعينات )L)DEEE الذJ أصCح ج,H; V ;)اصفة !U D S Y /0 % عام DE@E وت<8 |?اIة Qيئة خاصة تد*ى !P\; u _`abc /0 عام uDEEF قطاعات GPT % عام LDE@E *ندما بدأ ;\تr)ن ا+قراN الثا2تة الت<)ل |ىل ت)ظي.
    [Show full text]
  • Sistemi Operativi Real-Time Marco Cesati Lezione R13 Sistemi Operativi Real-Time – II Schema Della Lezione
    Sistemi operativi real-time Marco Cesati Lezione R13 Sistemi operativi real-time – II Schema della lezione Caratteristiche comuni VxWorks LynxOS Sistemi embedded e real-time QNX eCos Windows Linux come RTOS 15 gennaio 2013 Marco Cesati Dipartimento di Ingegneria Civile e Ingegneria Informatica Università degli Studi di Roma Tor Vergata SERT’13 R13.1 Sistemi operativi Di cosa parliamo in questa lezione? real-time Marco Cesati In questa lezione descriviamo brevemente alcuni dei più diffusi sistemi operativi real-time Schema della lezione Caratteristiche comuni VxWorks LynxOS 1 Caratteristiche comuni degli RTOS QNX 2 VxWorks eCos 3 LynxOS Windows Linux come RTOS 4 QNX Neutrino 5 eCos 6 Windows Embedded CE 7 Linux come RTOS SERT’13 R13.2 Sistemi operativi Caratteristiche comuni dei principali RTOS real-time Marco Cesati Corrispondenza agli standard: generalmente le API sono proprietarie, ma gli RTOS offrono anche compatibilità (compliancy) o conformità (conformancy) allo standard Real-Time POSIX Modularità e Scalabilità: il kernel ha una dimensione Schema della lezione Caratteristiche comuni (footprint) ridotta e le sue funzionalità sono configurabili VxWorks Dimensione del codice: spesso basati su microkernel LynxOS QNX Velocità e Efficienza: basso overhead per cambi di eCos contesto, latenza delle interruzioni e primitive di Windows sincronizzazione Linux come RTOS Porzioni di codice non interrompibile: generalmente molto corte e di durata predicibile Gestione delle interruzioni “separata”: interrupt handler corto e predicibile, ISR lunga
    [Show full text]
  • Hands-On Intel® Software Development & Oneapi WORKSHOP
    Hands-on Intel® Software Development & oneAPI WORKSHOP May 26-27, 2020 Scandic Solli, Parkveien 68 Box 2458 Solli, 0202 Oslo AGENDA DAY 1 - Technical Computing & Developer Tools - May 26 Timing Sessions 08:30 – 09:00 Registration & Light breakfast Part 1: Coding for maximum performance using the new Intel® Parallel Studio XE 2020 A refresher on the Intel® Hardware Architecture for Software Developers and Architects This session will offer in-depth insights into the current and future Intel® hardware platforms tailored to the 09:00 -09:45 needs of software developers, software architects, HPC and AI experts. We will cover the latest Intel® processors and the future Intel® GPU architecture. Developing code for Intel® architecture: how to achieve maximum performance using the new Intel® Parallel Studio XE 2020 09:45 – 10:30 Learn how Intel® Software Development Tools will help you to achieve optimal performance in your High Performance Computing, Artificial Intelligence ,and IoT projects. Includes a look at the new Intel® Parallel Studio XE 2020 tools which are designed to take advantage of the latest generation of Intel processors. 10:30 – 11:00 Coffee Break How to optimize and maximize code performance Learn how to use some of the advanced features of Intel® VTune™ Amplifier profile your applications. See how you can use event-based and architectural analysis to fine-tune your code so that it is taking full 11:00 – 12:00 advantage of the latest processor features of the target CPU. Learn how to use Intel Advisor, a powerful tool for tracking down and solving vectorization problems. In this session we will demonstrate how the Intel Advisor vector analysis and associated Roofline Model can be used to identify and help fixing vectorization problems.
    [Show full text]
  • Software Engineering a Abnormal End: Abend Abnormaal Einde De Beëindiging Van Een Proces Voordat Dat Proces Geheel Is Afgewerkt
    1 Verklarende terminologielijst voor de Software Engineering A abnormal end: abend abnormaal einde De beëindiging van een proces voordat dat proces geheel is afgewerkt. abort (to) afbreken Een proces afbreken voordat het volledig is afgewerkt. absolute address absoluut adres Een adres dat permanent aan een eenheid of geheugenplaats is toegewezen en dat de eenheid of de geheugenplaats identificeert zonder dat daarvoor een vertaling of berekening nodig is. absolute assembler absoluut assembleerprogramma Een assembleerprogramma dat uitsluitend absolute code genereert. absolute code absolute code Code waarin alle adressen absoluut zijn. absolute coding absolute codering Een coderingsmethode waarin gebruik wordt gemaakt van instructies die absolute adressen bevatten. absolute expression absolute uitdrukking Een uitdrukking voorafgaande aan het moment waarop het assembleren van een programma plaatsvindt. Dit moment wordt niet beïnvloed door het verplaatsen van het programma. Een absolute uitdrukking kan een absoluut adres in een assembleertaal weergeven. absolute instruction absolute instructie 1. Een instructie in de definitieve uitvoerbare vorm. 2. Een computerinstructie waarin alle adressen uit absolute adressen bestaan. absolute loader absoluut laadprogramma Een programma dat een ander programma in het hoofdgeheugen kan plaatsen. Dit begint bij het initiële adres dat aan de code door het assembleerprogramma of de compiler is toegewezen en dat de adressen in de code niet verder wijzigt of aanpast. absolute load module absolute laadmodule 2 Een combinatie van werkmodules die op een gespecificeerd adres in het werkgeheugen wordt uitgevoerd. absolute machine code absolute machinecode Machinecode die steeds in vaste geheugenplaatsen moet worden geladen en niet mag worden verplaatst. Dit in tegenstelling tot verplaatsbare machinecode. absolute pathname absolute padnaam Een padnaam die de informatie bevat over de wijze waarop een bestand kan worden gevonden.
    [Show full text]
  • Evaluating Techniques for Parallelization Tuning in MPI, Ompss and MPI/Ompss
    Evaluating techniques for parallelization tuning in MPI, OmpSs and MPI/OmpSs Advisors: Author: Prof. Jesús Labarta Vladimir Subotic´ Prof. Mateo Valero Prof. Eduard Ayguade´ A THESIS SUBMITTED IN FULFILMENT OF THE REQUIREMENTS FOR THE DEGREE OF Doctor per la Universitat Politècnica de Catalunya Departament d’Arquitectura de Computadors Barcelona, 2013 i Abstract Parallel programming is used to partition a computational problem among multiple processing units and to define how they interact (communicate and synchronize) in order to guarantee the correct result. The performance that is achieved when executing the parallel program on a parallel architec- ture is usually far from the optimal: computation unbalance and excessive interaction among processing units often cause lost cycles, reducing the efficiency of parallel computation. In this thesis we propose techniques oriented to better exploit parallelism in parallel applications, with especial emphasis in techniques that increase asynchronism. Theoretically, this type of parallelization tuning promises multiple benefits. First, it should mitigate communication and synchro- nization delays, thus increasing the overall performance. Furthermore, parallelization tuning should expose additional parallelism and therefore increase the scalability of execution. Finally, increased asynchronism would allow more flexible communication mechanisms, providing higher toler- ance to slower networks and external noise. In the first part of this thesis, we study the potential for tuning MPI par- allelism. More specifically, we explore automatic techniques to overlap communication and computation. We propose a speculative messaging technique that increases the overlap and requires no changes of the orig- inal MPI application. Our technique automatically identifies the applica- tion’s MPI activity and reinterprets that activity using optimally placed non-blocking MPI requests.
    [Show full text]
  • Class-Action Lawsuit
    Case 3:20-cv-00863-SI Document 1 Filed 05/29/20 Page 1 of 279 Steve D. Larson, OSB No. 863540 Email: [email protected] Jennifer S. Wagner, OSB No. 024470 Email: [email protected] STOLL STOLL BERNE LOKTING & SHLACHTER P.C. 209 SW Oak Street, Suite 500 Portland, Oregon 97204 Telephone: (503) 227-1600 Attorneys for Plaintiffs [Additional Counsel Listed on Signature Page.] UNITED STATES DISTRICT COURT DISTRICT OF OREGON PORTLAND DIVISION BLUE PEAK HOSTING, LLC, PAMELA Case No. GREEN, TITI RICAFORT, MARGARITE SIMPSON, and MICHAEL NELSON, on behalf of CLASS ACTION ALLEGATION themselves and all others similarly situated, COMPLAINT Plaintiffs, DEMAND FOR JURY TRIAL v. INTEL CORPORATION, a Delaware corporation, Defendant. CLASS ACTION ALLEGATION COMPLAINT Case 3:20-cv-00863-SI Document 1 Filed 05/29/20 Page 2 of 279 Plaintiffs Blue Peak Hosting, LLC, Pamela Green, Titi Ricafort, Margarite Sampson, and Michael Nelson, individually and on behalf of the members of the Class defined below, allege the following against Defendant Intel Corporation (“Intel” or “the Company”), based upon personal knowledge with respect to themselves and on information and belief derived from, among other things, the investigation of counsel and review of public documents as to all other matters. INTRODUCTION 1. Despite Intel’s intentional concealment of specific design choices that it long knew rendered its central processing units (“CPUs” or “processors”) unsecure, it was only in January 2018 that it was first revealed to the public that Intel’s CPUs have significant security vulnerabilities that gave unauthorized program instructions access to protected data. 2. A CPU is the “brain” in every computer and mobile device and processes all of the essential applications, including the handling of confidential information such as passwords and encryption keys.
    [Show full text]
  • Designing PCI Cards and Drivers for Power Macintosh Computers
    Designing PCI Cards and Drivers for Power Macintosh Computers Revised Edition Revised 3/26/99 Technical Publications © Apple Computer, Inc. 1999 Apple Computer, Inc. Adobe, Acrobat, and PostScript are Even though Apple has reviewed this © 1995, 1996 , 1999 Apple Computer, trademarks of Adobe Systems manual, APPLE MAKES NO Inc. All rights reserved. Incorporated or its subsidiaries and WARRANTY OR REPRESENTATION, EITHER EXPRESS OR IMPLIED, WITH No part of this publication may be may be registered in certain RESPECT TO THIS MANUAL, ITS reproduced, stored in a retrieval jurisdictions. QUALITY, ACCURACY, system, or transmitted, in any form America Online is a service mark of MERCHANTABILITY, OR FITNESS or by any means, mechanical, Quantum Computer Services, Inc. FOR A PARTICULAR PURPOSE. AS A electronic, photocopying, recording, Code Warrior is a trademark of RESULT, THIS MANUAL IS SOLD “AS or otherwise, without prior written Metrowerks. IS,” AND YOU, THE PURCHASER, ARE permission of Apple Computer, Inc., CompuServe is a registered ASSUMING THE ENTIRE RISK AS TO except to make a backup copy of any trademark of CompuServe, Inc. ITS QUALITY AND ACCURACY. documentation provided on Ethernet is a registered trademark of CD-ROM. IN NO EVENT WILL APPLE BE LIABLE Xerox Corporation. The Apple logo is a trademark of FOR DIRECT, INDIRECT, SPECIAL, FrameMaker is a registered Apple Computer, Inc. INCIDENTAL, OR CONSEQUENTIAL trademark of Frame Technology Use of the “keyboard” Apple logo DAMAGES RESULTING FROM ANY Corporation. (Option-Shift-K) for commercial DEFECT OR INACCURACY IN THIS purposes without the prior written Helvetica and Palatino are registered MANUAL, even if advised of the consent of Apple may constitute trademarks of Linotype-Hell AG possibility of such damages.
    [Show full text]
  • Chapter 1. Origins of Mac OS X
    1 Chapter 1. Origins of Mac OS X "Most ideas come from previous ideas." Alan Curtis Kay The Mac OS X operating system represents a rather successful coming together of paradigms, ideologies, and technologies that have often resisted each other in the past. A good example is the cordial relationship that exists between the command-line and graphical interfaces in Mac OS X. The system is a result of the trials and tribulations of Apple and NeXT, as well as their user and developer communities. Mac OS X exemplifies how a capable system can result from the direct or indirect efforts of corporations, academic and research communities, the Open Source and Free Software movements, and, of course, individuals. Apple has been around since 1976, and many accounts of its history have been told. If the story of Apple as a company is fascinating, so is the technical history of Apple's operating systems. In this chapter,[1] we will trace the history of Mac OS X, discussing several technologies whose confluence eventually led to the modern-day Apple operating system. [1] This book's accompanying web site (www.osxbook.com) provides a more detailed technical history of all of Apple's operating systems. 1 2 2 1 1.1. Apple's Quest for the[2] Operating System [2] Whereas the word "the" is used here to designate prominence and desirability, it is an interesting coincidence that "THE" was the name of a multiprogramming system described by Edsger W. Dijkstra in a 1968 paper. It was March 1988. The Macintosh had been around for four years.
    [Show full text]
  • Micron Technology, Wave Systems, Lenovo and American Megatrends Inc
    October 28, 2014 Micron Technology, Wave Systems, Lenovo and American Megatrends Inc. Announce Intention to Create New Industry Standard to Meet Heightened Global Security Requirements Companies Will Collaborate to Strengthen Core Root of Trust for Measurement for the Enterprise Supply Chain BOISE, Idaho, Oct. 28, 2014 (GLOBE NEWSWIRE) -- Micron Technology, Inc. (Nasdaq:MU), a global leader in advanced semiconductor systems, and Wave Systems Corp. (Nasdaq:WAVX), a leading provider of endpoint security, today announced they intend to expand their collaboration to include Lenovo (HKSE:992) (ADR:LNVGY) and American Megatrends Inc. (AMI). Together, the four companies plan to develop advanced enterprise-class security offerings to address the escalating concerns of governments and multinational businesses. To meet the overall objective of verifying and securing software components, these solutions will significantly strengthen the Core Root of Trust for Measurement (CRTM) to offer best-in-class protection against current and emerging pre-boot threats within the supply chain. The companies intend for these solutions to form the basis of a new industry standard designed to ensure the integrity of the supply chain. According to the 2014 Verizon DBIR report, supply chain vulnerabilities and third-party vendors are still a leading cause of enterprise data breaches (Source, Verizon DBIR, 2014). With major brands continually leaking sensitive enterprise data, it is becoming even more critical to architect a comprehensive enterprise security suite that protects memory content from its inception in manufacturing throughout a computing device's life cycle. By providing verification of the CRTM, the first BIOS code that executes, the security of system measurements can be ensured rather than implicitly trusted, reducing the risk of supply chain attacks.
    [Show full text]
  • Precise Null Pointer Analysis Through Global Value Numbering
    Precise Null Pointer Analysis Through Global Value Numbering Ankush Das1 and Akash Lal2 1 Carnegie Mellon University, Pittsburgh, PA, USA 2 Microsoft Research, Bangalore, India Abstract. Precise analysis of pointer information plays an important role in many static analysis tools. The precision, however, must be bal- anced against the scalability of the analysis. This paper focusses on improving the precision of standard context and flow insensitive alias analysis algorithms at a low scalability cost. In particular, we present a semantics-preserving program transformation that drastically improves the precision of existing analyses when deciding if a pointer can alias Null. Our program transformation is based on Global Value Number- ing, a scheme inspired from compiler optimization literature. It allows even a flow-insensitive analysis to make use of branch conditions such as checking if a pointer is Null and gain precision. We perform experiments on real-world code and show that the transformation improves precision (in terms of the number of dereferences proved safe) from 86.56% to 98.05%, while incurring a small overhead in the running time. Keywords: Alias Analysis, Global Value Numbering, Static Single As- signment, Null Pointer Analysis 1 Introduction Detecting and eliminating null-pointer exceptions is an important step towards developing reliable systems. Static analysis tools that look for null-pointer ex- ceptions typically employ techniques based on alias analysis to detect possible aliasing between pointers. Two pointer-valued variables are said to alias if they hold the same memory location during runtime. Statically, aliasing can be de- cided in two ways: (a) may-alias [1], where two pointers are said to may-alias if they can point to the same memory location under some possible execution, and (b) must-alias [27], where two pointers are said to must-alias if they always point to the same memory location under all possible executions.
    [Show full text]