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University of Cape Town Declaration The copyright of this thesis vests in the author. No quotation from it or information derived from it is to be published without full acknowledgementTown of the source. The thesis is to be used for private study or non- commercial research purposes only. Cape Published by the University ofof Cape Town (UCT) in terms of the non-exclusive license granted to UCT by the author. University Automated Gateware Discovery Using Open Firmware Shanly Rajan Supervisor: Prof. M.R. Inggs Co-supervisor: Dr M. Welz University of Cape Town Declaration I understand the meaning of plagiarism and declare that all work in the dissertation, save for that which is properly acknowledged, is my own. It is being submitted for the degree of Master of Science in Engineering in the University of Cape Town. It has not been submitted before for any degree or examination in any other university. Signature of Author . Cape Town South Africa May 12, 2013 University of Cape Town i Abstract This dissertation describes the design and implementation of a mechanism that automates gateware1 device detection for reconfigurable hardware. The research facilitates the pro- cess of identifying and operating on gateware images by extending the existing infrastruc- ture of probing devices in traditional software by using the chosen technology. An automated gateware detection mechanism was devised in an effort to build a software system with the goal to improve performance and reduce software development time spent on operating gateware pieces by reusing existing device drivers in the framework of the chosen technology. This dissertation first investigates the system design to see how each of the user specifica- tions set for the KAT (Karoo Array Telescope) project in [28] could be achieved in terms of design decisions, toolchain selection and software modifications. The final design satisfies the user specifications by treating the gateware programmed on reconfigurable hardware just like any other physical device attached to the system, extending the device database available to bootloader, mapping kernel device driver to operate on the gateware programmed and allowing the user to run suitable applications based on the personality of the gateware image programmed. The system implementation is then described and issues related to the process of integrating gateware, bootloader and kernel interfaces are discussed. The resultsUniversity of tests conducted onof the actualCape hardware Town demonstrating the overall concept are presented. Conclusions are drawn based on these results and suggestions for future work and design improvements are recommended. 1Gateware is a University of California, Berkeley coined term for design logic that goes into the FPGA ii To The Lord Almighty, my family, friends for all their support and guidance. If not for all of you, I would not be the man I am today. University of Cape Town iii Acknowledgements I would like to thank the following parties for their assistance and involvement in the completion of this project: • My supervisor, Prof Mike Inggs who believed in me as a professional and gave me the freedom and space to research at my own pace. A special thanks for his valuable time for reading through the draft of this dissertation and recommending corrections. • My cosupervisor, Dr Marc Welz who has been instrumental in the success of this research. His valuable advice, steadfast support and kind words has been of im- mense value during the tenure of this research. A special thanks for his time for reading through and recommending corrections to the draft of this dissertation. • Dr Alan Langman for providing the initial support and advice for the research. • The SKA / KAT bursary programme for providing funding for this research. • The entire DBE Team which i regard and respect as a family, ably led by Mr Fran- cois Kapp. A special thanks to Mr Andrew Martens and Mr David George for assisting me with inputs for the design stages. University of Cape Town • My family and friends for their love and encouragement throughout the project. • My wife, Bifin Shanly, who has been very instrumental in providing a peaceful family atmosphere so that i could focus on my research. iv Contents Declaration i Abstract ii Acknowledgements iv Nomenclature xiii 1 Introduction 1 1.1 Background of Investigation . 1 1.2 Project Motivation . 2 1.3 Project Scope . 2 1.4 Objectives . 3 1.5 DissertationUniversity Overview . .of . .Cape . .Town . 3 2 Background 9 2.1 Device detection in conventional computer platforms . 10 2.1.1 PCI (Peripheral Component Interconnect) . 10 2.1.1.1 Brief history . 10 2.1.1.2 Overview . 10 2.1.1.3 Device Detection . 12 2.1.2 ACPI (Advanced Configuration and Power Interface) . 12 v 2.1.2.1 Brief history . 12 2.1.2.2 Overview . 13 2.1.2.3 Device Detection . 14 2.1.3 OF (Open Firmware) . 15 2.1.3.1 Brief history . 15 2.1.3.2 Overview . 15 2.1.3.3 Device Detection . 17 2.1.4 Summary . 18 2.2 Device detection in FPGA-based software systems . 20 2.2.1 Related Studies . 20 2.2.2 Linux . 21 2.2.2.1 Background . 21 2.2.2.2 Overview . 22 2.2.2.3 Features . 23 2.2.2.4 Device Detection in Linux . 24 2.2.3 BORPH . 24 2.2.3.1 Background . 24 University of Cape Town 2.2.3.2 Overview . 24 2.2.3.3 Features . 26 2.2.3.4 Device Detection in BORPH . 27 2.2.4 Summary . 27 2.3 Chapter Summary . 29 vi 3 Design 31 3.1 Design Constraints . 32 3.2 Design Choices . 32 3.3 Design Methodology . 35 3.4 System Architecture . 36 3.5 System Design . 38 3.5.1 System Overview . 38 3.5.1.1 System Connection Diagram . 38 3.5.1.2 AMCC PowerPC Architecture . 39 3.5.2 FPGA Programming Design . 41 3.5.2.1 From U-Boot . 44 3.5.2.2 From linux . 45 3.5.3 Gateware Design . 46 3.5.3.1 Gateware Toolflow . 46 3.5.3.2 Gateware Support . 47 3.5.4 Device Detection Design . 52 3.5.4.1 From U-Boot . 53 3.5.4.2University From Linux .of . .Cape . .Town . 55 3.5.5 Design Optimisations . 58 3.5.5.1 Memory mapped device driver . 58 3.6 Chapter Summary . 59 4 Implementation and Results 61 4.1 Embedded Development Setup . 62 4.2 High level implementation block diagram . 64 4.3 Gateware implementation . 65 vii 4.3.1 Serial loopback implementation . 66 4.3.2 Simple data capture implementation . 67 4.4 Device description . 69 4.5 Device discovery and enumeration . 71 4.6 Device operation and control . 75 4.6.1 Device Drivers . 75 4.6.2 Userspace Applications . 79 4.7 Chapter Summary . 81 5 Conclusions and Future Directions 83 5.1 Summary . 83 5.2 Conclusions . 83 5.3 Dissemination Strategy . 84 5.4 Recommendations for future work . 84 A Source Code 86 B ROACH Board Connections 87 C DTC CompilerUniversity Usage of Cape Town 89 Bibliography 90 viii List of Figures 1.1 Device detection overview . 5 2.1 Layout of a typical PCI system [23] . 10 2.2 PCI configuration header [23] . 11 2.3 ACPI system architecture . 13 2.4 ACPI device detection . 14 2.5 Open Firmware internal and external interfaces . 16 2.6 Open Firmware probe and detection . 17 2.7 Recent operating systems for FPGAs [32] . 20 2.8 Linux kernel overview [23] . 22 2.9 High level overview of GNU / Linux [27] . 23 2.10 High level block diagram of BORPH [16] . 25 2.11 BORPHUniversity [5] . .of . .Cape . .Town . 26 2.12 Results of test conducted between BORPH and Linux device driver with memory mapped support . 28 3.1 Linux and BORPH operating system flow diagram . 33 3.2 Design steps to reach the final system . 35 3.3 Automated gateware discovery system architecture . 37 3.4 System connectivity diagram . 38 3.5 PPC440EPx functional block diagram [4] . 40 ix 3.6 Slave configuration modes [44] . 41 3.7 SelectMAP Configuration Flow Chart . 42 3.8 FPGA-PowerPC SelectMAP programming interface . 43 3.9 Programming FPGA from U-Boot using SelectMAP interface . 44 3.10 Character device driver for FPGA programming . 45 3.11 MSSGE toolflow diagram for CASPER hardware . 46 3.12 UARTLite serial OPB core connectivity in EDK . 48 3.13 Graphical representation of sound card design using iADC in Simulink . 50 3.14 Graphical representation of PPC440EPx device tree . 52 3.15 Graphical representation of ROACH device tree . 54 3.16 Device tree usage and detection in Linux . 56 3.17 Memory mapping FPGA . 58 4.1 Cross-development setup for ROACH . 62 4.2 U-Boot port changes for ROACH2 . 63 4.3 High level implementation block diagram of automated gateware discov- ery mechanism using OF .......................... 64 4.4 Gateware connections to PowerPC, buses and FPGA . 65 4.5 Serial designUniversity running on PowerPC of and Cape FPGA . .Town . 66 4.6 PowerPC-FPGA interface for sound capture design..
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